JPS62274780A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce short-channel effect in a semiconductor device and improve the device in its back-gate feature by a method wherein source and drain regions of one conductivity type are provided respectively in opposite-conductivity islands of high impurity concentration. CONSTITUTION:A P-channel MOS transistor 10 is constituted of a source region 3A, drain region 3B, gate oxide film 4, and gate electrode 5, which are P-type impurity layers formed on an N-type semiconductor substrate 1. As for the source region 3A and drain region 3B, they are formed in their respective N<+>- type diffusion islands 2. In the source region 3A and drain region 3B, lateral diffusion at their shallow portions are similar to that in their deeper portions, and lateral expansion in their structures is smaller than that in a conventional design. In this way, the device may be greatly improved in its short-channel effect, and in its back-gate feature, etc., because there is no N<+>-type well layer that is required in a conventional structure.

Description

[Detailed description of the invention] 3. Detailed description of the invention [Industrial application field] The present invention relates to a semiconductor device.

[Conventional technology]

As is well known, semiconductor integrated circuits have been made into LSIs, and the semiconductor elements constituting them are required to be increasingly miniaturized. Among the various problems associated with miniaturization, MO8 is a typical one.
There is a short channel effect due to the short channel of semiconductor devices.

In particular, it is well known that the lateral spread of diffusion in the P-type diffusion layer that becomes the source and drain regions of a P-channel MO8 transistor is greater than that of the N-type diffusion layer that becomes the source and drain region of an N-channel MOS transistor due to the high-temperature salt treatment process. It is as follows. Also, P channel MO8 to 9
It is also well known that when the N-type substrate impurity concentration in the transistor formation region is low, this lateral spread becomes large.

Conventionally, this lateral spread often causes punch-through between the source region and the drain region, causes the threshold voltage to completely fluctuate, and otherwise destabilizes the electrical characteristics. Therefore, in these days when there is a demand for shorter channels, the above-mentioned lateral spread becomes an important problem.

There are ways to completely eliminate this problem, such as reducing the amount of ions implanted or lowering the ion implantation acceleration voltage when implanting ions into the source/drain region. New problems arise that adversely affect the electrical characteristics, such as a decrease in the saturation current of the MOS transistor (high layer resistance in the in-region) and a decrease in the saturation current of the MOS transistor. Furthermore, the method of lowering the accelerating voltage is often limited by the device, with a limit of about 30 keys.

There are other methods such as heat treatment to lower the temperature, but since a PSG film is used as the interlayer film covering the gate electrode and flattening is important, it is impossible to lower the temperature below 950'C. However, reliability problems such as disconnection of wiring in the upper layer of the interlayer film often occur.

Therefore, conventionally, as shown in FIG.
In the case of an 8 transistor 1o, an N+ type well layer 9 with a high impurity concentration is formed in the N type semiconductor substrate 1 or an N type epitaxial layer in the element formation region, and the source region 3A and drain region 3B made of a P type diffusion layer are expanded laterally. methods were used to suppress this.

Similarly, as shown in FIG. 4, for the N-channel MOS transistor 20, a P-type well layer 11 with a high impurity concentration is formed, and a source region 7 made of an N-type diffusion layer is formed.
A method of suppressing the lateral expansion of the drain region 7B and the drain region 7B has been used.

[Problem that the invention seeks to solve]

In the semiconductor device having the conventional structure described above, the short channel effect can be suppressed in devices used on the high threshold voltage side, but the N+ type well layer is suppressed in devices used on the low threshold voltage side. 9-! Otherwise, it is necessary to lower the surface impurity concentration of the P+ type well layer 11, and it is difficult to suppress the lateral spread of diffusion in the shallow portions of the source/drain regions.

Furthermore, there is also the problem that increasing the impurity concentration in each well layer deteriorates back gate characteristics, which adversely affects electrical characteristics.

An object of the present invention is to provide a semiconductor device that suppresses lateral expansion of source and drain regions, reduces short channel effects, and improves back gate characteristics.

[Means for solving problems]

A semiconductor device of the present invention includes a source region and a drain region formed on a semiconductor substrate and made of an impurity layer of one conductivity type;
A semiconductor device having a MOS transistor including a gate oxide film formed between the source region and the drain region and a gate electrode formed on the gate oxide film, wherein the source region and the drain region are separated from each other. It is formed within a highly concentrated impurity layer island of opposite conductivity type.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of the present invention, and shows the case where the present invention is applied to a P-channel MO8 transistor.

In FIG. 1, a P-channel MO8 transistor 10 is composed of a source region 3A made of a P-type impurity layer formed on an N-type semicircular substrate 1, a drain region 3B, a gate oxide film 4, and a gate electrode 5. There is. Soshi 1,
In particular, the source region 3A and the drain region 3B are formed in separate dovetail-shaped diffusion layer islands 2, respectively.

In this embodiment constructed in this manner, the lateral spread of diffusion in the shallow portions of the three source regions and the drain region 3B is the same as that in the deep portions, and the lateral spread of the diffusion in the shallow portions of the three source regions and the drain region 3B is the same as that in the deep portions, and that of the conventional structure shown in FIG. It can be made smaller than the width. Therefore, short channel effects can be significantly improved. Furthermore, since the N+ type well layer in the conventional structure is not required, back gate characteristics and the like are also improved.

It shows that the

In this second embodiment as well, a source region 7A and a drain region 7B made of an N-type impurity layer constituting an N-channel MOS transistor 20 are located within a P+ type diffusion island 6 provided in a P-type well layer 8. Because of this, the lateral spread 9 becomes smaller as in the case of FIG.

〔Effect of the invention〕

As explained above, the present invention reduces the short channel effect of a semiconductor device by forming source regions and drain regions of -4 conductivity type in separate high-concentration impurity layer islands of opposite conductivity type. This has the effect of improving back gate characteristics.

[Brief explanation of drawings]

1 and 2 are sectional views of first and second embodiments of the present invention, and FIGS. 3 and 4 are sectional views of a conventional semiconductor device. 1...N-type semiconductor substrate, 2...-N+ type diffusion layer island, 3A
... Source region, 3B... Drain region, 4...
Gate oxide film, 5... Gate electrode, 6... Door-shaped diffusion layer island, 7... Source region, 7B... Drain region, 8
...P-type well layer, 9...N+ type tauwell layer 10...
・P-channel MO8 transistor, 11...P ten-type well layer, 20...N-channel MO8 transistor. Preliminary drawing 1 Z1

Claims (1)

[Claims] A source region and a drain region made of one conductivity type impurity layer formed on a semiconductor substrate, a gate oxide film formed between the source region and the drain region, and a gate electrode formed on the gate oxide film. 1. A semiconductor device having a MOS transistor comprising a MOS transistor, wherein the source region and the drain region are formed in separate islands of high concentration impurity layers of opposite conductivity types.