JPH0413861B2 - - Google Patents
Info
- Publication number
- JPH0413861B2 JPH0413861B2 JP62048807A JP4880787A JPH0413861B2 JP H0413861 B2 JPH0413861 B2 JP H0413861B2 JP 62048807 A JP62048807 A JP 62048807A JP 4880787 A JP4880787 A JP 4880787A JP H0413861 B2 JPH0413861 B2 JP H0413861B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor region
- semiconductor
- type
- region
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 102
- 238000009792 diffusion process Methods 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 16
- 230000005611 electricity Effects 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 239000000758 substrate Substances 0.000 description 9
- 238000000926 separation method Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は素子間分離を必要とする半導体装置
に係わり、例えば、高出力トランジスタを含むモ
ノリシツク集積回路に好適な半導体装置に関す
る。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device that requires isolation between elements, and for example, relates to a semiconductor device suitable for a monolithic integrated circuit including high-output transistors. .
（従来の技術）
大出力トランジスタを含むモノリシツク集積回
路においては、従来、一般に大出力トランジスタ
のコレクタ電極を半導体チツプの表面から取り出
すようになつている。(Prior Art) Conventionally, in a monolithic integrated circuit including a high-output transistor, the collector electrode of the high-output transistor is generally taken out from the surface of a semiconductor chip.
しかし、こにような構成では、半導体チツプの
面積が大きくなるという問題がある。 However, such a configuration has a problem in that the area of the semiconductor chip becomes large.
この問題を解決するために、第４図に示すよう
なモノリシツク集積回路が考えられている。図示
のモノリシツク集積回路は、N+型の半導体基板
１１の所定の位置に、Ｎ型の第１の埋込み層１２
を形成した後、Ｐ型のシリコン単結晶をエピタキ
シヤル成長させる。次に、このエピタキシヤル層
１３の表面から所定の位置にＮ型の第２の埋込み
層１４を形成後、Ｎ型のエピタキシヤル層１５を
成長させる。最後に、P+型の拡散層１６により、
PN分離を行なつている。 In order to solve this problem, a monolithic integrated circuit as shown in FIG. 4 has been considered. The illustrated monolithic integrated circuit includes an N type first buried layer 12 at a predetermined position of an N + type semiconductor substrate 11.
After forming, a P-type silicon single crystal is epitaxially grown. Next, after forming an N-type second buried layer 14 at a predetermined position from the surface of this epitaxial layer 13, an N-type epitaxial layer 15 is grown. Finally, due to the P + type diffusion layer 16,
Performing PN separation.
上記構成においては、Ｎ型のエピタキシヤル層
１５のうち、P+型の拡散層１６とＰ型のエピタ
キシヤル層１３によつて分離された島領域１７に
は、小信号トランジスタ等が形成され、N+型の
シリコン半導体基板１１に電気的につながるＮ型
のエピタキシヤル層１８には大出力トランジスタ
が形成される。したがつて、大出力トランジスタ
のコレクタ電極を半導体チツプの表面から取り出
さなくてもよいので、半導体チツプの面積を小さ
くすることができる。 In the above structure, a small signal transistor or the like is formed in the island region 17 of the N type epitaxial layer 15 separated by the P + type diffusion layer 16 and the P type epitaxial layer 13. A high output transistor is formed in the N type epitaxial layer 18 electrically connected to the N + type silicon semiconductor substrate 11. Therefore, since it is not necessary to take out the collector electrode of the high output transistor from the surface of the semiconductor chip, the area of the semiconductor chip can be reduced.
しかし、このような構成では、P+型の拡散層
１６が必要であり、このP+型の拡散層を形成す
るときに、縦方向とほぼ同じ横方向の拡散が不可
避的に発生し、チツプ面積の増大を招くという問
題が生じる。 However, in such a configuration, a P + type diffusion layer 16 is required, and when forming this P + type diffusion layer, diffusion in the lateral direction, which is almost the same as the vertical direction, inevitably occurs, and the chip A problem arises in that the area increases.
また、島領域１７とＮ型のエピタキシヤル層１
８とが同じエピタキシヤル成長によつて同時に形
成されるので、両者の不純物濃度が同じになり、
それぞれに作り込む半導体素子の特性に合つた不
純物濃度を設定できないという問題がある。 In addition, the island region 17 and the N-type epitaxial layer 1
8 are formed at the same time by the same epitaxial growth, so the impurity concentration of both is the same,
There is a problem in that it is not possible to set an impurity concentration that matches the characteristics of each semiconductor element to be manufactured.
（発明が解決しようとする問題点）
以上述べたように、大出力トランジスタのコレ
クタ電極を半導体チツプの裏面から取り出せるよ
うにした従来の半導体装置においては、PN分離
によつてチツプ面積の拡大を招くという問題や各
半導体領域において、それぞれに作り込まれる素
子に合つた不純物濃度を設定することができない
という問題があつた。(Problems to be Solved by the Invention) As described above, in conventional semiconductor devices in which the collector electrode of a high-output transistor can be taken out from the back side of a semiconductor chip, PN separation causes an increase in the chip area. There was a problem that it was not possible to set an impurity concentration suitable for each element to be manufactured in each semiconductor region.
この発明は上述したような問題を解決すること
ができる半導体装置を提供することを目的とす
る。 An object of the present invention is to provide a semiconductor device that can solve the above-mentioned problems.
［発明の構成］
（問題点を解決するための手段）
第１の導電型の第１の半導体領域の上に第２の
導電型の第２の半導体領域を形成し、この第２の
半導体領域に、その表面から上記第１の半導体領
域に至る第１の導電型の第３の半導体領域と、上
記第１の半導体領域に達する前の所定の位置まで
形成された第４の半導体領域とを形成している。
そして、上記第３の半導体領域に、この第３の半
導体領域と上記第１の半導体領域とを通電する第
１の半導体素子を形成し、上記第４の半導体領域
に、この第４の半導体領域のみを通電する第２の
半導体素子を形成するようにし、かつ上記第２の
半導体領域を、上記第１の半導体素子と第２の半
導体素子とを互いに分離する領域として構成して
いる。[Structure of the Invention] (Means for Solving the Problems) A second semiconductor region of a second conductivity type is formed on a first semiconductor region of a first conductivity type, and the second semiconductor region a third semiconductor region of the first conductivity type extending from the surface thereof to the first semiconductor region; and a fourth semiconductor region formed to a predetermined position before reaching the first semiconductor region. is forming.
A first semiconductor element that conducts current between the third semiconductor region and the first semiconductor region is formed in the third semiconductor region, and a first semiconductor element that conducts electricity between the third semiconductor region and the first semiconductor region is formed in the fourth semiconductor region. A second semiconductor element is formed that only conducts current, and the second semiconductor region is configured as a region that separates the first semiconductor element and the second semiconductor element from each other.
（作 用）
上記構成によれば、横方向のPN分離が第２の
導電型の拡散層によつてなされることがないの
で、PN分離に伴うチツプ面積の拡大を防止する
ことができる。(Function) According to the above configuration, since PN separation in the lateral direction is not performed by the second conductivity type diffusion layer, it is possible to prevent the chip area from increasing due to PN separation.
また、第３の半導体領域と第４の半導体領域と
は個別に形成されているので、作り込む半導体素
子の特性に合つた不純物濃度を設定することがで
きる。 Further, since the third semiconductor region and the fourth semiconductor region are formed separately, the impurity concentration can be set to match the characteristics of the semiconductor element to be manufactured.
（実施例）
以下、図面を参照してこの発明の一実施例を詳
細に説明する。(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
第１図ａ〜ｃはこの発明に係わる半導体装置の
一実施例の製造工程を示す断面図である。 FIGS. 1a to 1c are cross-sectional views showing the manufacturing process of an embodiment of a semiconductor device according to the present invention.
まず、第１図ａにおいては、N+型の半導体基
板（比抵抗０〜0.015Ωcm、厚さ300〜500μm）の
表面に、Ｐ型のシリコン（比抵抗５〜20Ωcm）を
約20〜30μmエピタキシヤル成長させ、エピタキ
シヤル層２２を形成する。 First, in Fig. 1a, P-type silicon (specific resistance 5-20 Ωcm) is epitaxially deposited to a thickness of about 20-30 μm on the surface of an N + type semiconductor substrate (specific resistance 0-0.015 Ωcm, thickness 300-500 μm). Then, the epitaxial layer 22 is formed.
次に、第１図ｂでは、Ｐ型のエピタキシヤル層
２２の表面からＮ型の不純物を選択拡散し、Ｎ型
の半導体領域２３を形成する。この時、Ｎ型の半
導体領域２３はN+型シリコン半導体基板２１と
つながるようにする。 Next, in FIG. 1B, N-type impurities are selectively diffused from the surface of the P-type epitaxial layer 22 to form an N-type semiconductor region 23. At this time, the N type semiconductor region 23 is connected to the N + type silicon semiconductor substrate 21.
最後に、第１図ｃにおいては、Ｐ型のエピタキ
シヤル層２２の表面からＮ型の不純物を選択拡散
し、Ｎ型の半導体領域２４を形成する。但し、こ
の場合は、上記Ｎ型の半導体領域２３とは異な
り、ｐ型のシリコン半導体基板２１につながらな
いようにする。これにより、Ｎ型の半導体領域２
４は、Ｐ型のエピタキシヤル層２２に囲まれた島
領域となる。 Finally, in FIG. 1c, N-type impurities are selectively diffused from the surface of the P-type epitaxial layer 22 to form an N-type semiconductor region 24. However, in this case, unlike the N-type semiconductor region 23 described above, it should not be connected to the P-type silicon semiconductor substrate 21. As a result, the N-type semiconductor region 2
4 is an island region surrounded by a P-type epitaxial layer 22.
第２図は上記構成をもつ半導体装置に素子を作
り込んだ場合の断面構造を示す。 FIG. 2 shows a cross-sectional structure when an element is built into a semiconductor device having the above structure.
なお、第２図では、島領域となるＮ型エピタキ
シヤル層２４として２４ａ，２４ｂの２つを示
す。 In FIG. 2, two N-type epitaxial layers 24a and 24b are shown as the island regions.
Ｐ型のエピタキシヤル層２２からN+型のシリ
コン半導体基板２１につながるＮ型の半導体領域
２３に形成される素子は、例えばパワー素子とし
て良く知られるＤ−MOS型の電界効果トランジ
スタ（以下、FETと記す）である。ここで、２
５１はベースであり、２５２はソースであり、２
５３はゲートである。 The elements formed in the N-type semiconductor region 23 that connects the P-type epitaxial layer 22 to the N + type silicon semiconductor substrate 21 are, for example, D-MOS field effect transistors (hereinafter referred to as FETs), which are well known as power elements. ). Here, 2
51 is the base, 252 is the source, 2
53 is a gate.
また、一方のＮ型の半導体領域２４ａには、例
えば、耐圧をさほど必要としないNPN型のバイ
ポーラトランジスタ２６が形成されている。ここ
で、２６１はこのトランジスタ２６のベースであ
り、２６２はエミツタであり、２６３はコレクタ
である。他方のＮ型の半導体領域２４ｂには、Ｐ
チヤンネルMOSFET２７とＮチヤンネル
MOSFET２８が形成されている。ここで、２７
１，２８１は各FET２７，２８のソースであり、
２７２，２８２は同じくドレインであり、２７
３，２８３は同じくゲートである。 Further, in one of the N-type semiconductor regions 24a, for example, an NPN-type bipolar transistor 26 that does not require much breakdown voltage is formed. Here, 261 is the base of this transistor 26, 262 is the emitter, and 263 is the collector. In the other N type semiconductor region 24b, P
Channel MOSFET27 and N channel
A MOSFET 28 is formed. Here, 27
1,281 is the source of each FET27, 28,
272 and 282 are also drains, and 27
3,283 is also a gate.
なお、上記FET２５，２７，２８やバイポー
ラトランジスタ２９は詳細は省略するが、周知の
方法で作られるものである。 Although details of the FETs 25, 27, and 28 and the bipolar transistor 29 are omitted, they are manufactured by a well-known method.
２９は半導体チツプの表面に形成された絶縁膜
であり、３０は半導体チツプの裏面に形成された
上記Ｄ−MOS型FETのドレイン電極として使わ
れる導電体層である。 29 is an insulating film formed on the front surface of the semiconductor chip, and 30 is a conductive layer formed on the back surface of the semiconductor chip used as the drain electrode of the D-MOS type FET.
以上述べたようにこの実施例は、Ｐ型のエピタ
キシヤル層２２にＮ型の不純物を選択拡散するこ
とにより、Ｎ型の半導体領域２３，２４を形成す
るようにしたものである。したがつて、この実施
例によれば、横方向PN分離をP+型の拡散層１６
を使つて行なう従来の半導体装置と違つて、例え
ば、第２図に示すｘの距離を小さくすることがで
き、横方向のPN分離に伴うチツプ面積の拡大を
防ぐことができる。 As described above, in this embodiment, N-type semiconductor regions 23 and 24 are formed by selectively diffusing N-type impurities into the P-type epitaxial layer 22. Therefore, according to this embodiment, the lateral PN separation is performed using the P + type diffusion layer 16.
Unlike a conventional semiconductor device using a semiconductor device, for example, the distance x shown in FIG. 2 can be made small, and the chip area can be prevented from increasing due to lateral PN separation.
また、各Ｎ型の半導体領域２３，２４を拡散に
より個別に形成することにより、各半導体領域２
３，２４の不純物濃度を別々に設定することがで
き、作り込む素子の特性に合つた不純物濃度を設
定することができる。 In addition, by forming each N-type semiconductor region 23 and 24 individually by diffusion, each semiconductor region 2
The impurity concentrations of 3 and 24 can be set separately, and the impurity concentrations can be set to match the characteristics of the device to be manufactured.
さらに、Ｎ型の半導体領域２３，２４を、Ｐ型
のエピタキシヤル層２２の表面からの不純物の拡
散によつて形成しているので、半導体領域２３，
２４の表面積が広くなり、表面を使用する半導体
素子に好都合な半導体領域を設定することができ
る。 Furthermore, since the N-type semiconductor regions 23 and 24 are formed by diffusion of impurities from the surface of the P-type epitaxial layer 22, the semiconductor regions 23 and
The surface area of 24 is increased, and a convenient semiconductor region can be set for a semiconductor device using the surface.
第３図はこの発明の他の実施例の構成を示す断
面図である。先の実施例では、Ｐ型のエピタキシ
ヤル層２２の表面からＮ型のシリコン半導体基板
２１まで形成される半導体領域２３を不純物の拡
散だけで形成する場合を説明したが、この実施例
では、N+型埋め込み層３１１と不純物の拡散層
３１２を使つて形成するにしたものである。すな
わち、まず、Ｐ型のエピタキシヤル層２２を形成
する前に、N+型のシリコン半導体基板２１の上
にN+型の埋め込み層３１１を形成する。次に、
Ｐ型のエピタキシヤル層２２を形成した後、その
表面からN+の埋込み層３１１につなげるように、
不純物を拡散し、拡散層３１２に形成する。 FIG. 3 is a sectional view showing the structure of another embodiment of the present invention. In the previous embodiment, a case was explained in which the semiconductor region 23 from the surface of the P-type epitaxial layer 22 to the N-type silicon semiconductor substrate 21 was formed only by diffusion of impurities. It is formed using a + type buried layer 311 and an impurity diffusion layer 312. That is, first, before forming the P-type epitaxial layer 22, an N + -type buried layer 311 is formed on the N + -type silicon semiconductor substrate 21. next,
After forming the P-type epitaxial layer 22, connect it to the N + buried layer 311 from its surface.
An impurity is diffused to form a diffusion layer 312.
このような構成によれば、先の実施例と同様の
効果を得ることができることは勿論、さらに、半
導体領域３１を形成するための不純物の拡散時間
を短縮することができる。また、半導体領域３１
の厚みを厚くすることができるので、高耐圧半導
体素子の搭載が可能となる。 According to such a configuration, it is possible to obtain the same effects as in the previous embodiment, and furthermore, it is possible to shorten the diffusion time of impurities for forming the semiconductor region 31. In addition, the semiconductor region 31
Since the thickness can be increased, it is possible to mount a high voltage semiconductor element.
以上この発明の実施例をいくつか説明したが、
この発明はこのような実施例に限定されるもので
はなく、他にも、発明の要旨を逸脱しない範囲で
種々様々変形実施可能なことは勿論である。 Several embodiments of this invention have been described above, but
It goes without saying that the present invention is not limited to these embodiments, and that various other modifications can be made without departing from the gist of the invention.
［発明の効果］
以上述べたようにこの発明によれば、横方向の
PN分離に伴うチツプ面積の拡大を防止すること
ができるとともに、それぞれの半導体領域におい
て、作り込む半導体素子の特性に合つた不純物濃
度を設定することができる半導体装置を提供する
ことができる。[Effect of the invention] As described above, according to this invention, horizontal
It is possible to provide a semiconductor device in which it is possible to prevent the chip area from increasing due to PN separation, and in which impurity concentrations can be set in each semiconductor region to match the characteristics of the semiconductor element to be fabricated.
第１図はこの発明に係わる半導体装置の一実施
例の製造工程を示す断面図、第２図は第１図で説
明した半導体装置に半導体素子を作り込んだ状態
を示す断面図、第３図はこの発明に係わる半導体
装置の他の実施例の構成を示す断面図、第４図は
従来の半導体装置の構成を示す断面図である。
２１…Ｎ型のシリコン半導体基板、２２…Ｐ型
のエピタキシヤル層、２３，２４，２４ａ，２４
ｂ，３１…Ｎ型の半導体領域、２５…Ｄ−
MOSFET、２６…NPN型のバイポーラトランジ
スタ、２７，２８…MOSFET、２９…絶縁層、
３０…導電体層、３１１…N+型の埋込み層、３
１２…Ｎ型の拡散層。
FIG. 1 is a cross-sectional view showing the manufacturing process of an embodiment of a semiconductor device according to the present invention, FIG. 2 is a cross-sectional view showing a state in which a semiconductor element is built into the semiconductor device explained in FIG. 1, and FIG. 4 is a cross-sectional view showing the structure of another embodiment of the semiconductor device according to the present invention, and FIG. 4 is a cross-sectional view showing the structure of a conventional semiconductor device. 21... N-type silicon semiconductor substrate, 22... P-type epitaxial layer, 23, 24, 24a, 24
b, 31...N-type semiconductor region, 25...D-
MOSFET, 26... NPN type bipolar transistor, 27, 28... MOSFET, 29... Insulating layer,
30...Conductor layer, 311...N + type buried layer, 3
12...N type diffusion layer.
Claims (1)
導電型の第２の半導体領域と、 この第２の半導体領域に、その表面から上記第
１の半導体領域に至るように形成された第１の導
電型の第３の半導体領域と、 上記第２の半導体領域に、その表面から上記第
１の半導体領域に達する前の所定の位置まで形成
された第４の半導体領域と、 を具備し、上記第３の半導体領域に、この第３の
半導体領域と上記第１の半導体領域とを通電する
第１の半導体素子を形成し、 上記第４の半導体領域に、この第４の半導体領
域のみを通電する第２の半導体素子を形成し、 上記第２の半導体領域を、上記第１の半導体素
子と第２の半導体素子とを互いに分離する領域と
して構成したことを特徴とする半導体装置。 ２ 上記第３の半導体領域は、不純物の拡散によ
り形成されていることを特徴とする特許請求の範
囲第１項記載の半導体装置。 ３ 上記第３の半導体領域は、 上記第１の半導体領域の表面に形成された第１
の導電型の埋め込み層と、 上記第２の半導体領域に、その表面から上記第
１の導電型の埋め込み層に至るように形成された
拡散層と、 を具備したことを特徴とする特許請求の範囲第１
項記載の半導体装置。[Claims] 1: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type formed on the first semiconductor region; and a second semiconductor region of the second conductivity type. a third semiconductor region of the first conductivity type formed in the region from the surface thereof to the first semiconductor region; and a third semiconductor region of the first conductivity type formed in the second semiconductor region from the surface to the first semiconductor region. a fourth semiconductor region formed to a predetermined position before reaching the third semiconductor region; and a first semiconductor that conducts current between the third semiconductor region and the first semiconductor region. forming a second semiconductor element in the fourth semiconductor region that conducts electricity only in the fourth semiconductor region; A semiconductor device characterized in that it is configured as a region that separates a semiconductor element from each other. 2. The semiconductor device according to claim 1, wherein the third semiconductor region is formed by diffusion of impurities. 3 The third semiconductor region includes a first semiconductor region formed on the surface of the first semiconductor region.
and a diffusion layer formed in the second semiconductor region from the surface thereof to the buried layer of the first conductivity type. Range 1
1. Semiconductor device described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62048807A JPS63216370A (en) | 1987-03-05 | 1987-03-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62048807A JPS63216370A (en) | 1987-03-05 | 1987-03-05 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63216370A JPS63216370A (en) | 1988-09-08 |
| JPH0413861B2 true JPH0413861B2 (en) | 1992-03-11 |
Family
ID=12813479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62048807A Granted JPS63216370A (en) | 1987-03-05 | 1987-03-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63216370A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02143454A (en) * | 1988-11-25 | 1990-06-01 | Hitachi Ltd | Semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57155768A (en) * | 1981-03-23 | 1982-09-25 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS5835978A (en) * | 1981-08-28 | 1983-03-02 | Fujitsu Ltd | Semiconductor device |
| JPS6017943A (en) * | 1983-07-08 | 1985-01-29 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS60258949A (en) * | 1985-01-04 | 1985-12-20 | Nec Corp | Complementary field effect semiconductor device |
-
1987
- 1987-03-05 JP JP62048807A patent/JPS63216370A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57155768A (en) * | 1981-03-23 | 1982-09-25 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS5835978A (en) * | 1981-08-28 | 1983-03-02 | Fujitsu Ltd | Semiconductor device |
| JPS6017943A (en) * | 1983-07-08 | 1985-01-29 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS60258949A (en) * | 1985-01-04 | 1985-12-20 | Nec Corp | Complementary field effect semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63216370A (en) | 1988-09-08 |
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |