JPS5835978A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make a high dielectric resistance element and a low threshold-low dielectric resistance element coexist in a same substrate by forming two kinds or more of N layers, depth thereof differs, to a P type Si substrate and shaping FETs to the N layers. CONSTITUTION:An Si3N4 mask 25 is formed onto the SiO2 thin-film 22 of a P type Si substrate 21 and a photo-resist mask is jointly used, P and As ions are implanted successively to regions 26, 27 and annealed and a deep N layer 31, shallow N layer 29, deep N<++> layer 34' and a shallow N<+> layer 36' in each N layer are shaped selectively, and a resist mask 37 is molded, B ions are implanted and an N<+> layer 38' is formed. The mask 37 is removed and the whole is annealed, and the channel cuts of the N<++> type 34 and the N<+> types 36, 38 and two shallow and deep kinds of the N wells 29, 31 are completed. High drain dielectric resistance is obtained when the PMOS element T1 is shaped to the N layer 31, depth thereof is approximately twice as long as normal devices, and the RMOS element T2 of normal dielectric resistance-low threshold voltage in the shallow N layer 29 and the NMOS element T3 of normal dielectric resistance in the surface of the substrate 1 can be made coexist.

Description

[Detailed description of the invention] The present invention relates to MI8fi semiconductor devices, particularly to voltage resistance.

This invention relates to a semiconductor device 06 with a total weight of 1 g, including two or more types of in-fer transistors having electrical characteristics such as threshold voltage O^.

In a semiconductor integrated circuit (IC) K equipped with a circuit for controlling a device operating at high voltage such as a fluorescent display tube, when forming a high voltage resistor (0Ml8) transistor in the shell region to control the armpit high voltage, conventional Wrinkle high voltage withstand MI8) Twister and low threshold value-
Normal transistors having a low breakdown voltage are arranged in parallel in the same Nil region, and the impurity concentration of the shell is low in order to give a low threshold voltage to a large number of normal transistors formed in the well. Conventionally, when forming a high voltage MIS transistor in an area where the concentration is limited, a high voltage MIS transistor is formed around the diffusion region to which the high voltage of the transistor is applied. However, in the conventional structure, the depth of the shell region is limited due to the low impurity concentration as described above. Therefore, when a high voltage is applied to the diffusion region, the vertical direction O formed between the diffusion region and the shell becomes shallower.
The expansion of the depletion layer in the PN junction reaches the bottom of the well region and punch-through occurs between the diffusion region and the substrate, so the load voltage that can be controlled by a high voltage transistor is about 20 (V). In view of the above-mentioned problems, the present invention has been proposed to provide an easy-to-use semiconductor device in which an in-well transistor with a high breakdown voltage and an in-well transistor with a low threshold and low breakdown voltage are arranged side by side on the same semiconductor substrate. The structure of the device provides tubes.

That is, the present invention provides a semiconductor device in which two or more types of impurity fell regions having conductivity types opposite to that of the substrate and having different thicknesses are provided in a semiconductor substrate having -conductivity fJit-, and a field effect transistor is formed in the mosquito well region. It is characterized by:

Hereinafter, one embodiment of the present invention will be described in detail with reference to a sectional view of a main part shown in FIG. 1 and a process sectional view shown in FIGS. 2(a) to 2(b)K.

A semiconductor IC to which the present invention is applied has, for example, a structure as shown in FIG.
A P-type semiconductor (silicon) substrate having a specific resistance of about (Ω-1), 2 is a deep layer formed by implanting phosphorus ions (P) at a high dose of 4 × 10'” (atm/j) 1 degree. The first N-well region is as deep as 5 μm, and 3 is <z
xtocatm/d) Formed by implanting P+ at a low dose of 11 degrees, the shallow second ON well region has a depth of about 2 to 3 μm, 4 m, 4 b, 4 a, and 4 are field oxide films, 5 is an N-channel channel with a relatively low degree of impurity (1fl).
The cut region 6 is a relatively low-Pm channel Φ cut region with a relatively low impurity concentration.

Then, on the surface of the deep jllON quell region 2, there is an I
X 10” (atm/j) sjl!O boron (B) ka)-slL95eoo ~60G0(X)sritom
A Pal drain region 8 to which a high voltage is applied, a P source region 9 to which a normal voltage is applied, and the PM drain region StS of about 10" (atm/cd) -
A high-voltage PMOS transistor T! consists of a P-chicken offset region 10 doped with 1 * 5 IIaoooc is formed.

Also, the surface of the shallow second ON well region 3 has an OB similar to the above.
P-drain region 13 with nobility and depth. PW source region 9 and gate oxide film 11. A normal voltage PMO transistor 8) consisting of a multi-crystalline gate electrode 12 is formed. Also, on the surface of the PW8i board 1,
Arsenic (As) 4 x 10” (atm/cj)
An NMOS transistor T with a normal breakdown voltage is formed, consisting of an N1 type drain region 14 and an N+ type source region 15 with a doped depth of approximately 4000 [J], a gate oxide Jll [11] and a polycrystalline S1 gate electrode 12. An insulating film 16 made of phosphosilicate glass (PSG) or the like formed on these transistors is covered with aluminum (AL) or the like led out from each drain region and source region through an electrode window. Electrode wiring 17m, 1
7b, 17c, 17d, 17e, and 17f are provided. Note that the gate wiring is not shown in this figure because it is formed in a region other than the constraint.

As shown in the above embodiment, in the present invention, high voltage PMO
8) The transistor T1 is formed within 2° of the ninth N-well region with a depth approximately twice the normal depth. Therefore, the width of the depletion layer region in the vertical direction between the P-type drain/region 8 and the N-well region to which a high voltage is applied is reduced to 2 compared to the conventional width.
Since it is possible to secure nearly [times] more, in this embodiment, a drain breakdown voltage of about 40[:V] can be obtained.

Further, since the normal breakdown voltage PMO8) transistor T is formed in the shallow 20th quell region 3 with a low density [F] vortex formed at a low dose since the expansion of the depletion layer is small.

gIL-2 PMO8) Transistor T, 0 low threshold voltage is ensured.

Next, manufacture the nine conductor device shown in the above example.
The order of 011P is determined using the process cross-sectional diagrams shown in FIGS.
1, a thin silicon dioxide (810 m) film 22 of 5oo (X) lim is formed by thermal oxidation, and then the 81
Activated regions 23m and 23b are formed on the film 22 by ordinary chemical vapor deposition and turning means.

Silicon nitride (SisNJ film 25@l) covering 234I, O to form 25a on 26, and a first film having a window exposing the first well formation region 26 and @2 well formation region 27 on the substrate. 1 photoresist film 28 is formed by a normal photo process, and then using the photoresist film 28 as a mask, ions ( ) and (
P) is selectively implanted at a dose of, for example, 2×10" (atm/j) lim, and is implanted into the tenth well formation region 26 and the second well formation region 27. ◎ Next, as shown in FIG. 2, a 207th automatic resist a30 extending over the eighth felt forming region 27 is formed on the iron substrate. The photoresist of No. 2 is made into a 1# mask at $28.30, and then ions (P) are selectively applied to the 26th surface of the felt formation region of No. 1 at a dose of, for example, 2 x 10" (atm/d). to form the first well forming region 26Kil9(g) implanted region 31'@Then, the first and second 7-hole resist films 28.3
After removing the 0, a desired O14 temperature annealing treatment is performed in the usual manner.The high-concentration phosphorus implanted region 31' is deeply diffused by the low-temperature annealing, and the low-nobility phosphorus [F] is deeply diffused.
The implantation region 29' is shallowly diffused to form a first ONWi well region 31 with a depth of about 5 [μtin] in the first fer formation region 26 and a 20th well formation region 27, as shown in FIG. 2(c)K. According to the normal O channel cut region formation method in the 0th order to form the second ON deep well region 29 at a depth of 2 to 3 [mu], first, a window is formed on the substrate surface to expose a high ampere. A photoresist film 33 of I3 is formed, and a first
ONl [10” (atm/j) I on the 31st side of the Fell region
Arsenic ions (A-) are selectively implanted at a high dose of IIEO, and a high-intensity implantation region 34' is selectively implanted at a distance of nine from the front ffi activation region 13a on the upper part of the Nllll Fell 31 of the irises 1. , and then a second It (as shown in 4), a first N well region 31 and a 24th D
A photoresist film 35 of A4 with AT exposing the upper part of the NIL quell region 29 is formed, and a photoresist film 35 of 1G" (atm/j) is applied to the photoresist J[35 and StS as a film zs island and 28b tv mask. IIC) Shallow selective implantation of arsenic ions (MuS) at a low dose into the gold body in regions other than the activation regions 23m and jlab in the jll and second Nll1 well regions 31 and 8 and the upward s. 1Il
Forming the IWLAI implant region 36' is shown in FIG.
・)K As shown, the first . flat) NW!
A rattan s07 photoresist film 37 is formed covering the well region 31.29, and the photoresist film 37 and 5is
Past board 21i1K using N4j[25a as a mask
Boron ions (B+) are shallowly implanted at a dose of 1 G'' (atm/j, 111 degrees) to selectively form a shallow B implanted region 88' on the 8g! surface of the IJllSi substrate 21. Oto resist 311 [3
After removing 5 and tomo, 81sN+J[2! ilL, 25b2
5e as an oxidation-resistant mask, selective thermal oxidation is performed to form an activated region 23a on the substrate surface as shown in FIG. 2(f)K.

23b, 23atwid determine 7 4-k)” oxidation 1
[39m.

39b, 39@, and 39d are formed. At this time, as described above, the field oxide films 39m and 3 into which impurities are implanted are
On the upper surface of the first ONffi query region 31 at the bottom of 9b, there is a
The channel cut area 34 and the active area 23 are connected to the channel cut area 34 and the activation area 23&.
N+m channel cut area 36 or 74/'
)" oxidation jlHI9b, 39e The upper surface sK of the lower 110 rattan 2ON well region 29 is the active region + 23bK contacting hNm channel-cut region 36 is further each 74-# oxidation Jlk:la, $11.39c.

3194 lower *0Ps181 groups I [21P on the top part! j
81sN on the activation regions 23m, 28b, and H1s at the 0th order in which the lf Yarnel cut region 88 is formed.
S 10s at the bottom of the control membrane 21a, isb, 28* and 7O
After removing the film 22 by the O method, the activated regions 23+a, 2 are removed by oxidation as shown in FIG.
Gate oxide 1g40 is formed on the irises 3b and 23c, and a polycrystalline Iil gate electrode 41 is formed on the gate oxide film 40 through ordinary chemical vapor deposition and patterning means.
Activated region 23a is formed according to the normal OCMOIi manufacturing method.
That is, the circumference 1! ! IC
? A pm drain region 43 and a pm source region 44 having an offset region 42 are formed to form a high breakdown voltage PMO 8).
The tuning transistor T1 and the activation region 23b11J'bll
A P drain region 41 is provided on the upper surface of the ZON*quel region 29.
1. By forming the P- source region 44, the normal breakdown voltage PMOai
) Transistor Tt as a trap and active region 88 @ ie pH 8
1 N-drain region 4s and N+1m source region 46 are formed on the upper surface of the substrate 21 to form the normal breakdown voltage) 1MO8) transistor Ta respectively. As shown in II(b)K, an insulating film 47 such as KP8G is formed on the axillary substrate by the usual method, an electric wire is formed on the wrinkle insulating metal 47, and an electrode wiring 411a*isb is formed on the axillary conjunctive film 47. , 41Je,
484411e and 411f are formed. At this time, wiring connecting to the polycrystalline 81 gate electrode 41 is also formed, but this wiring is not shown because it is outside the cut box area.

In addition, in the above method, if the threshold voltage of the high-voltage PMO resistor is formed low, the injection temperature to 111 degrees in the N fer formation region of jll is lowered, and high-temperature annealing is performed intensely. Particularly) the 10th NII well region is formed deeply and at the same time its #! The surface straightness may be reduced to a desired value. Alternatively, the threshold voltage may be controlled by implanting a low dose of boron (6), etc., which has a conductivity opposite to that of Fer.
Although the structure in which regions are provided in the semiconductor substrate KNQ has been described, the present invention can also be applied to a reverse conductor.
According to the above theory, according to the present invention, two in-well transistors with high withstand voltage and low threshold Since a low-voltage in-fer transistor can be installed in parallel with a harmful bird, the semiconductor ICO4 is equipped with a high-voltage device drive circuit! ! A book that can improve your abilities. This is a fragmentary diagram of the main parts in one embodiment of the present invention.
m) to QlO - Manufacturing process interruption iui in the example
◎ In IIK, 1 is the semiconductor (silicon) substrate, 2 is the first O
N query area, 3 is the second ON query area, 4a14b6
4c, 4dd field oxidation group, 5 is r 臘 channel ambiguous cut region, 6 is N++-channel cut region, 7 is P
#i channel cut region, 8.13+ is PJI drain region, 9 is P type source region, 10 is P
``ATAT offset region is gate oxide film, 12 is polycrystalline silicon/gate electrode, 14 is 8-layer drain region, 1
5 is an N''-source region, 16 is an insulating film, 17m, 17b
@17e, 17@, 17f are electrode wiring, TI is high voltage PMO8) tsy transistor, T■ is normal voltage PMO8)
0 indicates the normal voltage resistance NMO 8) Tungister.

Claims (1)

[Claims] It is characterized by providing two or more types of impurity shell regions having different m-s in a semiconductor substrate having one conductive layer and an opposite conductive layer, and forming a field effect transistor in the shell region. A semiconductor device t.