JPH10172981A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set withstand voltage to be high and to improve the operating speed. SOLUTION: The method is to manufacture a semiconductor device where a bipolar transistor is formed on a P-type silicon substrate 1. A heat treatment process for ion-implanting As to a first collector burying area in the P-type silicon substrate 1, ion-implanting Phos whose diffusion coefficient is larger than that of As to second collector burying areas 11 in the P-type silicon substrate 1 positioned below emitter regions 27, and activating As implanted in the first collector burying region 7 and Phos implanted to the second collector burying areas, is executed. An N-type epitaxial layer 15 is deposited on the P-type silicon substrate 1 and graft base region 23, base regions 25, and the emitter regions 27 are formed on the N-type epitaxial layer 15. Thus, withstand voltage is made high and speed is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of achieving high withstand voltage and operating at a high speed, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Monolithic semiconductor devices (integrated circuits)
While low-voltage, miniaturization, and high-speed operations are advancing, those that handle high-voltage, high-current, and high-speed operations are often formed by combining discrete components. Tends to form. this is,
Although the fields that require high withstand voltage may be limited,
This also has an effect on the difficulty in a manufacturing method having both high breakdown voltage and high speed.

FIG. 9 is a sectional view showing a conventional semiconductor device (bipolar transistor). An epitaxial layer 115 is deposited on the surface of the semiconductor substrate 101.
A diffusion layer 113 of an isolation region for element isolation is formed on the epitaxial layer 115 and the semiconductor substrate 101, and a diffusion layer 107 of a collector buried region is provided between the diffusion layers 113 of the isolation region on the surface of the semiconductor substrate 101. Are formed.

[0004] In the epitaxial layer 115, a diffusion layer 121 of a collector take-out region located between the diffusion layers 113 of the isolation region and above the diffusion layer 107 of the collector buried region is formed. The diffusion layer 121 in the collector extraction region is connected to the diffusion layer 107 in the collector buried region.

[0005] On the surface of the epitaxial layer 115, a diffusion layer 123 of a graft base region located between the diffusion layers 113 of the isolation region and above the diffusion layer 107 of the collector buried region is formed.
A diffusion layer 125 in the base region is formed on the surface of the epitaxial layer 115 so as to connect the diffusion layers 123 in the graft base region to each other. Inside the diffusion layer 125 in the base region, a diffusion layer 127 in the emitter region is formed.

[0006]

Incidentally, in order to obtain a high breakdown voltage in the above-mentioned conventional bipolar transistor, it is necessary to lower the impurity concentration of the epitaxial layer 115, to increase the thickness of the epitaxial layer 115, or to use a graft base. A method of giving a large curvature to the shape of the diffusion layer 123 in the region or increasing the width of the base region 125 can be considered. On the contrary,
In order to increase the speed in the above-described conventional bipolar transistor, it is necessary to increase the impurity concentration of the epitaxial layer 115, to reduce the thickness of the epitaxial layer 115, and to reduce the impurity concentration of the diffusion layer 125 in the base region. For example, the width of the base region 125 may be reduced. As described above, there is a demand for a method that is incompatible with achieving high speed and achieving high withstand voltage. Therefore, there is a problem that increasing the breakdown voltage sacrifices the speed, and increasing the speed sacrifices the breakdown voltage.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of achieving a high withstand voltage and a high speed at the same time, and a method of manufacturing the same. It is in.

[0008]

In order to solve the above-mentioned problems, a semiconductor device according to the present invention is a bipolar transistor formed on a semiconductor substrate, the device being provided below a graft base region formed on the semiconductor substrate. Located first
And a second collector buried region located below the emitter region and formed thicker than the first collector buried region.

Further, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which a bipolar transistor is formed on a semiconductor substrate, wherein a first impurity is implanted in a first collector buried region of the semiconductor substrate. Ion-implanting; ion-implanting a second impurity having a larger diffusion coefficient than the first impurity into a second collector buried region of the semiconductor substrate located below the emitter region; A heat treatment step of activating the first impurity implanted into the collector buried region and the second impurity implanted into the second collector buried region.

According to the present invention, a first impurity is ion-implanted into the first collector buried region, and a second collector buried region located below the emitter region has a diffusion coefficient larger than that of the first impurity. The second impurity is ion-implanted. Thereby, the second collector buried region can be formed thicker than the first collector buried region. As a result, the speed at which electrons injected from the emitter are extracted to the collector can be increased, and the speed can be increased. Further, a first collector buried region having a thickness smaller than that of the second collector buried region is formed below the graft base region. For this reason, it is possible to sufficiently increase the thickness of the portion having a low impurity concentration of the N-type epitaxial layer located on the first collector buried region,
High breakdown voltage can be achieved. Therefore, it is possible to increase the withstand voltage and at the same time to increase the speed.

Preferably, the first impurity is As, and the second impurity is Phos. Ph
Since the diffusion coefficient of os is about twice as large as that of As,
The second collector buried region can be formed thicker than the first collector buried region. Further, it is preferable that the mask used for the step of ion-implanting the second impurity has the same pattern shape as the mask used for the ion implantation step for forming the emitter region. Second
Is formed below the emitter region.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device (NPN bipolar transistor) according to an embodiment of the present invention. An N-type epitaxial layer 15 is deposited on the surface of the P-type silicon substrate 1. On the surface of the P-type silicon substrate 1, a P-type diffusion layer 13 of an isolation region for element isolation is formed.
A diffusion layer 7 of a first buried collector region is formed between the diffusion layers 13 of the isolation region on the surface of the P-type silicon substrate 1. On the surface of the P-type silicon substrate 1 and the N-type epitaxial layer 15, the second
The N type diffusion layer 11 of the collector buried region is formed. The thickness of the diffusion layer 11 in the second buried collector region is larger than the thickness of the diffusion layer 7 in the first buried collector region.

The N-type epitaxial layer 15 has a P-type diffusion layer 22 in an isolation extraction region, and the diffusion layer 22 in the isolation extraction region is connected to the diffusion layer 13 in the isolation region.
In the N-type epitaxial layer 15, an N-type diffusion layer 21 of a collector extraction region located between the diffusion layers 22 of the isolation extraction region and located on the diffusion layer 11 of the second collector buried region is formed. ing. The diffusion layer 21 in the collector take-out region is connected to the diffusion layer 11 in the second collector buried region.

On the surface of the N-type epitaxial layer 15, the P-type diffusion of the graft base region located between the diffusion layers 22 in the isolation extraction region and above the diffusion layer 7 in the first collector buried region. A layer 23 is formed. On the surface of the N-type epitaxial layer 15, a diffusion layer 25 in the base region is formed so as to connect the diffusion layers 23 in the graft base region to each other. An N-type diffusion layer 27 of an emitter region is formed inside the diffusion layer 25 of the base region.

Next, a method of manufacturing the above-described NPN bipolar transistor will be described with reference to the drawings. 2 to 7 show an NP according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a method for manufacturing an N-type bipolar transistor.

First, as shown in FIG. 2, a thermal oxide film 3 having a thickness of about 10 to 100 nm is formed on the surface of a P-type silicon substrate 1 by a thermal oxidation method. This thermal oxide film 3 is for suppressing generation of channeling, defects, and the like due to ion implantation in a later step. After that, a first resist film 5 is provided on the thermal oxide film 3 by performing patterning by a photo lithography technique.

Next, using the first resist film 5 as a mask, the first collector buried region 7a of the bipolar transistor in the P-type silicon substrate 1 contains, for example, As as an impurity at an accelerating voltage of 30 to 70 keV, 1 × 10
^The ions are implanted at a dose of ¹⁵ / cm ^{2 to} 5 × 10 ¹⁵ / cm ² .

Thereafter, as shown in FIG. 3, the first resist film 5 is removed, and the thermal oxide film 3 is patterned by photolithography to form a second resist film.
Is provided. The pattern shape of the resist film 9 is the same as that of the mask used in the ion implantation step for forming the diffusion layer 27 in the later-described emitter region of the bipolar transistor.

Next, using the second resist film 9 as a mask, the second collector buried region 11a of the bipolar transistor in the P-type silicon substrate 1 has an accelerating voltage of, for example, Phos of 30 to 70 keV as an impurity.
Ions are implanted at a dose of ^{× 10 13 / cm 2 ~5 ×} 10 14 / cm 2. In this case, an impurity having a larger diffusion coefficient than the impurity implanted into the first collector buried region 7a is used. Incidentally, the diffusion coefficient of Phos is about twice as large as that of As. The second collector buried region 11a is located immediately below the later-described emitter region of the bipolar transistor and immediately below the later-described collector extraction region. Next, after the second resist film 9 is removed, for example, Boron is ion-implanted as an impurity into the isolation region for element isolation (not shown).

Thereafter, as shown in FIG. 4, a heat treatment for activating the impurities implanted in the first and second collector buried regions 7a and 11a and the isolation region is performed, for example, in a nitrogen atmosphere at 1100 to 1200. The reaction is performed at a temperature of 100C for 100 to 300 minutes. As a result, the N-type diffusion layers 7 and 11 in the first and second collector buried regions and the P-type diffusion layer 13 in the isolation region are formed on the P-type silicon substrate 1.

Next, as shown in FIG.
Is removed, an N-type epitaxial layer 15 having a thickness of about 10 to 15 μm is deposited on the surface of the P-type silicon substrate 1. Next, a thermal oxide film 17 having a thickness of about 10 to 50 nm is formed on the surface of the N-type epitaxial layer 15 by a thermal oxidation method.

Thereafter, a third resist film 19 is provided on the thermal oxide film 17 by performing patterning by photolithography. Using the third resist film 19 as a mask, for example, Phos as an impurity is contained in the collector extraction region 21a of the bipolar transistor in the N-type epitaxial layer 15 by 30 to 100.
Accelerating voltage of keV, 1 × 10 ¹⁵ / cm ^{2 to} 5 × 10 ¹⁵ / cm
Ions are implanted at a dose of ² . The collector extraction region 21a is a diffusion layer 1 of a second collector buried region.
1 above. Next, after the third resist film 19 is removed, for example, Boron is ion-implanted as an impurity into an isolation extraction region of the N-type epitaxial layer 15 located above the diffusion layer 13 in the isolation region. (Not shown).

Next, as shown in FIG. 6, a thermal diffusion process of the collector extraction region 21a and the isolation extraction region is performed, for example, in a nitrogen atmosphere at 1100 to 1200.
It is performed at a temperature of 300C for 300 to 600 minutes. As a result, an N-type diffusion layer 21 in the collector extraction region and a P-type diffusion layer 22 in the isolation extraction region are formed in the N-type epitaxial layer 15. As a result, the diffusion layer 21 in the collector extraction region is connected to the diffusion layer 11 in the second collector buried region, and the diffusion layer 22 in the isolation extraction region is connected to the diffusion layer 13 in the isolation region.

Thereafter, as shown in FIG.
A resist film (not shown) is provided on the substrate by performing patterning by photolithography. Using this resist film as a mask, the N-type epitaxial layer 15
For example, Boron is 40 to 80 k as an impurity in the graft base region 23 of the bipolar transistor in
eV acceleration voltage, 5 × 10 ¹⁴ / cm ^{2 to} 5 × 10 ¹⁵ / cm ²
Is implanted at a dose of. Next, thermal diffusion treatment of the graft base region 23 is performed, for example, in a nitrogen atmosphere at 1000
The reaction is performed at a temperature of １1100 ° C. for 200 to 300 minutes. Thus, a P-type diffusion layer 23 in the graft base region located above the diffusion layer 7 in the first collector buried region is formed in the N-type epitaxial layer 15.

Next, as shown in FIG. 8, a resist film (not shown) is provided on the thermal oxide film 17 by performing patterning by photolinography. Using this resist film as a mask, the base region 25 of the bipolar transistor in the N-type epitaxial layer 15 contains, for example, BF ₂ as an impurity at an accelerating voltage of 40 to 80 keV, 5 × 10 ¹³ / cm ^{2 to} 5 × 10 ¹⁴ / cm ² . Ions are implanted at a dose. Thereafter, a thermal diffusion process of the base region 25 is performed, for example, in a nitrogen atmosphere at a temperature of 900 ° C. for 30 minutes. Thereby, the N-type epitaxial layer 1
5, a diffusion layer 25 in a base region located above the diffusion layer 11 in the second collector buried region is formed. Next, the resist film is removed.

After that, a resist film (not shown) is provided on the thermal oxide film 17 by performing patterning by photolithography. Using this resist film as a mask, the emitter region 27 of the bipolar transistor in the N-type epitaxial layer 15 contains, for example, As as an impurity at an acceleration voltage of 30 to 70 keV, 1 × 10 ¹⁵ / cm.
Ions are implanted at a dose of ² to 1 × 10 ¹⁶ / cm ² .
Next, a thermal diffusion process of the emitter region 27 is performed, for example, in a nitrogen atmosphere at a temperature of 950 ° C. for 30 minutes. As a result, an N-type diffusion layer 27 as an emitter region is formed inside the base region 25 in the N-type epitaxial layer 15. Thereafter, the resist film is removed. As a result, the P-type silicon substrate 1 and the N-type epitaxial layer 15
A bipolar transistor 29 is formed.

According to the above embodiment, the second collector buried region diffusion layer 11 thicker than the first collector buried region diffusion layer 7 is provided below the emitter region diffusion layer 27. Therefore, the thickness of the portion having a low impurity concentration of the N-type epitaxial layer 15 located on the diffusion layer 11 in the second collector buried region can be made smaller than that of the conventional bipolar transistor. As a result, the speed at which electrons injected from the emitter are extracted to the collector can be increased, and the speed can be increased. Further, a diffusion layer 7 of a first collector buried region, which is thinner than the diffusion layer 11 of the second collector buried region, is provided below the diffusion layer 23 of the graft base region. For this reason, the portion of the N-type epitaxial layer 15 located on the diffusion layer 7 in the first collector buried region with a low impurity concentration can be made sufficiently thick, and a high breakdown voltage can be achieved. In other words, even if the thickness of the N-type epitaxial layer 15 is made larger than that of the conventional bipolar transistor in order to increase the breakdown voltage, the traveling distance of the carrier in the portion of the N-type epitaxial layer 15 having a low impurity concentration is reduced. It can be shorter than a bipolar transistor, and it is possible to increase the speed. Therefore, in the conventional bipolar transistor, it was not possible to increase the breakdown voltage and increase the speed at the same time. However, in the bipolar transistor, it is possible to increase the breakdown voltage and increase the speed at the same time.

The thickness of the diffusion layer 7 in the first buried collector region is changed to the thickness of the diffusion layer 11 in the second buried collector region.
As shown in FIG. 2 and FIG.
This is because impurities having different diffusion coefficients are ion-implanted. Specifically, As and Pho whose diffusion coefficients differ by about twice are used.
This is because s is ion-implanted. Therefore, by appropriately selecting the impurity to be ion-implanted, the thickness of each of the diffusion layers 7 and 11 in the first and second collector buried regions can be controlled, and the high speed and the high breakdown voltage can be simultaneously realized. The bipolar transistor 29 can be manufactured.

[0029]

As described above, according to the present invention,
By ion-implanting a second impurity having a larger diffusion coefficient than the first impurity into the second collector buried region,
The second buried collector region is formed thicker than the first buried collector region. Therefore, it is possible to provide a semiconductor device and a method for manufacturing the same, which can achieve high withstand voltage and high speed at the same time.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device (N) according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a PN-type bipolar transistor).

FIG. 2 is a cross-sectional view showing a method for manufacturing an NPN bipolar transistor according to one embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a method for manufacturing the NPN-type bipolar transistor according to one embodiment of the present invention, showing a step subsequent to FIG. 2;

FIG. 4 is a cross-sectional view showing a method for manufacturing the NPN-type bipolar transistor according to the embodiment of the present invention, which shows a step subsequent to FIG. 3;

FIG. 5 is a cross-sectional view showing a method of manufacturing the NPN-type bipolar transistor according to the embodiment of the present invention, which shows the next step of FIG. 4;

6 is a cross-sectional view showing a method for manufacturing the NPN bipolar transistor according to one embodiment of the present invention, which is a step subsequent to FIG. 5; FIG.

FIG. 7 is a cross-sectional view showing the method for manufacturing the NPN-type bipolar transistor according to the embodiment of the present invention, which shows the step subsequent to FIG. 6;

8 is a cross-sectional view showing a method for manufacturing the NPN-type bipolar transistor according to one embodiment of the present invention, which shows the next step of FIG. 7. FIG.

FIG. 9 shows a conventional semiconductor device (bipolar transistor).
FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P type silicon substrate, 3 ... Thermal oxide film, 5 ... First resist film, 7a ... First collector buried region, 7 ... First
N-type diffusion layer in the collector buried region, 9 ... second resist film, 11a ... second collector buried region, 11 ...
N-type diffusion layer in the second collector buried region, 13: P-type diffusion layer in the isolation region, 15: N-type epitaxial layer, 17: thermal oxide film, 19: third resist film, 2
1a: Collector extraction region, 21: N-type diffusion layer of collector extraction region, 22: P-type diffusion layer of isolation extraction region, 23: P-type diffusion layer of graft base region, 25: Diffusion layer of base region, 27 ... N-type diffusion layer in the emitter region, 29 ... bipolar transistor, 101 ...
Semiconductor substrate, 115: epitaxial layer, 113: diffusion layer of isolation region for element isolation, 107: diffusion layer of collector buried region, 121: diffusion layer of collector extraction region, 123: diffusion layer of graft base region, 1
25 ... Diffusion layer in base region, 127 ... Diffusion layer in emitter region.

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device in which a bipolar transistor is formed in a semiconductor substrate, the method comprising: ion-implanting a first impurity into a first collector buried region in the semiconductor substrate; Ion-implanting a second impurity having a larger diffusion coefficient than the first impurity into the second collector buried region of the semiconductor substrate located therein; and implanting the first impurity implanted into the first collector buried region.
And a heat treatment step of activating the second impurity implanted in the second collector buried region and the second impurity implanted in the second collector buried region. 2. The method according to claim 1, wherein said semiconductor substrate is made of silicon. 3. The method according to claim 1, wherein the first impurity is As, and the second impurity is Phos.
The manufacturing method of the semiconductor device described in the above. 4. The mask used in the step of ion-implanting the second impurity has the same pattern shape as the mask used in the step of ion-implanting the emitter region. Of manufacturing a semiconductor device. 5. A bipolar transistor formed on a semiconductor substrate, comprising: a first collector buried region formed below the graft base region, formed on the semiconductor substrate; and a thicker than the first collector buried region. And a second collector buried region located below the emitter region, which is formed thick.