JPH03101251A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03101251A JPH03101251A JP23723889A JP23723889A JPH03101251A JP H03101251 A JPH03101251 A JP H03101251A JP 23723889 A JP23723889 A JP 23723889A JP 23723889 A JP23723889 A JP 23723889A JP H03101251 A JPH03101251 A JP H03101251A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- diffusion layer
- impurity diffusion
- isolation region
- type impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000002955 isolation Methods 0.000 claims abstract description 23
- 238000009792 diffusion process Methods 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 20
- 150000004767 nitrides Chemical class 0.000 abstract description 14
- 230000015556 catabolic process Effects 0.000 abstract description 7
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 abstract description 2
- 238000002513 implantation Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- -1 boron ions Chemical class 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明はLOGO3酸化工程により素子分離領域を形成
する半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device in which an element isolation region is formed by a LOGO3 oxidation process.
(従来の技術)
近年、半導体装置の高集積化・高密度化に伴い、回路素
子間の分離がますます重要となってきている。(Prior Art) In recent years, with the increasing integration and density of semiconductor devices, isolation between circuit elements has become increasingly important.
従来、MOSトランジスタ素子間の分離領域を酸化膜分
離法(LOGO8)により形成する際、ナイトライド及
びフォトレジストをマスクとして、ボロンを選択的に分
離領域全体にイオン注入することにより、素子間の分離
を高める方法が知られている。Conventionally, when forming isolation regions between MOS transistor elements by oxide film isolation method (LOGO8), isolation between elements is achieved by selectively implanting boron ions into the entire isolation region using nitride and photoresist as a mask. There are known methods to increase
以下、従来の半導体装置の製造方法について説明する。A conventional method for manufacturing a semiconductor device will be described below.
第2図は従来の半導体装置の主要工程段階での素子分離
領域の断面図であり、1はP型シリコンで構成された半
導体基板、2は半導体基板1の表面に形成された酸化膜
、3は酸化膜2の表面に選択的に形成されたナイトライ
ド膜、4はナイトライド膜3の表面に選択的に形成され
たフォトレジスト膜、5はP型不純物拡散層、6はLO
GO8酸化膜、7は半導体基板1の表面に選択的に形成
されたN型不純物拡散層を示す。FIG. 2 is a cross-sectional view of an element isolation region at the main process stage of a conventional semiconductor device, in which 1 is a semiconductor substrate made of P-type silicon, 2 is an oxide film formed on the surface of the semiconductor substrate 1, and 3 is a nitride film selectively formed on the surface of the oxide film 2, 4 is a photoresist film selectively formed on the surface of the nitride film 3, 5 is a P-type impurity diffusion layer, and 6 is a LO
A GO8 oxide film 7 indicates an N-type impurity diffusion layer selectively formed on the surface of the semiconductor substrate 1.
すなわち、従来の半導体装置の製造方法では第2図(a
)に示すように、半導体基板1の表面に酸化膜2を形成
し、その上にナイトライド膜3及びフォトレジスト膜4
を形成する。次に、フォトリソグラフィ及びエツチング
により、フォトレジスト膜4及びナイトライド膜3に選
択的に開孔部8を形成した後、ボロンイオンを注入し、
P型不純物拡散層5を形成する6次に、第2図(b)に
示すように、フォトレジスト膜4を除去し酸化すること
によりLOGO8酸化膜6を形成した後、ソース・ドレ
イン領域となるN型不純物拡散層7を選択的に形成して
いた。That is, in the conventional method of manufacturing a semiconductor device, as shown in FIG.
), an oxide film 2 is formed on the surface of a semiconductor substrate 1, and a nitride film 3 and a photoresist film 4 are formed thereon.
form. Next, after selectively forming openings 8 in the photoresist film 4 and nitride film 3 by photolithography and etching, boron ions are implanted.
Next, as shown in FIG. 2(b), the photoresist film 4 is removed and oxidized to form a LOGO8 oxide film 6, which will become the source/drain region. The N-type impurity diffusion layer 7 was selectively formed.
(発明が解決しようとする課題)
しかしながら、上記の方法では半導体装置の高集積化・
高密度化に伴い、短い分離幅の領域に高い濃度のP型不
純物拡散層5を必要とし、このため素子の耐圧が低くな
るという問題があった。(Problems to be Solved by the Invention) However, the above method does not allow for high integration and
With the increase in density, a high concentration P-type impurity diffusion layer 5 is required in a region with a short separation width, which causes a problem in that the breakdown voltage of the device becomes low.
(発明の目的) 本発明は上記従来の問題点を解決するもので。(Purpose of the invention) The present invention solves the above-mentioned conventional problems.
高い耐圧を持つ素子分離領域の形成を可能とする半導体
装置の製造方法を提供することを目的とする。An object of the present invention is to provide a method for manufacturing a semiconductor device that enables formation of an element isolation region with high breakdown voltage.
(課題を解決するための手段)
この目的を達成するために本発明の半導体装置の製造方
法は、素子分離領域の半導体基板の中央付近のみに選択
的にP型不純物拡散層を形成する工程を行なう。(Means for Solving the Problems) In order to achieve this object, the method for manufacturing a semiconductor device of the present invention includes a step of selectively forming a P-type impurity diffusion layer only in the vicinity of the center of the semiconductor substrate in the element isolation region. Let's do it.
(作 用)
本発明における素子分離領域の形成方法では、素子分離
領域の半導体基板の中央付近のみ選択的にイオン注入す
ることにより、形成される高い濃度のP型不純物拡散層
が素子のN型不純物拡散層まで広がらないため、高い耐
圧を持つ素子分離領域を形成することができる。(Function) In the method for forming an element isolation region according to the present invention, ions are selectively implanted only in the center of the semiconductor substrate in the element isolation region, so that the formed high concentration P-type impurity diffusion layer becomes an N-type impurity diffusion layer of the element. Since it does not spread to the impurity diffusion layer, an element isolation region with high breakdown voltage can be formed.
(実施例)
以下1本発明の実施例について、図面を参照しながら説
明する。(Example) An example of the present invention will be described below with reference to the drawings.
第1図(a)〜(C)は、本発明の一実施例の主要工程
段階での素子分離領域の断面図を示すものである。第1
図Ca)において、1はP型シリコンで構成された半導
体基板、2は半導体基板1の表面に形成された酸化膜、
3は酸化膜2の表面に選択的に形成されたナイトライド
膜、4はナイトライド膜3の表面に選択的に形成された
フォトレジスト膜を示す。FIGS. 1A to 1C show cross-sectional views of an element isolation region at main process steps in an embodiment of the present invention. 1st
In Figure Ca), 1 is a semiconductor substrate made of P-type silicon, 2 is an oxide film formed on the surface of the semiconductor substrate 1,
Reference numeral 3 indicates a nitride film selectively formed on the surface of the oxide film 2, and reference numeral 4 indicates a photoresist film selectively formed on the surface of the nitride film 3.
第1図(b)において4′はフォトレジスト膜4をベー
ク処理した後のフォトレジスト膜、5はフォトレジスト
膜4′をマスクとして選択的に形成されたP型不純物拡
散層を示す。In FIG. 1(b), 4' indicates a photoresist film after baking the photoresist film 4, and 5 indicates a P-type impurity diffusion layer selectively formed using the photoresist film 4' as a mask.
第1図(c)において6はLOC:O8酸化膜、7は半
導体基板1の表面に選択的に形成されたN型不純物拡散
層を示す。In FIG. 1(c), 6 indicates an LOC:O8 oxide film, and 7 indicates an N-type impurity diffusion layer selectively formed on the surface of the semiconductor substrate 1. In FIG.
まず、第1図(a)において示すように、半導体基板1
の表面に酸化膜2を形成し、その上にナイトライド膜3
及びフォトレジスト膜4を形成する。First, as shown in FIG. 1(a), a semiconductor substrate 1
An oxide film 2 is formed on the surface of the oxide film 2, and a nitride film 3 is formed on it.
and a photoresist film 4 is formed.
次に、フォトリソグラフィ及びエツチングにより、フォ
トレジスト膜4及びナイトライド膜3に選択的に開孔部
8を形成する6次に、第1図(b)に示すようにフォト
レジスト膜4を180℃程度の温度でベーク処理するこ
とにより、ナイトライド膜3の端より0.3ミクロン程
度入り込んだフォトレジスト膜4′を形成した後、フォ
トレジスト膜4′をマスクとしてボロン注入することに
より、半導体基板1の表面に選択的にP型不純物拡散層
5を形成する。これにより、素子分離領域のP型半導体
基板1の中央付近のみに高い濃度のP型不純物拡散層5
を形成しているため、PN接合がN型不純物拡散層とP
型半導体基板1とで作られる。従って、高い濃度のP型
不純物拡散層とでPN接合が作られる従来例よりも、P
N接合からのびる空乏層内の電界が緩和され、高い耐圧
を持つ素子分離領域を形成することができる。Next, openings 8 are selectively formed in the photoresist film 4 and the nitride film 3 by photolithography and etching.Next, the photoresist film 4 is heated to 180° C. as shown in FIG. 1(b). After forming a photoresist film 4' that penetrates about 0.3 microns from the edge of the nitride film 3 by baking at a temperature of about 100 mL, boron is implanted using the photoresist film 4' as a mask to form a semiconductor substrate. A P-type impurity diffusion layer 5 is selectively formed on the surface of 1. As a result, a high concentration P-type impurity diffusion layer 5 is formed only near the center of the P-type semiconductor substrate 1 in the element isolation region.
Since the PN junction is formed between the N type impurity diffusion layer and the P
type semiconductor substrate 1. Therefore, P
The electric field in the depletion layer extending from the N junction is relaxed, and an element isolation region with high breakdown voltage can be formed.
(発明の効果)
以上説明したように本発明は、素子分離領域の半導体基
板の中央付近のみに選択的にP型不純物拡散層を形成す
ることにより、高い耐圧を持つ素子分離領域が形成され
る優れた半導体装置の製造方法を実現できるものである
。(Effects of the Invention) As explained above, the present invention forms an element isolation region with a high breakdown voltage by selectively forming a P-type impurity diffusion layer only near the center of a semiconductor substrate in an element isolation region. This makes it possible to realize an excellent method for manufacturing semiconductor devices.
第1図は本発明の一実施例における半導体装置の製造方
法の主要工程段階の半導体装置の断面図、第2図は従来
の半導体装置の製造方法の主要工程段階の半導体装置の
断面図である。
1 ・・・P型シリコン半導体基板、 2・・・酸化膜
、 3 ・・・ナイトライド膜、 4゜4′ ・・・
フォトレジスト膜、 5 ・・・ P型不純物拡散層、
6・・・LOGO8酸化膜、7・・・N型不純物拡散
層、 8 ・・・開孔部。FIG. 1 is a cross-sectional view of a semiconductor device at a main process step in a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor device at a main process step in a conventional method for manufacturing a semiconductor device. . 1... P-type silicon semiconductor substrate, 2... Oxide film, 3... Nitride film, 4°4'...
Photoresist film, 5... P-type impurity diffusion layer,
6... LOGO8 oxide film, 7... N-type impurity diffusion layer, 8... Opening part.
Claims (1)
形成するに際して、素子分離領域の半導体基板の中央付
近のみに選択的にP型不純物拡散層を形成することを特
徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, which comprises selectively forming a P-type impurity diffusion layer only in the vicinity of the center of the semiconductor substrate in the element isolation region when forming the element isolation region on the semiconductor surface by a LOCOS oxidation process.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23723889A JPH03101251A (en) | 1989-09-14 | 1989-09-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23723889A JPH03101251A (en) | 1989-09-14 | 1989-09-14 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03101251A true JPH03101251A (en) | 1991-04-26 |
Family
ID=17012436
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23723889A Pending JPH03101251A (en) | 1989-09-14 | 1989-09-14 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03101251A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100685896B1 (en) * | 2005-07-07 | 2007-02-26 | 동부일렉트로닉스 주식회사 | Method for fabrication of strained silicon transistor |
US9061540B2 (en) | 2011-09-07 | 2015-06-23 | 3M Innovative Properties Company | Paperclip tab |
-
1989
- 1989-09-14 JP JP23723889A patent/JPH03101251A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100685896B1 (en) * | 2005-07-07 | 2007-02-26 | 동부일렉트로닉스 주식회사 | Method for fabrication of strained silicon transistor |
US9061540B2 (en) | 2011-09-07 | 2015-06-23 | 3M Innovative Properties Company | Paperclip tab |
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