JPH05226351A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a high-frequency and high-speed vertical type PNP transistor by forming a flat low-doped collector area by suppressing the creeping-up of a buried collector layer to an epitaxial layer side by performing diffusion heat treatment, etc., after continuously performing ion implantation two or more times into the epitaxial layer with different acceleration energy. CONSTITUTION:After a buried area 5 is formed on a semiconductor substrate 1 through a photolithographic process, an epitaxial layer 3 is formed on the entire surface of the substrate 1 and a resist 2c is formed on the layer 3 through its oxide film 4. Then an opening is formed by removing the resist 2c and film 4 on the part of layer 3 proposed to a low-doped collector layer 6a and ions are continuously implanted into the opening two or more times with different acceleration energy and diffusion heat treatment is performed. For example, boron ions are implanted by changing the acceleration energy from 500KeV to 50KeV through 300KeV, 150KeV, and 100KeV.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a bipolar IC and a vertical PNP transistor.

[0002]

2. Description of the Related Art FIGS. 4 and 5 show a conventional method of manufacturing a collector portion of a vertical PNP transistor.

First, a resist 11a is formed on a P-type silicon substrate 10, and ³¹ P ⁺ ions are implanted by a photolithography process for forming a bottom surface separation region 12 [FIG. 4 (a)].

Next, after the diffusion heat treatment, the bottom surface separating region 12 is formed.
Ion implantation of ¹¹ B ^{+ with} a high concentration (up to × 10 ¹⁴ dose) is performed by a photolithography process for forming a buried collector region thereon (FIG. 4B).

Next, epitaxial growth is performed to form an epitaxial layer 13 on the P-type silicon substrate 10.
Further, a P ⁺ region 14 for separating the NPN transistor portion is formed [FIG. 4 (c)].

Subsequently, a low concentration (.about. × 10 ¹² do) is formed by a photolithography process for forming the collector region 14a.
se) ¹¹ B ⁺ ion implantation is performed [FIG. 5 (a)]. Then, diffusion heat treatment is performed at 1000 ° C. for about 3 hours to 5 hours to form the low concentration collector region 14a [FIG.
(B)].

The impurity concentration profile of the collector region 14 at this time is shown in FIG. As shown in this figure, the impurity concentration of the epitaxial layer 13 decreases to a predetermined diffusion layer depth, and the diffusion concentration in the low collector layer is not constant.

[0008]

By the way, in the prior art, a low concentration collector region is required to realize a vertical PNP transistor. The collector region is formed by epitaxial growth, photoetching and ion implantation. It was formed by implantation and diffusion heat treatment for a long time.

However, due to this long-time diffusion treatment, there is a problem that the withstand voltage is lowered due to the creeping up of the high-concentration buried collector layer toward the epitaxial layer side. Therefore, it is necessary to make the epitaxial layer sufficiently thick. .. However, on the other hand, as a factor for realizing a high-frequency and high-speed vertical PNP transistor, the epitaxial layer must be thinned, which has been difficult to realize.

The present invention has been made in view of these points, and it is possible to suppress the creeping of the buried collector layer toward the epitaxial layer side and form a flat low-concentration collector region. It is an object of the present invention to provide a manufacturing method for realizing a PNP transistor of the type.

[0011]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises forming a buried region on a semiconductor substrate by a photolithography process, and then forming an epitaxial region on the entire surface of the substrate. After forming a layer and then forming a resist on the epitaxial layer via an oxide film, an opening is provided by removing the resist and the oxide film above the epitaxial layer where the low collector layer is to be formed, and thereafter, It is characterized by having a step of performing a diffusion heat treatment after ion-implanting into the opening portion twice or more continuously at different acceleration energies.

[0012]

The operation of the present invention will be described with reference to FIG. 3 for explaining the operation thereof. The diffusion depth of the ions increases as the acceleration energy of the ions increases. Therefore, the acceleration energy is 500 KeV, 300 KeV,
Change to 150 KeV, 100 KeV, 50 KeV,
When ion implantation is performed continuously, each diffusion distribution becomes
As shown in the figure (a), d ₁ , d ₂ , d ₃ , d
The density profile is ₄ and d ₅ . Furthermore, when the diffusion heat treatment is performed on the substrate in this state, the impurity concentration with respect to the diffusion depth becomes constant, and as shown in FIG. 7B, the concentration profile having a flat portion at any diffusion depth of the low concentration collector region. Becomes

[0013]

1 and 2 are views for explaining an embodiment of the present invention with time. First, a resist 2a is formed on a P-type silicon substrate 1, and ³¹ P ⁺ ions are implanted by a photolithography process for forming the bottom surface separation region 5 [FIG. 1 (a)].

After the diffusion heat treatment, ¹¹ B ⁺ ions of high concentration (up to × 10 ¹⁴ dose) are implanted on the bottom surface isolation region 5 by a photolithography process for forming a buried collector region [FIG. 1]. (B)].

Next, epitaxial growth is performed to form an epitaxial layer 3 on the P-type silicon substrate 1. Further, a P ⁺ region 6 for separating the NPN transistor portion is formed [FIG. 1 (c)].

[0016] Next, an oxide film 4 is formed on the epitaxial layer 3.
After the formation, a resist 2c is formed on the oxide film 4.
Photolithography process for forming collector region
The first high-energy, low-dose boron ion
Injection. In this embodiment, the acceleration energy at this time is 5
00 KeV, dose 2 × 10¹²Do about dose [Fig. 2
(A)].

Subsequently, the dose amount is kept unchanged as 2 × 10 ¹² dose, and the acceleration energy is changed to perform ion implantation continuously for the second time, the third time, the fourth time, and the fifth time. The energy at this time is 300 KeV and 150, respectively.
Ion implantation is performed by changing to KeV, 100 KeV, and 50 KeV [FIG. 2 (b)].

Thereafter, diffusion heat treatment is performed at 1000 ° C. for 30 to 60 minutes to form the low concentration collector layer 6a. [FIG. 2 (c)]. A profile of the impurity concentration of the low concentration collector region thus formed is shown in FIG.

Here, FIG. 10A is a profile after performing ion implantation five times by changing only the above-mentioned acceleration energy, and FIG. 8B is a diffusion heat treatment for forming a collector region. The profile after performing is shown.

That is, the acceleration energy is 500 KeV,
300 KeV, 150 KeV, 100 KeV, 50 Ke
When the ion implantation is continuously performed by changing the value to V, the diffusion distributions of the respective ions are d ₁ , respectively, as shown in FIG.
The density profiles are d ₂ , d ₃ , d ₄ , and d ₅ . Further, when the diffusion heat treatment is performed on the substrate in this state, the impurity concentration with respect to the diffusion depth becomes constant, and a flat concentration profile is obtained at any diffusion depth of the low concentration collector region 6a as shown in FIG. ..

[0021]

As described above, according to the present invention,
Since the diffusion heat treatment is performed after the ion implantation is continuously performed twice or more at different acceleration energies into the opening above the epitaxial layer where the low collector layer is to be formed, the low collector layer can be formed in a short heat treatment time. Can be formed flat, and therefore the creeping up of the buried collector layer toward the epitaxial layer can be suppressed. As a result, the epitaxial layer can be thinned, and high frequency and high speed vertical P
An NP transistor can be realized. In addition, the diffusion heat treatment is useful because it can be significantly shortened as compared with the conventional method.

[Brief description of drawings]

FIG. 1 is a schematic sectional view illustrating an embodiment of the present invention over time.

FIG. 2 is a schematic sectional view illustrating an embodiment of the present invention over time.

FIG. 3 is a diagram illustrating an embodiment of the present invention.

FIG. 4 is a diagram illustrating a conventional example over time.

FIG. 5 is a diagram illustrating a conventional example over time.

FIG. 6 is a diagram illustrating a conventional example.

[Explanation of symbols]

1 ... P type substrate 2a, 2b, 2c ... Resist 3 ... Epitaxial layer 4 ... Oxide film 5 ... Bottom isolation region 6 ... P ⁺ region 6a .... Low-concentration collector layer

Claims (1)

[Claims] 1. A semiconductor substrate is formed with a buried region by a photolithography process, an epitaxial layer is formed on the entire surface of the substrate, and then a resist is formed on the epitaxial layer via an oxide film. An opening is formed by removing the resist and the oxide film above the epitaxial layer where the collector layer is to be formed, and then ion implantation is performed twice or more continuously at different acceleration energies in the opening, followed by diffusion heat treatment. A method of manufacturing a semiconductor device, the method including: