JPH02237037A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPH02237037A JPH02237037A JP1057513A JP5751389A JPH02237037A JP H02237037 A JPH02237037 A JP H02237037A JP 1057513 A JP1057513 A JP 1057513A JP 5751389 A JP5751389 A JP 5751389A JP H02237037 A JPH02237037 A JP H02237037A
- Authority
- JP
- Japan
- Prior art keywords
- impurity concentration
- film
- region
- thickness
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000005468 ion implantation Methods 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims description 38
- 238000009413 insulation Methods 0.000 claims 2
- 239000000758 substrate Substances 0.000 abstract description 17
- 230000010354 integration Effects 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 230000005669 field effect Effects 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 10
- 238000009826 distribution Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- -1 phosphorus ion Chemical class 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
本発明は、ソース・ドレイン拡散層領域がチャネル形成
領域に近接した低不純物濃度領域とそれ以外の高不純物
濃度領域とからなるＭｉｓ型電界効果トランジスタ （
ＦＥＴ）を含む半導体集積回路の製造方法に関する．
〔従来の技術〕
Ｍｉｓ型ＦＥＴの高耐圧化を目的として、ソース・ドレ
イン拡散層領域のチャネル形成領域側端部に、同一の導
電型で比較的低不純物濃度の拡散層領域を設けた構造が
現在広く用いられている．第２図（Ｍｌ〜（ａｌにその
ような構造のＭＯＳ型ＦＥＴの製造方法におけるソース
・ドレイン領域への不純物導入方法を示す．まずＰ型シ
リコン基板ｌ上にゲート酸化膜２を介して形成された多
結晶シリコンゲート電極３をマスクとして、１×１０１
″／一程度の低ドーズ量でりん４のイオン注入を行う（
第２図［ａｌ）．次に、ゲート電極３およびソース・ド
レイン拡散層において低不純物濃度領域とするべき領域
をフォトレジスト膜５で覆った後（第２図（ｂｌ）、今
度は５Ｘ１Ｇ”／一程度の高ドーズ量で再びりんのイオ
ン注入を行う （第２図（Ｃｌ）．次にフォトレジスト
Ｉｌｌ５を除去したのち （第２図（ｄ））、熱処理を
行うことにより、低不純物濃度および高不純物濃度のＮ
型拡散領域６．７をもつ高耐圧構造ＭＯＳ型ＦＥＴのソ
ース・ドレイン拡散、層領域を形成する （第２図ｆｉ
ｌ１）．以上の工程によって形成されたソース・ドレイ
ン低不純物濃度拡散Ｎ６を含むＭＯＳ型ＦＥＴを用いれ
ば、通常のＭＯＳ型ＦＥＴと比較してドレイン拡散層で
の電界集中が緩和されるため、ソース・ドレイン間耐圧
が向上する．
ところで、近年の半導体集積回路装置においては、上記
のような高耐圧化を目的としたＭＩＳ型ＦＥＴと、高速
，高集積化を目的とした微細なＭＩｓ型ＦＥＴとを同一
の基板上に集積する技術が重要となっている．しかし、
高速，高集積化を目的としたＦＥＴと高耐圧化を目的と
したＦＥＴとを同一基板上に集積する場合、以下の問題
点を克服する必要がある．すなわち、高速．高集積化を
目的としたＦＥＴは比較的ゲート絶縁膜厚を薄くする必
要があり、高耐圧化を目的としたＦＥＴは比較的厚くす
ることが必要である．ところが、従来の半導体装置にお
いては、上記２種類のＦＥＴを同一のゲート誘電膜上に
作成していたため、高速，高集積化と高耐圧化を同時に
満足することは極めて困難であった．そこで、この問題
点を克服するための手段として、同一基板上に２種類以
上の膜厚一のゲート誘電膜を備えた構造の半導体装置が
本出願人の特許出願にかかる特願昭６３ − ２０１４
７３号明細書に記載されている．第３図ｆａ）〜（ｄｌ
にこのような半導体装置におけるゲート酸化膜形成工程
の一例を示し、以下にその工程を説明する．まず、通常
の選択酸化法により素子領域以外のＰ型Ｓ１基板１上に
フィールド酸化膜８を形成した後、素子領域に残された
酸化膜を除去する （第３図（ａ））次いで乾燥酸素中
の熱処理により、素子顛域を含むウエハ全面に１８００
人のゲート酸化膜２を形成する （第３図（ｂｌ）．次
に、高耐圧ＮチャネルＭＯＳ型ＦＥＴを形成する方の素
子領域以外の部分を７ォトレジスト膜５で覆った後、前
記素子頷域部分のゲート酸化膜２をぶつ酸によるウェッ
トエソチングにより除去する （第３図（Ｃｌ）．その
後、前記フォトレジスト膜５をＯｘプラズマによるレジ
スト灰化により除去した後、乾燥酸素中の熱処理により
今度は素子領域を含むウエハ全面に４００人の厚さのゲ
ート酸化膜を形成する．以上の工程により高耐圧Ｎ型Ｆ
ＥＴの素子領域には２０００人の厚さのゲート酸化膜２
１，高集積．高速Ｎ型ＦＥＴの素子領域には４００人の
厚さのゲート酸化膜２２を得ることができる （第３図
（ｄ））
〔発明が解決しようとする課題〕
第２図および第３図に示した製造方法は、それぞれ高耐
圧化を目的としたＭＩＳ型ＦＥＴと、高速．高集積化を
目的としたＭＩＳ型ＦＥＴとを同一基板上に作成するこ
とに通した製造方法であり、両方の製造方法を紐合わせ
ることによって高耐圧ＭＴＳ型ＦＥＴと高速．高集積Ｍ
ＩＳ型ＦＥＴを同一基板上に作成でき、しかもゲート絶
縁膜厚を高耐圧ＦＥＴでは厚くし、高速．高集積ＦＥＴ
では薄くすることができる．ところが、これ・らの製造
方法を単純に組合わせた場合、それぞれの目的に対応し
て追加された工程数は、単純に加算されることになり、
従来の標準的なＭＩＳ型ＦＥＴの製造工程に比べ非常に
多くなってしまうという欠点があった．
本発明の目的は、高耐圧Ｍｉｓ型ＦＥＴが異なる種類の
ＭＴＳ型ＦＥＴと同一半導体基板に集積する場合でも工
程数が少ない半導体集積回路の・製造方法を提供するこ
とにある．
〔課題を解決するための手段〕
上記の目的の達成のために、本発明は、ソース・ドレイ
ン拡散層領域がチャネル形成領域に近接した低不純物濃
度領域とそれ以外の高不純物濃度領域とからなるＭＩＳ
型ＦＥＴを含む半導体集積回路の製造方法において、前
記低不純物濃度拡散層領域と高不純物濃度拡散Ｎ ６１
域を形成する際に、低不純物濃度拡散層を形成する領域
上部のゲート絶縁膜厚を高不純物濃度拡散層を形成する
領域上部のゲート絶縁膜厚と比較して厚くし、これらの
ゲート絶縁膜とゲート電極とをマスクにしてイオン注入
を行うものとする．
〔作用〕
ゲート絶縁膜の異なる領域上にイオン注入で不純物導入
を行うことにより、一度だけのイオン注人により２種類
の不純物濃度をもった拡散層領域を形成することができ
、これにより高耐圧化を目的としたＭＩＳ型ＦＥＴのソ
ース・ドレイン拡散層の低不純物濃度領域および高不純
物濃度領域が、例えば高速１高集積化を目的としたＭＩ
Ｓ型ＦＥＴのソース・ドレイン拡散層と同一工程で同一
半導体基板に形成できるので、工程数を低減することが
できる．
〔実施例〕
第１図＋Ｉｌｌ〜ｔｅｌは本発明の一実施例における製
造工程を高耐圧ＭＯＳ型ＦＥＴの部分について各図の左
側に、同一基板上の高速，高集積ＭＯＳ型ＦＥＴについ
て各図の右側にそれぞれ示したものであり、第２図，第
３図と共通の部分には同一の符号が付されている．まず
第３図に示した方法と同様に１８００人のゲート酸化ｌ
Ｉｌ２をＰ型Ｓ１基板上全面に形成し（第１図（ａｌ）
、その酸化膜の選択エッチングと乾燥酸素中の熱処理に
より２種類の膜厚のゲート酸化膜２１．２２を形成する
（第１図（ｂｌ）．この際、高耐圧ＭＯＳ型ＦＥＴに
おいては低不純物？度拡散層を作成する領域上のゲート
酸化膜２２の厚さは２０００人、高不純物濃度拡散層を
作成する領域上のゲート酸化膜２ｌの厚さは４００人と
する．また高速，高集積ＭＯＳ型ＦＥＴにおいては膜厚
４００人のゲート酸化膜２ｌを形成する．次に多結晶シ
リコンによってゲート電極３を形成したのち（第ｌ図ｆ
ｅ））、ゲート電極３をマスクとして自己整合的にりん
４のイオン注入を行う （第１図（ｄ１） このとき
のイオン注入条件は、Ｐ３１ イオンを用いて加速電
圧９０ｋｅＶ，ドーズｆ３．５ ＸＩＯ”／ａ＋１であ
る。Detailed Description of the Invention (Industrial Application Field) The present invention provides a mis-type field effect device in which a source/drain diffusion layer region is composed of a low impurity concentration region close to a channel forming region and a high impurity concentration region other than the channel formation region. Transistor (
This invention relates to a method for manufacturing semiconductor integrated circuits including FETs. [Prior Art] In order to increase the breakdown voltage of a Mis-type FET, a structure has been developed in which a diffusion layer region of the same conductivity type and a relatively low impurity concentration is provided at the end of the source/drain diffusion layer region on the side of the channel formation region. Currently widely used. Figure 2 (Ml~(al) shows a method of introducing impurities into the source/drain regions in the manufacturing method of a MOS type FET with such a structure. Using the polycrystalline silicon gate electrode 3 as a mask, 1×101
Ion implantation of phosphorus 4 is carried out at a low dose of about 1.
Figure 2 [al). Next, after covering the regions of the gate electrode 3 and the source/drain diffusion layer that should be low impurity concentration regions with a photoresist film 5 (Fig. Phosphorus ion implantation is performed again (Fig. 2 (Cl)).Next, after removing the photoresist Ill5 (Fig. 2 (d)), by performing heat treatment, N of low impurity concentration and high impurity concentration is implanted.
Forming the source/drain diffusion and layer regions of a high breakdown voltage structure MOS type FET having a type diffusion region 6.7 (Fig. 2 fi)
l1). If the MOS type FET including the source/drain low impurity concentration diffusion N6 formed by the above process is used, electric field concentration in the drain diffusion layer is relaxed compared to a normal MOS type FET, so Improves pressure resistance. Incidentally, in recent semiconductor integrated circuit devices, MIS type FETs intended for high breakdown voltage as described above and minute MIs type FETs intended for high speed and high integration are integrated on the same substrate. Technology is becoming important. but,
When integrating FETs aimed at high speed and high integration and FETs aimed at high breakdown voltage on the same substrate, the following problems must be overcome. In other words, high speed. FETs intended for high integration need to have a relatively thin gate insulating film, and FETs intended for high breakdown voltage need to have a relatively thick gate insulating film. However, in conventional semiconductor devices, the above two types of FETs were fabricated on the same gate dielectric film, making it extremely difficult to simultaneously satisfy high speed, high integration, and high breakdown voltage. Therefore, as a means to overcome this problem, a semiconductor device having a structure in which two or more types of gate dielectric films of the same thickness are provided on the same substrate is disclosed in Japanese Patent Application No. 63-2014 filed by the present applicant.
It is described in specification No. 73. Figure 3 fa) ~ (dl
An example of a process for forming a gate oxide film in such a semiconductor device is shown below, and the process will be explained below. First, a field oxide film 8 is formed on the P-type S1 substrate 1 in areas other than the element area by the usual selective oxidation method, and then the oxide film left in the element area is removed (Fig. 3(a)). During the heat treatment, the entire surface of the wafer including the device area is coated with 1800%
Form a gate oxide film 2 (FIG. 3(bl)) Next, after covering the area other than the element region where the high breakdown voltage N-channel MOS FET is to be formed with a photoresist film 5, The gate oxide film 2 in the area is removed by wet etching with butic acid (Fig. 3 (Cl)).Then, the photoresist film 5 is removed by resist ashing with Ox plasma, and then heat treated in dry oxygen. Next, a gate oxide film with a thickness of 400 nm is formed on the entire surface of the wafer including the element area.The above steps form a high breakdown voltage N-type F
There is a gate oxide film 2 with a thickness of 2,000 people in the ET element area.
1. High accumulation. A gate oxide film 22 with a thickness of 400 mm can be obtained in the element region of a high-speed N-type FET (Fig. 3(d)) [Problem to be solved by the invention] As shown in Figs. 2 and 3. The manufacturing methods used are MIS type FET, which aims to achieve high voltage resistance, and high-speed. This is a manufacturing method that creates MIS type FETs for the purpose of high integration on the same substrate, and by combining both manufacturing methods, high voltage MTS type FETs and high speed. High integration M
IS-type FETs can be fabricated on the same substrate, and the gate insulating film thickness can be increased for high-voltage FETs, allowing high-speed operation. Highly integrated FET
You can make it thinner. However, if these manufacturing methods are simply combined, the number of steps added for each purpose will simply be added.
This method has the disadvantage that it requires a much larger number of manufacturing steps than the conventional standard MIS type FET manufacturing process. An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit that requires fewer steps even when a high voltage Mis-type FET is integrated on the same semiconductor substrate as a different type of MTS-type FET. [Means for Solving the Problems] In order to achieve the above object, the present invention provides a source/drain diffusion layer region consisting of a low impurity concentration region close to a channel forming region and a high impurity concentration region other than the region. M.I.S.
In the method of manufacturing a semiconductor integrated circuit including a type FET, the low impurity concentration diffusion layer region and the high impurity concentration diffusion layer region N61
When forming the regions, the thickness of the gate insulating film above the region where the low impurity concentration diffusion layer is formed is made thicker than the gate insulating film thickness above the region where the high impurity concentration diffusion layer is formed. Ion implantation is performed using the gate electrode and the gate electrode as masks. [Operation] By introducing impurities into different regions of the gate insulating film by ion implantation, it is possible to form diffusion layer regions with two types of impurity concentrations with just one ion implanter, which allows for high breakdown voltage. For example, the low impurity concentration region and the high impurity concentration region of the source/drain diffusion layer of an MIS type FET intended for high-speed integration are
Since it can be formed on the same semiconductor substrate in the same process as the source/drain diffusion layer of the S-type FET, the number of process steps can be reduced. [Example] Figure 1 +Ill to tel shows the manufacturing process in one embodiment of the present invention for a high-voltage MOS FET on the left side of each figure, and for a high-speed, highly integrated MOS FET on the same substrate. They are shown on the right side, and the same parts as in Figures 2 and 3 are given the same reference numerals. First, 1,800 gate oxidizers were prepared using the method shown in Figure 3.
Il2 is formed on the entire surface of the P-type S1 substrate (Fig. 1 (al)
, gate oxide films 21 and 22 with two different thicknesses are formed by selective etching of the oxide film and heat treatment in dry oxygen (Fig. 1 (bl)). The thickness of the gate oxide film 22 on the region where the high impurity concentration diffusion layer is created is 2000, and the thickness of the gate oxide film 2l on the region where the high impurity concentration diffusion layer is created is 400. In the type FET, a gate oxide film 2l with a thickness of 400 nm is formed.Next, after forming a gate electrode 3 of polycrystalline silicon (Fig.
e)), ion implantation of phosphorus 4 is performed in a self-aligned manner using the gate electrode 3 as a mask (Fig. 1 (d1)) The ion implantation conditions at this time are P31 ions, acceleration voltage 90 keV, dose f 3.5 XIO ”/a+1.
この際Ｐ型シリコン基板に到達するＰ，１゛イオン４の
量は、その基板表面にあるゲート酸化膜厚に依存し、ゲ
ート酸化膜厚が厚いほどシリコン基板に到達するＰ■
イオンの量は少ない．従って窒素雰囲気中で熱処理を行
い、Ｐ３１゛イオンを拡散・活性化してＮ型拡散層を形
成した場合（第１図（ｅｌ ）、膜厚２０００人のゲー
ト酸化膜２２の下の拡散層はＮ型低不純物濃度拡散層の
ソース・ドレイン領域６、膜厚４００人のゲート酸化膜
２１の下の拡散層は、Ｎ型高不純物濃度拡散層のソース
・ドレイン領域７となる．上記拡散層の濃度分布を第４
図，第５図に示す．第４図はＮ型高不純物濃度拡散層７
の濃度分布、第５図はＮ型低不純物濃度拡散層６の濃度
分布となっている．両図において＆ｊｌｌｌがＮ型、＆
ｌ１２がＰ型の濃度分布である．この図からわかるよう
に、Ｎ型高不純物濃度拡散層７は高速，高集積ＦＥＴを
駆動させるのに適した濃度分布となっており、またＮ型
低不純物濃度拡散層６は高耐圧ＦＥＴにおいてドレイン
部電界集中を緩和するのに十分な濃度分布となっている
．
以上の方法によれば、ゲート酸化膜厚を２種類、同一基
板上に作成する第３図に示した従来方法による製造工程
を全く変えずに、ゲート酸化膜厚をエッチングにより２
種類に分けるためのパターンの高耐圧ＭＯＳ型ＦＥＴに
おけるソース・ドレイン部のみを変化させることによっ
て、第２図に示したような高耐圧ＦＥＴを高速，高集積
ＦＥＴと同一基板上に作成することができた．つまり第
２図および第３図における従来方法を組合わせた場合と
比較して、第２図における低不純物濃度拡散層形成工程
、第２図（ａ），（ｂｌが省略できることになる．
〔発明の効果〕
本発明によれば、高耐圧ＭｒＳ型ＦＥＴと高速．高集積
ＭＩＳ型ＦＥＴとの厚さの異なるゲート絶縁膜を同一基
板上に形成する既出願の方法に基づく工程を利用し、高
耐圧ＭＩＳ型ＦＥＴのソース・ドレイン部のゲート絶縁
膜の膜厚を２種類に分けるためのパターンを用意するの
みで、１回のイオン注入工程で高耐圧ＭＩＳ型ＦＥＴと
、例えば高速，高集積ＭＩＳ型ＦＥＴとのソース・ドレ
イン部が同時に形成でき、高，低不純物濃度のソース・
ドレイン拡散層領域を必要とする高耐圧Ｍ ｒ Ｓ．型
ＦＥＴを含む半導体集積回路の製造の際の工程数低減に
極めて有効である．At this time, the amount of P,1' ions 4 that reach the P-type silicon substrate depends on the thickness of the gate oxide film on the substrate surface, and the thicker the gate oxide film, the more P,1' ions that reach the silicon substrate.
The amount of ions is small. Therefore, when heat treatment is performed in a nitrogen atmosphere to diffuse and activate P31 ions to form an N-type diffusion layer (Fig. 1 (el)), the diffusion layer under the gate oxide film 22 with a thickness of 2000 The source/drain region 6 of the type low impurity concentration diffusion layer and the diffusion layer under the gate oxide film 21 with a film thickness of 400 will become the source/drain region 7 of the N type high impurity concentration diffusion layer. The fourth distribution
As shown in Fig. 5. Figure 4 shows an N-type high impurity concentration diffusion layer 7.
FIG. 5 shows the concentration distribution of the N-type low impurity concentration diffusion layer 6. In both figures, &jllll is N type, &
l12 is the concentration distribution of P type. As can be seen from this figure, the N-type high impurity concentration diffusion layer 7 has a concentration distribution suitable for driving a high-speed, highly integrated FET, and the N-type low impurity concentration diffusion layer 6 is used as a drain in a high-voltage FET. The concentration distribution is sufficient to alleviate the electric field concentration. According to the above method, the thickness of the gate oxide film can be changed to two types by etching without changing the manufacturing process of the conventional method shown in FIG.
By changing only the source/drain parts of the high-voltage MOS type FET in the pattern for dividing into different types, it is possible to create a high-voltage FET as shown in Figure 2 on the same substrate as a high-speed, highly integrated FET. did it. In other words, compared to the case where the conventional methods shown in FIGS. 2 and 3 are combined, the low impurity concentration diffusion layer forming step shown in FIG. 2 and FIGS. 2(a) and 2(bl) can be omitted. [Invention According to the present invention, high-voltage MrS-type FETs and high-speed, high-integration MIS-type FETs are formed using a process based on a previously applied method of forming gate insulating films with different thicknesses on the same substrate. By simply preparing a pattern to divide the thickness of the gate insulating film in the source/drain part of a high-voltage MIS FET into two types, a high-voltage MIS FET and, for example, a high-speed, highly integrated MIS can be produced in a single ion implantation process. The source and drain parts of type FET can be formed at the same time, and the source and drain parts with high and low impurity concentrations can be formed.
High breakdown voltage Mr S. which requires a drain diffusion layer region. It is extremely effective in reducing the number of steps when manufacturing semiconductor integrated circuits including type FETs.
第１図（５）〜（ａｌは本発明の一実施例における製造
工程を高耐圧ＭＯＳ型ＦＥＴの部分について各図の左側
に、高速．高集積ＭＯＳ型ＦＥＴについて各図の右側に
それぞれ順次示した断面図、第２図ｌａｌ〜［ａｌは従
来の高耐圧ＭＯＳ型ＦＥＴの製造工程を順次示す断面図
、第３図ｆａｌ〜（ｄｌは同一半導体基板に２種類のゲ
ート酸化膜を形成する既出願の工程を順次示す断面図、
第４図は本発明の一実施例により形成された高不純物濃
度Ｎ型拡散層の濃度分布図、第５図は同じく低不純物濃
度Ｎ型拡散層の濃度分布図である．
ｌ：Ｐ型シリコン基板、２ ： １８００人ゲート酸化
膜、２１ ： ４００人ゲート酸化膜、２２ ： ２０
００人ゲート酸化膜、３：ゲート電極、４：りんイオン
、６：Ｎ型低不純物濃度ソース・ドレイン拡散層、７：
Ｎ型高不純物濃度ソース・ドレイン拡散層．第２図
第１図
第３図Figures 1 (5) to (al) show the manufacturing process in one embodiment of the present invention on the left side of each figure for a high-voltage MOS FET, and on the right side of each figure for a high-speed, highly integrated MOS FET. Figure 2 is a cross-sectional view showing the manufacturing process of a conventional high-voltage MOS FET, and Figure 3 is a cross-sectional view showing the manufacturing process of a conventional high-voltage MOS FET. Cross-sectional diagrams sequentially showing the application process,
FIG. 4 is a concentration distribution diagram of a high impurity concentration N-type diffusion layer formed according to an embodiment of the present invention, and FIG. 5 is a concentration distribution diagram of a low impurity concentration N-type diffusion layer. l: P-type silicon substrate, 2: 1800 person gate oxide film, 21: 400 person gate oxide film, 22: 20
00 gate oxide film, 3: gate electrode, 4: phosphorus ion, 6: N-type low impurity concentration source/drain diffusion layer, 7:
N-type high impurity concentration source/drain diffusion layer. Figure 2 Figure 1 Figure 3
Claims (1)
近接した低不純物濃度領域とそれ以外の高不純物濃度領
域とからなるＭＩＳ型ＦＥＴを含む半導体集積回路の製
造方法において、前記低不純物濃度拡散層領域と高不純
物濃度拡散層領域を形成する際に、低不純物濃度拡散層
を形成する領域上部のゲート絶縁膜厚を高不純物濃度拡
散層を形成する領域上部のゲート絶縁膜厚と比較して厚
くし、これらのゲート絶縁膜とゲート電極とをマスクに
してイオン注入を行うことを特徴とする半導体集積回路
の製造方法。1) In a method for manufacturing a semiconductor integrated circuit including a MIS type FET in which the source/drain diffusion layer region is composed of a low impurity concentration region close to a channel forming region and a high impurity concentration region other than the low impurity concentration region, the low impurity concentration diffusion layer region When forming the high impurity concentration diffusion layer region, the gate insulation film thickness above the region where the low impurity concentration diffusion layer is formed is made thicker than the gate insulation film thickness above the region where the high impurity concentration diffusion layer is formed. A method for manufacturing a semiconductor integrated circuit, characterized in that ion implantation is performed using these gate insulating films and gate electrodes as masks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1057513A JP2596117B2 (en) | 1989-03-09 | 1989-03-09 | Method for manufacturing semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1057513A JP2596117B2 (en) | 1989-03-09 | 1989-03-09 | Method for manufacturing semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02237037A true JPH02237037A (en) | 1990-09-19 |
| JP2596117B2 JP2596117B2 (en) | 1997-04-02 |
Family
ID=13057818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1057513A Expired - Fee Related JP2596117B2 (en) | 1989-03-09 | 1989-03-09 | Method for manufacturing semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2596117B2 (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06120249A (en) * | 1991-12-24 | 1994-04-28 | Semiconductor Energy Lab Co Ltd | Manufacture of mos transistor and structure thereof |
| JPH08236771A (en) * | 1996-03-22 | 1996-09-13 | Semiconductor Energy Lab Co Ltd | Mos-type transistor |
| US5918116A (en) * | 1994-11-30 | 1999-06-29 | Lucent Technologies Inc. | Process for forming gate oxides possessing different thicknesses on a semiconductor substrate |
| US6268251B1 (en) * | 2000-07-12 | 2001-07-31 | Chartered Semiconductor Manufacturing Inc. | Method of forming MOS/CMOS devices with dual or triple gate oxide |
| US6337231B1 (en) | 1993-05-26 | 2002-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
| KR100552296B1 (en) * | 1998-11-04 | 2006-06-07 | 삼성전자주식회사 | Manufacturing Method of Polycrystalline Silicon Thin Film Transistor Board |
| JP2012195607A (en) * | 2012-06-13 | 2012-10-11 | Lapis Semiconductor Co Ltd | High breakdown voltage field-effect transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59161870A (en) * | 1983-03-07 | 1984-09-12 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS62252164A (en) * | 1986-04-21 | 1987-11-02 | エツセヂエツセ ミクロエレツトロ−ニカ エツセ・ピ・ア | Mos type integrated semiconductor device with gate oxide of nonuniform thickness and manufacture of the same |
| JPS63252459A (en) * | 1987-04-09 | 1988-10-19 | Seiko Epson Corp | Semiconductor device |
-
1989
- 1989-03-09 JP JP1057513A patent/JP2596117B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59161870A (en) * | 1983-03-07 | 1984-09-12 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS62252164A (en) * | 1986-04-21 | 1987-11-02 | エツセヂエツセ ミクロエレツトロ−ニカ エツセ・ピ・ア | Mos type integrated semiconductor device with gate oxide of nonuniform thickness and manufacture of the same |
| JPS63252459A (en) * | 1987-04-09 | 1988-10-19 | Seiko Epson Corp | Semiconductor device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06120249A (en) * | 1991-12-24 | 1994-04-28 | Semiconductor Energy Lab Co Ltd | Manufacture of mos transistor and structure thereof |
| US7087962B1 (en) | 1991-12-24 | 2006-08-08 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming a MOS transistor having lightly dopped drain regions and structure thereof |
| US6337231B1 (en) | 1993-05-26 | 2002-01-08 | Semiconductor Energy Laboratory Co., Ltd. | Method for producing semiconductor device |
| US5918116A (en) * | 1994-11-30 | 1999-06-29 | Lucent Technologies Inc. | Process for forming gate oxides possessing different thicknesses on a semiconductor substrate |
| JPH08236771A (en) * | 1996-03-22 | 1996-09-13 | Semiconductor Energy Lab Co Ltd | Mos-type transistor |
| KR100552296B1 (en) * | 1998-11-04 | 2006-06-07 | 삼성전자주식회사 | Manufacturing Method of Polycrystalline Silicon Thin Film Transistor Board |
| US6268251B1 (en) * | 2000-07-12 | 2001-07-31 | Chartered Semiconductor Manufacturing Inc. | Method of forming MOS/CMOS devices with dual or triple gate oxide |
| JP2012195607A (en) * | 2012-06-13 | 2012-10-11 | Lapis Semiconductor Co Ltd | High breakdown voltage field-effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2596117B2 (en) | 1997-04-02 |
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