JPH0541385A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the emitter-base junction breakdown strength of a semiconductor device. CONSTITUTION:An n<-> epitaxial layer 2 is formed on an n<+> silicon substrate or an n<+> diffusion layer 1; a p-type base region 4 is formed; after that, a silicon oxide film 5 is formed; a hole for impurity introduction use is formed in the silicon oxide film 5 phosphorus (P) is introduced by an oblique spinning ion implantation method by making use of the hole for impurity introduction use. Thereby, an n-type impurity region 10 is formed. Arsenic (As) is diffused. Thereby, an n<+> type emitter region 4 is formed. Thereby, an electric field in an emitter-base junction part is relaxed by the n-type impurity region 10 formed on the outer circumference of the n<+> type emitter region 4, and the emitter-base junction breakdown strength of the title device is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique for improving a breakdown voltage of an emitter-base junction of a bipolar transistor and reducing a tunnel current.

[0002]

2. Description of the Related Art FIGS. 6 and 7 are characteristic diagrams showing an element structure of a conventional npn-type bipolar transistor and an impurity concentration distribution just below the emitter of the element.

[0003] In FIG. 6, 1 is n ⁺ silicon substrate or n ⁺ diffusion layer, 2 n grown on the n ⁺ silicon substrate or n ⁺ diffusion layer 1 ^- is an epitaxial layer.

Reference numeral 5 is a silicon oxide film, which is formed by sequentially introducing impurities from windows formed in the silicon oxide film 5.
4 p-type base regions and 4 n ⁺ -type emitter regions are formed. 6 is an emitter metal electrode and 7 is a base metal electrode.

FIG. 7 is a characteristic diagram showing the impurity concentration distribution in the depth direction in the section II 'of FIG. Curves A _s and B shown in the characteristic diagram represent arsenic and boron concentrations in the emitter and base diffusions, respectively, and a broken line S _b represents antimony concentration in the collector regions (layers 1 and 2), respectively.

Next, FIGS. 20 and 21 show another n-type bipolar transistor having an element structure different from that of the npn-type bipolar transistor.
The characteristic view which shows the element structure of a pn-type bipolar transistor and the impurity concentration distribution just under the emitter of the element is shown. The npn-type bipolar transistor shown in FIG. 20 is
It is characterized by having an advanced self-aligned structure.

In FIG. 20, 51 is an n ⁺ silicon substrate or an n ⁺ diffusion layer, and 52 is an n ⁺ silicon substrate or an n ^+.
This is an n ⁻ epitaxial layer grown on the diffusion layer 51, and this n ⁻ epitaxial layer 52 is used as a collector region. Next, 53 is a base lead-out electrode formed of boron-implanted polysilicon, and 54 is polysilicon 5
3 is an oxide film formed on 3; 55 is an external base region;
Is an intrinsic base region, 57 is a sidewall film formed of an oxide film, 5
8 is an emitter lead electrode formed of polysilicon,
59 is an emitter region.

N having this advanced self-aligned structure
To make a pn-type bipolar transistor, an n ^- epitaxial layer 52 is grown on an n ⁺ silicon substrate or an n ⁺ diffusion layer 51 to form a collector region, for example, an oxide film is separated (not shown). , Npn-type bipolar transistors are determined. next,
After depositing polysilicon on the n ⁺ silicon substrate or the n ⁺ diffusion layer 51 and implanting boron at an accelerating voltage such that boron is retained in the polysilicon, a temperature at which boron does not diffuse into the n ⁻ epitaxial layer 52. Then, an oxide film 54 is deposited. Next, the oxide film 54 in the portion where the intrinsic base region is to be formed and the polysilicon under the oxide film 54 are sequentially etched to form an opening, and boron is injected from this opening.
Next, an oxide film is deposited on the entire surface of the n ⁺ silicon substrate or the n ⁺ diffusion layer 51, and the oxide film is anisotropically etched to form a sidewall film 57 on the sidewall of the opening.
Next, arsenic is implanted using the oxide film 4 and the sidewall film 57 as a mask. Polysilicon is deposited to form an emitter extraction electrode, and arsenic is implanted to reduce the emitter resistance. Finally, heat treatment is applied to the external base region 55, the intrinsic base region 56, the emitter region 59, the base extraction electrode 53, and the emitter extraction electrode 5.
8 is formed.

FIG. 21 shows I of FIG. 20 of the npn type bipolar transistor having the advanced self-aligned structure.
FIG. 11 is a characteristic diagram showing an impurity concentration distribution in the depth direction in a II-III ′ cross section. Curves A _s and B shown in the characteristic diagram
Indicates the arsenic and boron concentrations in the emitter and base diffusions, respectively, and the broken line S _b indicates the antimony concentration in the collector regions (layers 51 and 52), respectively.

[0010]

From the characteristic diagrams shown in FIGS. 7 and 21, the base concentration of the emitter-base junction is 10 ¹⁸ cm ^{−3 at} a relatively deep portion, that is, the lower surface of the n ⁺ type emitter region 4. As will be described below, it can be seen that the base concentration of the emitter-base junction reaches a maximum of 5 × 10 ¹⁸ cm ⁻³ at a relatively shallow portion, that is, the side surface of the n ⁺ type emitter region 4. Therefore, in the conventional semiconductor device, for example, when the intrinsic base concentration is increased to reduce the base resistance, the electric field is increased particularly in the side surface portion of the emitter region, and the emitter-base junction breakdown voltage is lowered. ..

Further, when the voltage between the base and the emitter is low, the tunnel current flowing from the base to the emitter has a great influence, and the current amplification factor (collector current / base current) is lowered.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of improving the breakdown voltage of the emitter-base junction and reducing the tunnel current, and a method of manufacturing the same.

[0013]

A semiconductor device according to a first invention is a semiconductor device having a first conductivity type collector region, a second conductivity type base region formed on the first conductivity type collector region, and a second conductivity type collector region. A first conductivity type emitter region formed on the conductivity type base region and a first conductivity type emitter region formed on the second conductivity type base region so as to be in contact with the outer periphery of the first conductivity type emitter region. And a first-conductivity-type impurity region having a lower concentration than the impurity concentration of.

A semiconductor device according to a second invention is the semiconductor device according to the first invention formed on a semiconductor substrate, wherein an emitter extraction electrode formed on the first conductivity type emitter region, A base lead-out electrode formed on the second conductivity type base region, and a plurality of layers formed on the side wall of the base lead-out electrode between the base lead-out electrode and the emitter lead-out electrode, The innermost layer is provided with a sidewall film made of an insulator.

A method of manufacturing a semiconductor device according to a third aspect of the present invention includes a step of forming a first conductivity type collector region, a step of forming a second conductivity type base region on the first conductivity type collector region, and Forming an insulating film on the second conductive type base region; forming an impurity introducing hole in the insulating film; introducing a first conductive type impurity from the impurity introducing hole; A step of forming a first conductivity type emitter region on a conductivity type base region, wherein a first conductivity type impurity is introduced by oblique rotation ion implantation from the impurity introduction hole, A step of forming a first-conductivity-type impurity region having a concentration lower than that of the first-conductivity-type emitter region so as to contact the outer periphery of the first-conductivity-type emitter region on the second-conductivity-type base region; And it features.

A method of manufacturing a semiconductor device according to a fourth aspect of the present invention includes a first conductivity type collector region formed on a semiconductor substrate, and a second conductivity type base region formed on the first conductivity type collector region. A first conductive type emitter region formed on the second conductive type base region, an emitter lead electrode formed on the first conductive type emitter region, and a second conductive type base region formed on the second conductive type base region. A method for manufacturing a semiconductor device, comprising: a base lead-out electrode; and a sidewall film formed on a sidewall of the base lead-out electrode,
The side wall film is formed of a first side wall film made of an insulator and formed on a side wall portion of the base lead electrode, and a second side wall film formed on a side wall of the first side wall film. Forming the first side wall film on the side wall of the base lead-out electrode, and using the first side wall film as a mask
A step of introducing a first conductivity type impurity into the conductivity type base region; a step of forming the second sidewall film on a sidewall of the first sidewall film; and a step of using the first and second sidewall films as a mask. Introducing the first conductivity type impurity into the second conductivity type base region, and the first conductivity type emitter region and the first conductivity type emitter due to the first conductivity type impurity introduced into the second conductivity type base region. And a step of forming a first conductivity type impurity region having a lower impurity concentration than the first conductivity type emitter region around the region.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first conductive type collector region formed on a semiconductor substrate; and a second conductive type base region formed on the first conductive type collector region. A first conductive type emitter region formed on the second conductive type base region, an emitter lead electrode formed on the first conductive type emitter region, and a second conductive type base region formed on the second conductive type base region. A method for manufacturing a semiconductor device, comprising: a base lead-out electrode; and a sidewall film formed on a sidewall of the base lead-out electrode,
A first sidewall film made of an insulator, the sidewall film being formed on a sidewall portion of the base extraction electrode, and a second sidewall containing a first conductivity type impurity formed on a sidewall of the first sidewall film. A step of forming the first side wall film on the side wall of the base extraction electrode, and forming the second side wall film containing a first conductivity type impurity on the side wall of the first side wall film. And a step of introducing a first conductivity type impurity into the second conductivity type base region by using the first and second sidewall films as a mask, and a second heat treatment from the second sidewall type base to the second conductivity type base by heat treatment. A first conductivity type impurity is introduced into the region, and the first conductivity type impurity introduced into the second conductivity type base region by the heat treatment is applied to the first conductivity type emitter region and the periphery of the first conductivity type emitter region. The first
And a step of forming a first conductivity type impurity region having a first conductivity type impurity concentration lower than that of the conductivity type emitter region.

A method of manufacturing a semiconductor device according to a sixth aspect of the present invention includes a first conductivity type collector region formed on a semiconductor substrate, and a second conductivity type base region formed on the first conductivity type collector region. A first conductive type emitter region formed on the second conductive type base region, an emitter lead electrode formed on the first conductive type emitter region, and a second conductive type base region formed on the second conductive type base region. A method for manufacturing a semiconductor device, comprising: a base lead-out electrode; and a sidewall film formed between the base lead-out electrode and the emitter lead-out electrode at a side wall of the base lead-out electrode. Using the sidewall film as a mask, an impurity of the first conductivity type is introduced by oblique rotation ion implantation so as to contact the outer periphery of the first conductivity type emitter region on the second conductivity type base region. It is characterized in that a step of forming a first-conductive type impurity region of lower concentration than the impurity concentration of said first conductivity type emitter region.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the third, fourth or sixth invention, wherein the first sidewall film is used as a mask in the second conductivity type base region. Before the step of introducing the first conductivity type impurity, at least one kind of ion of an inert ion, a halogen ion, and a group IV element ion is implanted to amorphize at least the region where the first conductivity type impurity region is to be formed. It is characterized by doing.

[0020]

According to the semiconductor device of the first and second inventions, the first conductivity type is provided on the outer periphery of the first conductivity type emitter region of the emitter-base junction where the base concentration in the second conductivity type base region is relatively high. The presence of the first-conductivity-type impurity region having a lower impurity concentration than that of the first-emitter region relaxes the steepness of the impurity-concentration distribution around the first-conductivity-type emitter region.
The depletion layer in this portion is likely to expand, the electric field at the emitter-base junction becomes low, and a higher emitter-base junction breakdown voltage than before can be obtained.

Further, as the depletion layer easily extends as described above, the emitter-base junction capacitance decreases and the base resistance increases. Then, this can reduce the tunnel current.

Further, according to the semiconductor device of the second invention,
The side wall portion of the base lead electrode is formed by laminating a plurality of layers between the base lead electrode and the emitter lead electrode, and the innermost layer further includes a side wall film made of an insulator. Therefore, it has an advanced self-alignment structure and is suitable for easily making a fine transistor with good controllability, which improves the performance of the transistor.

According to the method of manufacturing the semiconductor device of the third invention, the oblique rotation ion implantation is performed from the hole for introducing the impurity,
Introducing the first conductivity type impurity so as to contact the outer periphery of the first conductivity type emitter region on the second conductivity type base region,
Since the step of forming the first-conductivity-type impurity region having a lower concentration than the impurity concentration of the first-conductivity-type emitter region is provided, a desired impurity can be self-aligned in the emitter-base junction by combining with a well-known manufacturing technique. The region can be formed, and the semiconductor device according to the first invention can be easily manufactured.

According to the method of manufacturing a semiconductor device of the fourth invention, the step of introducing the first conductivity type impurity into the second conductivity type base region using the first sidewall film as a mask, and the step of forming the first sidewall film And a step of forming a second sidewall film on the sidewall, and a step of further introducing a first conductivity type impurity into the second conductivity type base region using the first and second sidewall films as a mask. Therefore, a desired impurity region can be formed in the emitter-base junction in a self-aligned manner by combining with a well-known manufacturing technique, and the semiconductor device according to the second invention can be easily manufactured.

According to the method of manufacturing the semiconductor device of the fifth invention, the second sidewall containing the first conductivity type impurity is deposited on the sidewall of the first sidewall film.
Forming a sidewall film of the first conductive type impurity from the second sidewall film to the second conductive type base region by heat treatment, and heat treating the first conductive type emitter region and the first conductive type emitter region. And a step of forming a first conductivity type impurity region having an impurity concentration lower than that of the first conductivity type emitter region around the conductivity type emitter region. Moreover, a desired impurity region can be formed in the emitter-base junction, and the semiconductor device according to the second invention can be easily manufactured.

According to the method of manufacturing a semiconductor device of the sixth invention, the first conductivity type impurity is introduced by oblique rotation ion implantation using the sidewall film as a mask, and the first conductivity type emitter is formed on the second conductivity type base region. So that it touches the outer circumference of the area,
Since the step of forming the first-conductivity-type impurity region having a lower concentration than the impurity concentration of the first-conductivity-type emitter region is provided, a desired self-alignment of the emitter-base junction can be achieved by combining with a well-known manufacturing technique. The impurity region can be formed, and the semiconductor device according to the second invention can be easily manufactured.

According to the method of manufacturing a semiconductor device of the seventh invention, before the step of introducing the first conductivity type impurity into the region where the second conductivity type base region is to be formed by using the first sidewall film as a mask, Since at least one kind of ion of an inert ion, a halogen ion, and a group IV element ion is implanted to amorphize at least the region where the first conductivity type impurity region is to be formed, a comparison is made in the heat treatment step. It is possible to perform sufficient heat treatment under mild conditions.
It is possible to easily prevent the occurrence of defects such as lattice defects in the conductivity type impurity region.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a sectional view showing the element structure of a semiconductor device according to the first embodiment of the present invention.

In the figure, 1 is an n ⁺ silicon substrate or an n ⁺ diffusion layer, 2 is an n ⁺ silicon substrate or an n ⁺ diffusion layer 1
Is an n ^- epitaxial layer grown on. A collector region is formed by the n ⁺ silicon substrate or the n ⁺ diffusion layer 1 and the n ⁻ epitaxial layer 2.

Reference numeral 5 is a silicon oxide film. Reference numeral 3 is a p-type base region formed by introducing impurities from a hole formed in the silicon oxide film 5. 4 is a silicon oxide film 5
It is an n ⁺ -type emitter region formed by introducing impurities from the hole formed in the hole. Reference numeral 10 denotes an n-type impurity region formed by introducing n-type impurities by oblique rotation ion implantation. Basic Aikototen of the conventional apparatus of this embodiment and FIG. 6, the periphery of the n ⁺ -type emitter region 4, by introducing n-type impurity by oblique rotation ion implantation, from the n ⁺ -type emitter region 4 The point is that the n-type impurity region 10 having a low impurity concentration is formed.

FIG. 2 is a characteristic diagram showing the impurity concentration distribution in the depth direction in the II-II 'cross section of the semiconductor device. P indicates the phosphorus concentration introduced to form the n-type impurity concentration 10. B and Sb are the same as in FIG. 7. As is clear from FIG. 2, the n ⁺ type emitter region 4
Since the n-type impurity region 10 exists around the
The steepness of the impurity concentration distribution is alleviated.

Therefore, the depletion layer is more likely to expand than in the conventional semiconductor device, and the electric field at the emitter-base junction does not become large in the peripheral portion of the n ⁺ type emitter region 4 as in the conventional case.

FIG. 3 is a diagram showing a method of manufacturing the semiconductor device of FIG.

First, the n ⁻ epitaxial layer 2 having an impurity concentration of about 10 ¹⁶ cm ⁻³ is formed on the n ⁺ silicon substrate or the n ⁺ diffusion layer 1. An oxide film 13 is formed on the surface of the n ⁻ epitaxial layer to a thickness of 0.5 to 1 μm, for example (FIG. 3A).

Next, a hole 14 for introducing impurities for forming a base is formed by a photo-etching process. A p-type impurity such as boron is added by an ion implantation method, a solid phase diffusion method, or a vapor phase diffusion method, and the junction depth is 0.25, for example.
A p-type base region 3 of μm is formed (FIG. 3B).

Next, an oxide film 15 having a thickness of 0.6 μm is formed on the surface.
A hole 16 for introducing impurities for forming an emitter is formed. Using the holes 16 for introducing impurities, an n-type impurity is introduced by the oblique rotation ion implantation method, and a region which will become the n ⁺ -type emitter region 4 and p
The n-type impurity region 10 is formed on the outer periphery of the junction with the type base region 3.
To form. The n-type impurity region 10 can be formed, for example, by using phosphorus as an impurity and performing oblique rotary ion implantation with an acceleration energy of about 5 to 30 KeV. Further, from the holes 16 for introducing impurities,
Type impurities are added by an ion implantation method, a solid phase diffusion method or a vapor phase diffusion method to form an n ⁺ type emitter region 4 (FIG. 3).
(C)).

Finally, the base drawing hole 1 is formed in the oxide film 15.
7 is formed and a metal layer is formed on the surface of the oxide film 15,
The metal layer is patterned by the photoetching process to form the base metal electrode 7 and the emitter metal electrode 6, and the bipolar transistor which is one embodiment of the present invention is completed (FIG. 3D).

Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 4 is a diagram showing an embodiment in which the manufacturing method of the present invention is applied to the manufacturing process of the semiconductor device shown in NTT Research Practical Report Vol. 36 No. 4 (1987).

First, an n ^- epitaxial layer 2 having an impurity concentration of about 10 ¹⁶ cm ^-3 is formed on the n ⁺ silicon substrate or the n ⁺ diffusion layer 1, and silicon is formed on the surface of the n ^- epitaxial layer 2 by a thermal oxidation method or the like. The oxide film 21 is formed. A p ⁺ type polysilicon film 2 is formed by forming a nitride film 22 on the silicon oxide film 21 and further adding boron on the nitride film 22.
3 is formed. A portion of the p ⁺ type polysilicon film 23 corresponding to the emitter-base region is etched by using a lithography technique (FIG. 4A).

Next, the p ⁺ type polysilicon film 23 is selectively oxidized. At this time, since the n ⁻ epitaxial layer 2 on which the emitter and the base will be formed later is covered with the nitride film 22, it is not oxidized. Next, p which will become the base electrode in the future
^The nitride film 22 is side-etched to the bottom of the ⁺ -type polysilicon film 23. Further, the silicon oxide film 21 is replaced with the nitride film 2
It is removed in the same range as 2 (FIG. 4B).

In order to fill the space under the p ⁺ type polysilicon film 23 formed by removing the nitride film 22 and the silicon oxide film 21, polysilicon doped with boron is deposited again. Next, the p ⁺ -type polysilicon film 23 is connected to the n ⁻ epitaxial layer 2 by removing the deposited polysilicon except the one filling the space portion (FIG. 4C).

Next, a thermal oxide film is formed on the exposed surface of the n ^- epitaxial layer 2 and the side surface of the p ⁺ type polysilicon filling the space. Ion implantation is performed through this oxide film to form the intrinsic base layer 24. Next, a polysilicon film 25 is deposited on the oxide film, and then directional etching is performed by reactive ion etching to form the impurity introducing hole 16. Here, phosphorus (P) is introduced through the impurity introduction hole 16 at an acceleration energy of about 5 to 30 KeV by the oblique rotation ion implantation method to form the n-type impurity region 10 (FIG. 4D).

Thereafter, polysilicon 26 is deposited again, and n ⁺ type emitter region 4 is formed by diffusion from polysilicon 26 into which arsenic (As) has been ion-implanted. Then, an insulating film is deposited, contact holes are opened, and aluminum wiring is provided to complete the device (FIG. 4E).

Next, a third embodiment will be shown. FIG. 5 is a diagram showing a manufacturing method for simultaneously forming a high breakdown voltage bipolar transistor according to the present invention and a conventional bipolar transistor on the same substrate.

Similar to the conventional integrated circuit forming method using bipolar transistors, an n ⁺ diffusion layer 1, an n ^- epitaxial layer 2 and an element isolation p diffusion layer 34 are formed on a p ^- substrate 33.
To form.

Then, FIG. 3A and FIG.
Similar to the step described in (b), the p-type base diffusion region 3 is formed, the insulating film 35 such as an oxide film, and the impurity introduction hole 1 are formed.
6, n ⁺ type emitter region 4 is formed.

Next, a film 36 such as a resist is formed as an ion implantation mask for covering the n ⁺ type emitter region 4 of the normal bipolar transistor 32, and the n-type impurity is removed from the high breakdown voltage bipolar transistor 31 by the oblique rotation ion implantation method. Is introduced around the n ⁺ type emitter region 4 to form an n type impurity region 10 (FIG. 5A).

Next, a hole 17 for drawing out the base electrode and a hole 37 for drawing out the collector electrode are formed, and thereafter, the emitter metal electrode 6, the base metal electrode 7, and the collector metal electrode 3 are formed.
8 is formed (FIG. 5B).

By selectively forming the n-type impurity region 10 in the bipolar transistor on the same substrate as described above, a bipolar transistor having a high breakdown voltage and a bipolar transistor having a low base resistance can be simultaneously formed.

For example, high breakdown voltage bipolar transistor 31
Is applied to the BICMOS circuit, and the bipolar transistor 32 having a low base resistance is applied to the ECL circuit, whereby a high-performance BICMOS integrated circuit can be realized.

Next, FIG. 8 to FIG. 14 for the fourth embodiment.
Will be explained.

FIG. 8 is a sectional view showing the element structure of the semiconductor device according to the fourth embodiment of the present invention.

In FIG. 8, the same symbols as those in FIG.
57a denotes an oxide film which is a first side wall film, 57b denotes an oxide film which is a first side wall film,
Reference numeral 60 denotes an n-type impurity region which is a first conductivity type impurity region.

The basic difference between this embodiment and the conventional semiconductor device shown in FIG. 20 is that the semiconductor device is surrounded by the n ⁺ -type emitter region 59.
The point is that an n-type impurity is introduced to form an n-type impurity region 60 having an impurity concentration lower than that of the n ⁺ -type emitter region 59.

FIG. 9 is a characteristic diagram showing the impurity concentration distribution in the depth direction in the IV-IV 'cross section of the semiconductor device. A curve P shown in the drawing shows the phosphorus concentration introduced for forming the n-type impurity concentration 60. Curve B, broken line S
About b, it is the same as that of FIG. As is clear from FIG. 9, since the n-type impurity region 60 exists around the n ⁺ -type emitter region 59, the steepness of the impurity concentration distribution is alleviated.

Therefore, the depletion layer is more likely to expand than in the conventional semiconductor device, and the electric field at the emitter-base junction does not become large in the peripheral portion of the n ⁺ type emitter region 59 as in the conventional case.

10 to 15 are views showing a method of manufacturing the semiconductor device shown in FIG.

First, an n ^- epitaxial layer 52 having an impurity concentration of about 10 ¹⁶ cm ^-3 is formed on the n ⁺ silicon substrate or the n ⁺ diffusion layer 1. Next, an oxide film is separated (not shown) to determine an element portion forming an npn-type bipolar transistor. Next, a polysilicon 53 is deposited on the n ⁻ epitaxial layer 52, for example, to a thickness of 50 nm, and boron fluoride ions (BF ²⁺ ) are deposited in the polysilicon.
Is implanted at 4 × 10 ¹⁵ cm ⁻³ with an acceleration energy of 40 keV (FIG. 10).

Next, the oxide film 54 is deposited at a deposition temperature of 450.degree.
Is deposited to 400 nm. Then, by a photoetching process, the oxide film 54 in the portion where the intrinsic base region is to be formed and the polysilicon 53 under the oxide film 54 are sequentially etched and opened to form an impurity introduction hole. P-type impurities by ion implantation method, solid phase diffusion method or vapor phase diffusion method,
For example, boron is added to form the p-type base region 56 (FIG. 11).

Next, after depositing an oxide film to a thickness of 200 nm, the oxide film is anisotropically etched to form a sidewall film 57a which is a first sidewall film on the sidewall of the impurity introducing hole. And
Using the oxide film 54 and the sidewall film 57a as a mask, for example, phosphorus ions (P ⁺ ) which are n-type impurities are ion-implanted at an acceleration energy of about 5 to 30 keV (FIG. 12).

Next, after depositing an oxide film with a thickness of 200 nm, the oxide film is anisotropically etched to form a sidewall film 57b as a second sidewall film on the sidewall of the sidewall film 57a. Then, using the side wall films 57a and 57b as a mask, an n-type impurity such as arsenic ion (As ⁺ ) is added by an ion implantation method, a solid phase diffusion method or a vapor phase diffusion method (FIG. 13).

Next, polysilicon 58 is deposited to form an emitter extraction electrode, arsenic ions (As ⁺ ) are implanted to reduce the emitter resistance, and then patterning is performed. Finally, heat treatment is performed to form the external base region 55, the intrinsic base region 56, the emitter region 59, the low-concentration n-type impurity region 60, the base extraction electrode 53, and the emitter extraction electrode 58 (FIG. 1).
4).

Next, a fifth embodiment of the present invention will be described with reference to FIG.
Will be explained.

In the fourth embodiment, when phosphorus (P), which is an n-type impurity, is used in the ion implantation method to form the low-concentration n-type impurity region 60, the dose of phosphorus (P) is increased. Since the amount is 5 × 10 ¹⁴ cm ⁻² or less, the n-type impurity region 60 does not become amorphous, and when heat treatment is performed under the same conditions as in the past, lattice defects and the like are formed in the n-type impurity region 60, and Working as a recombination center,
There is concern about leakage current.

Therefore, after the step of forming the sidewall film 57a of the fourth embodiment and before the implantation of phosphorus ions (P ⁺ ), as shown in FIG.
After implanting 10 ¹⁴ cm ^-2 and making it amorphous, phosphorus ions (P ⁺ ) are implanted. After that, the above-mentioned concern can be solved by manufacturing in the same manufacturing process as the fourth embodiment.

Next, FIG. 16 shows the sixth embodiment of the present invention.
Will be explained.

In the fourth embodiment, an example in which the ion implantation method is used as the means for forming the low-concentration n-type impurity region 60 has been described, but a solid phase diffusion method may be used. After the step of forming the first side wall film 57a of the example, as shown in FIG. 16, a PSG (Posphorus Silicat) which is an oxide film containing phosphorus (P) as an n-type impurity.
e Glass) 61 is deposited by the CVD method. Next, P is formed on the side wall of the first side wall film 57a by a full-etchback method.
With SG left, a second sidewall film corresponding to the sidewall film 57b of FIG. 8 is formed. Hereinafter, it is manufactured by the same manufacturing process as the fourth embodiment. An n-type impurity region corresponding to the n-type impurity region 60 in the fourth embodiment is formed by diffusing phosphorus (P) in the second sidewall film made of PSG into the silicon substrate during heat treatment. Therefore, the content of phosphorus (P) in PSG and the condition of heat treatment must be set so that the impurity concentration of the n-type impurity region is lower than the impurity concentration of the emitter region.

Next, FIG. 17 shows the seventh embodiment of the present invention.
Will be explained.

In the sixth embodiment, the solid-phase diffusion method from PSG formed by the CVD method is used as the means for forming the low-concentration n-type impurity region 60, but the first embodiment of the fourth embodiment is used. After the step of forming the side wall film 57a, as shown in FIG.
The second sidewall film 62 may be left on the sidewall of the first sidewall film 57a by etching back after coating by (Spin On Glass) method and then baking. Below, the fourth
It is manufactured by the same manufacturing process as that of the embodiment. An n-type impurity region corresponding to the n-type impurity region 60 in the fourth embodiment is formed by diffusing phosphorus (P) in the second sidewall film 62 made of a phosphorus film into the silicon substrate during heat treatment. Therefore, the phosphorus (P) content in the phosphorus film and the heat treatment conditions must be set so that the impurity concentration in the n-type impurity region is lower than the impurity concentration in the emitter region.

FIG. 18 shows the eighth embodiment of the present invention.
Will be explained.

Although the insulating film is used as the second side wall film in the fourth to seventh examples, the second side wall film may not be the insulating film, and a conductor film such as a polysilicon film may be used. After the step of forming the first sidewall film 57a of the fourth embodiment, as shown in FIG. 18, a polysilicon film containing phosphorus (P) as an n-type impurity is deposited on the entire surface. The second side wall film 63 may be left on the side wall of the first side wall film 57a by the etch back method. Hereinafter, it is manufactured by the same manufacturing process as the fourth embodiment. The n-type impurity region corresponding to the n-type impurity region 60 in the fourth embodiment is formed by diffusing phosphorus (P) in the second sidewall film 63 made of a polysilicon film into the silicon substrate during heat treatment. Therefore, the phosphorus (P) content in the polysilicon film and the heat treatment conditions must be set so that the impurity concentration in the n-type impurity region is lower than the impurity concentration in the emitter region.

Next, a ninth embodiment of the present invention will be described with reference to FIG.
Will be explained.

In the fourth embodiment, the low concentration n-type impurity region 6 is used.
Although an example of using a normal ion implantation method has been shown as a means for forming 0, an oblique rotation ion implantation method may be used, and the step of forming the first sidewall film 57a of the fourth embodiment is performed. After that, as shown in FIG. 19, phosphorus ions (P ⁺ ) are implanted by the oblique rotation ion implantation method using the first sidewall film 57a as a mask. Without forming the side wall film 57b, n-type impurities are introduced by using the side wall film 57a as a mask by a usual method, and thereafter, the same manufacturing process as that of the fourth embodiment is performed. As a result, phosphorus ions (P ⁺ ) are implanted into the silicon substrate below the first side wall film 57a, and an n-type impurity region corresponding to the n-type impurity region 60 in the fourth embodiment can be formed during the heat treatment. it can. At this time, the ion implantation for amorphization in the fifth embodiment may be performed by using the oblique rotation ion implantation method, and the same effect as that of the fifth embodiment is obtained.

In each of the fourth to ninth embodiments, the second method is used as the n-type impurity introduction method for forming the emitter region.
After forming the side wall film of, the method of introducing impurities by the ion implantation method using the first and second side wall films as a mask has been described. For example, a polysilicon film containing arsenic is deposited as an emitter extraction electrode. Alternatively, the emitter region may be formed by diffusing arsenic into the silicon substrate during the heat treatment, and the same effects as those of the above-described respective embodiments are obtained.

Further, in each of the above-mentioned embodiments, the npn-type bipolar transistor has been described, but the same can be applied to a pnp-type transistor by exchanging the n-type and the p-type. Produce an effect.

[0078]

As described above, according to the semiconductor device of the first aspect of the present invention, the impurity region of the same conductivity type as the emitter region and having a lower concentration than the emitter region is formed on the outer periphery of the first conductivity type emitter region. With the provision of the same base concentration, the steepness of the impurity concentration distribution in the outer periphery of the first conductivity type emitter region becomes small and the electric field of the emitter-base junction is relaxed to improve the emitter-base junction breakdown voltage. You can Further, there is an effect that a semiconductor device capable of reducing the tunnel current can be obtained by increasing the depletion layer around the emitter-base junction.

Further, according to the semiconductor device of the second aspect of the present invention, in the side wall portion of the base lead-out electrode, a plurality of layers are formed between the base lead-out electrode and the emitter lead-out electrode, Since the innermost layer further includes a sidewall film made of an insulator and has an advanced self-aligned structure, it becomes a structure suitable for easily making a fine transistor with good controllability, There is an effect that the performance of the transistor can be improved.

According to the semiconductor device manufacturing method of the third aspect of the present invention, the first conductivity type impurity is introduced by oblique rotary ion implantation from the impurity introduction hole, and the second conductivity type base region is formed. Since the step of forming the first-conductivity-type impurity region having a lower concentration than the impurity concentration of the first-conductivity-type emitter region is provided so as to be in contact with the outer periphery of the first-conductivity-type emitter region, by combining with a well-known manufacturing technique, A desired impurity region can be formed in the emitter-base junction in a self-aligned manner, and the semiconductor device according to the first aspect can be easily manufactured.

According to the method for manufacturing a semiconductor device of the invention according to claim 4, the step of introducing the first conductivity type impurity into the second conductivity type base region using the first sidewall film as a mask,
Forming a second side wall film on the side wall of the first side wall film; and introducing a first conductivity type impurity into the second conductivity type base region using the first and second side wall films as a mask. And a desired impurity region can be formed in the emitter-base junction in a self-aligned manner by combining with a well-known manufacturing technique, and the semiconductor device according to claim 2 can be easily manufactured. There is an effect that it becomes possible to do.

According to the method of manufacturing a semiconductor device of the fifth aspect of the present invention, the step of forming the second sidewall film containing the first conductivity type impurity on the sidewall of the first sidewall film and the heat treatment are performed. A first conductive type impurity is introduced into the second conductive type base region from a second sidewall film, and the first conductive type impurity is formed around the first conductive type emitter region and the first conductive type emitter region by the heat treatment. And a step of forming a first conductivity type impurity region having an impurity concentration lower than that of the emitter region. Therefore, by combining with a well-known manufacturing technique, a desired impurity region can be self-aligned at the emitter-base junction. The semiconductor device can be formed and the semiconductor device according to the second aspect can be easily manufactured.

Further, according to the method of manufacturing a semiconductor device of the present invention, the first conductivity type impurity is introduced by oblique rotation ion implantation using the sidewall film as a mask, and the first conductivity type impurity is formed on the second conductivity type base region. Since the step of forming the first-conductivity-type impurity region having a lower concentration than the impurity concentration of the first-conductivity-type emitter region is provided so as to be in contact with the outer periphery of the first-conductivity-type emitter region, by combining with a well-known manufacturing technique, A desired impurity region can be formed in the emitter-base junction in a self-aligning manner, and the semiconductor device according to the second aspect can be easily manufactured.

Further, according to the method of manufacturing a semiconductor device of the present invention, before the step of introducing the first conductivity type impurity into the second conductivity type base region using the first sidewall film as a mask, Since at least one kind of ions among active ions, halogen ions and group IV element ions is implanted to amorphize at least the region where the first conductivity type impurity region is to be formed, in the heat treatment process, Sufficient heat treatment can be performed under mild conditions.
It is possible to easily prevent the occurrence of defects such as lattice defects in the conductivity type impurity region, and it is possible to easily manufacture the semiconductor device according to claim 1 or 2.

[Brief description of drawings]

FIG. 1 is a sectional view showing an element structure of a semiconductor device according to a first embodiment of the present invention.

2 is a characteristic diagram showing an impurity concentration distribution in a depth direction in a II-II ′ cross section of the semiconductor device of FIG.

FIG. 3 is a process sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor device in the manufacturing process according to the second embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device in the manufacturing process according to the third exemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view showing the structure of a conventional semiconductor device.

FIG. 7 is a characteristic diagram showing an impurity concentration distribution in the depth direction in the II ′ cross section of the semiconductor device of FIG.

FIG. 8 is a sectional view showing an element structure of a semiconductor device which is a fourth embodiment of the present invention.

9 is a characteristic diagram showing the impurity concentration distribution in the depth direction in the IV-IV ′ cross section of the semiconductor device of FIG.

FIG. 10 is a process sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 11 is a process sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 12 is a process sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 13 is a process sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 14 is a process sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 15 is a sectional view of a semiconductor device manufacturing process according to the fifth embodiment of the present invention.

FIG. 16 is a sectional view of a semiconductor device in a manufacturing process, which is a sixth embodiment of the present invention.

FIG. 17 is a sectional view of a semiconductor device in a manufacturing process, which is a seventh embodiment of the present invention.

FIG. 18 is a manufacturing step sectional view of a semiconductor device according to an eighth embodiment of the present invention.

FIG. 19 is a manufacturing step sectional view of a semiconductor device which is a ninth embodiment of the present invention.

FIG. 20 is a cross-sectional view showing the structure of a conventional semiconductor device.

21 is a characteristic diagram showing an impurity concentration distribution in the depth direction in a III-III ′ cross section of the semiconductor device of FIG. 20.

[Explanation of symbols]

DESCRIPTION ^OF SYMBOLS 1 n ⁺ silicon substrate or n ⁺ diffusion layer 2 n ^- epitaxial layer 3 p type base region 4 n ⁺ type emitter region 5 silicon oxide film 6 emitter metal electrode 7 base metal electrode 10 n type impurity region 51 n ⁺ silicon substrate or n ⁺ Diffusion layer 52 n ^- Epitaxial layer 53 p ⁺ Polysilicon film 54 Oxide film 55 External base region 56 Intrinsic base regions 57a, 57b Sidewall film 58 n ⁺ Polysilicon film 59 n ⁺ type emitter region 60 n type impurity region

Claims (7)

[Claims] 1. A first conductivity type collector region, a second conductivity type base region formed on the first conductivity type collector region, and a first conductivity type emitter formed on the second conductivity type base region. The first conductive type emitter region and the first conductive type emitter region, and the first conductive type emitter region is formed on the second conductive type base region.
A first conductivity type impurity region having a concentration lower than that of the conductivity type emitter region; 2. A semiconductor device formed on a semiconductor substrate, wherein an emitter lead electrode formed on the first conductivity type emitter region and a base lead formed on the second conductivity type base region. Electrode, and a side wall film of the base extraction electrode, a side wall film formed by laminating a plurality of layers between the base extraction electrode and the emitter extraction electrode, the innermost layer being made of an insulator, The semiconductor device according to claim 1, further comprising: 3. A step of forming a first conductive type collector region, a step of forming a second conductive type base region on the first conductive type collector region, and an insulating film on the second conductive type base region. A step of forming, a step of forming a hole for introducing impurities in the insulating film, and introducing a first conductivity type impurity from the hole for introducing impurities,
And a step of forming a first conductivity type emitter region on the second conductivity type base region, wherein oblique rotation ion implantation is performed from the impurity introduction hole.
A first conductivity type impurity having a concentration lower than the impurity concentration of the first conductivity type emitter region is introduced so as to contact the outer periphery of the first conductivity type emitter region on the second conductivity type base region. A method of manufacturing a semiconductor device, comprising the step of forming an impurity region. 4. A first conductivity type collector region formed on a semiconductor substrate, a second conductivity type base region formed on the first conductivity type collector region, and a second conductivity type base region formed on the second conductivity type base region. A first conductive type emitter region, and
An electrode for extracting an emitter formed on a conductive type emitter region, an electrode for extracting a base formed on the second conductive type base region, and an electrode for extracting a base and an emitter on a side wall of the electrode for extracting a base. A method of manufacturing a semiconductor device, comprising: a side wall film formed by stacking a plurality of layers between the side wall film and an extraction electrode; wherein the side wall film is made of an insulator formed on a side wall of the base extraction electrode. A first side wall film and a second side wall film formed on the side wall of the first side wall film, the step of forming the first side wall film on the side wall of the base extraction electrode; Introducing a first conductivity type impurity into the second conductivity type base region using the first sidewall film as a mask; forming the second sidewall film on the sidewall of the first sidewall film; And the Further introducing a first conductivity type impurity into the second conductivity type base region by using the sidewall film as a mask, and the first conductivity type emitter region by the first conductivity type impurity introduced into the second conductivity type base region. And a step of forming a first conductivity type impurity region having a lower impurity concentration than that of the first conductivity type emitter region around the first conductivity type emitter region, and a method of manufacturing a semiconductor device. 5. A first conductivity type collector region formed on a semiconductor substrate, a second conductivity type base region formed on the first conductivity type collector region, and a second conductivity type base region formed on the second conductivity type base region. A first conductive type emitter region, and
An electrode for extracting an emitter formed on a conductive type emitter region, an electrode for extracting a base formed on the second conductive type base region, and an electrode for extracting a base and an emitter on a side wall of the electrode for extracting a base. A method of manufacturing a semiconductor device, comprising: a side wall film formed by stacking a plurality of layers between the side wall film and an extraction electrode; wherein the side wall film is made of an insulator formed on a side wall of the base extraction electrode. 1 side wall film and a second side wall film containing a first conductivity type impurity formed on the side wall of the first side wall film, and the first side wall film is formed on the side wall of the base extraction electrode. A step of forming, a step of forming the second sidewall film containing a first conductivity type impurity on a sidewall of the first sidewall film, and a step of forming the second conductivity type using the first and second sidewall films as a mask Base area A step of introducing a first conductivity type impurity into the second conductive film, and a step of introducing a first conductivity type impurity from the second sidewall film into the second conductivity type base region by heat treatment, Forming a first conductivity type impurity region having a lower impurity concentration than that of the first conductivity type emitter region around the first conductivity type emitter region. 6. A first conductivity type collector region formed on a semiconductor substrate, a second conductivity type base region formed on the first conductivity type collector region, and a second conductivity type base region formed on the second conductivity type base region. A first conductive type emitter region, and
An electrode for extracting an emitter formed on a conductive type emitter region, an electrode for extracting a base formed on the second conductive type base region, and an electrode for extracting a base and an emitter on a side wall of the electrode for extracting a base. A method of manufacturing a semiconductor device, comprising: a sidewall film formed between a lead electrode and a lead electrode; wherein the sidewall film is used as a mask to introduce impurities of a first conductivity type by oblique rotation ion implantation, The semiconductor is characterized in that a step of forming a first-conductivity-type impurity region having a concentration lower than that of the first-conductivity-type emitter region is provided so as to contact the outer periphery of the first-conductivity-type emitter region on the region. Device manufacturing method. 7. Before the step of introducing the first conductivity type impurity into the second conductivity type base region by using the first sidewall film as a mask, at least one of an inert ion, a halogen ion and a group IV element ion is formed. 7. The method for manufacturing a semiconductor device according to claim 3, wherein at least a region where the first conductivity type impurity region is to be formed is made amorphous by implanting ions of a type.