JP2010192710A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of providing an excellent current amplification factor; and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device includes: a semiconductor substrate; a first conductivity type first conductive layer 12 arranged on the semiconductor substrate and formed of silicon carbide; a first conductivity type second conductive layer 14 arranged on the first conductive layer 12, having impurity concentration lower than that of the first conductive layer 12, and formed of silicon carbide; a second conductivity type base region 16 arranged in the second conductive layer 14 and having a conductivity type different from the first conductivity type; and a first conductivity type emitter region 18 arranged in the base region 16, having a front surface flush with the front surface of the base region 16, and having impurity concentration of 5&times;10<SP>17</SP>to 5&times;10<SP>19</SP>cm<SP>-3</SP>. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. In particular, the present invention relates to a semiconductor device as a planar bipolar transistor using a silicon carbide semiconductor and a method for manufacturing the semiconductor device.

  Wide band gap compound semiconductors such as silicon carbide (hereinafter sometimes referred to as “SiC”) operate in harsh environments such as high breakdown voltage, high output, and high temperature compared to compound semiconductors such as Si semiconductor and GaAs. It is attracting attention as an electronic device material. In addition, SiC can be easily made p-type by adding impurities as compared with nitride compound semiconductors such as gallium nitride (GaN). Therefore, it can be applied to a bipolar transistor that requires a p-type semiconductor layer and an n-type semiconductor layer.

Conventionally, an n ⁺ type SiC substrate, an n ⁻ type SiC epitaxial region formed on the n ⁺ type SiC substrate, a p type base region formed in the n ⁻ type SiC epitaxial region, and a p type base region An n ⁺ -type emitter region formed and a p ⁺ -type base contact region formed in the p-type base region and adjacent to the n ⁺ -type emitter region, and no depletion layer is formed in the p-type base region A bipolar transistor is known in which the free carrier concentration in the p-type base region is smaller than the space charge concentration in the depletion layer when the depletion layer is formed in the p-type base region (for example, Patent Document 1).

  The bipolar transistor described in Patent Document 1 can exhibit a high current gain by having the above-described configuration.

JP 2004-247545 A

  For the performance of the bipolar transistor, the current amplification factor, which is the ratio of the collector current to the base current, is important. The current amplification factor is determined mainly based on the emitter injection efficiency. The emitter injection efficiency is determined based on the base hole current and the emitter electron current, and the base hole current is determined based on the emitter impurity concentration and the emitter depth. Further, the emitter electron current is determined based on the base impurity concentration and the base width. However, the bipolar transistor described in Patent Document 1 does not optimize the impurity concentration of the emitter region and the impurity concentration of the base region, and there is a limit to improving the performance of the bipolar transistor.

  Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can obtain a good current gain.

In order to achieve the above object, the present invention provides a semiconductor substrate, a first conductive layer of a first conductivity type provided on the semiconductor substrate and formed of silicon carbide, provided on the first conductive layer, A first conductive type second conductive layer having an impurity concentration lower than that of the conductive layer and made of silicon carbide; and a second conductive layer provided in the second conductive layer and having a conductivity type different from the first conductive type. A second conductivity type base region, a first region provided in the base region, having a surface flush with the surface of the base region and having an impurity concentration of 5 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ or less A semiconductor device comprising an emitter region of one conductivity type is provided.

In the semiconductor device, the base region preferably has an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less.

  The semiconductor device further includes an emitter electrode provided on a part of the surface of the emitter region, and the distance from the end of the emitter electrode to the boundary between the base region and the emitter region is less than that of minority carriers in the emitter region. It can also be longer than the average diffusion distance.

  In the semiconductor device, the surface concentration of the emitter region in contact with the base region can be lower than the concentration of the emitter region in contact with the intrinsic base region formed between the base region and the emitter region.

In order to achieve the above object, the present invention provides a step of preparing a semiconductor substrate, a step of forming a first conductive layer of a first conductivity type formed of silicon carbide on the semiconductor substrate, and a first conductive layer. Forming a first conductive type second conductive layer having an impurity concentration lower than that of the first conductive layer and formed of silicon carbide on the first conductive layer; A step of forming a base region by ion-implanting impurity atoms of a second conductivity type different from the first conductivity type while changing energy stepwise, and the surface is flush with the surface of the base region In addition, the impurity concentration of 5 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ or less is obtained by ion-implanting impurity ions of the first conductivity type while gradually changing the acceleration energy to a partial region of the base region. Forming an emitter region having And a method of manufacturing a semiconductor device comprising the steps.

  According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device that can obtain a good current gain.

It is sectional drawing of the semiconductor device which concerns on embodiment of this invention. FIG. 6 is a distribution diagram of current amplification factors when the emitter concentration and the base concentration are variously changed in the semiconductor device according to the present embodiment. It is a figure which shows the flow of the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows the flow of the manufacturing process of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on an Example. FIG. 5A is a distribution diagram of impurity concentration in the X1-X2 direction in FIG. 4, and FIG. 5B is a distribution diagram of impurity concentration in the Y1-Y2 direction in FIG.

[Embodiment]
(Configuration of semiconductor device)
FIG. 1 shows an outline of a cross section of a semiconductor device according to an embodiment of the present invention.

  As an example, the semiconductor device 1 according to the present embodiment is a planar bipolar transistor formed mainly from a SiC-based semiconductor as a wide gap semiconductor of group IV-IV. Specifically, the semiconductor device 1 includes a SiC substrate 10 as a semiconductor substrate, a first conductive layer 12 of the first conductivity type provided on the SiC substrate 10 and formed of SiC, and the first conductive layer 12. A first conductive type second conductive layer 14 made of SiC having an impurity concentration lower than the impurity concentration of the first conductive layer 12, and a second conductive layer 14 provided in the first conductive type A second conductivity type base region 16 of a different conductivity type, and a first conductivity type emitter region 18 provided in the base region 16 and having a surface flush with the surface of the base region 16. Further, the semiconductor device 1 is in contact with the base electrode 20 provided on a part of the surface of the base region 16, the emitter electrode 2 provided on a part of the surface of the emitter region 18, and the first conductive layer 12 of the SiC substrate 10. And a back surface electrode 25 provided on the surface opposite to the facing side (hereinafter also referred to as “the back surface of the SiC substrate 10”).

  The SiC substrate 10 can be a poly-type SiC substrate such as a 3C type, 2H type, 4H type, or 6H type. For example, as the SiC substrate 10, a 4H-SiC {0001} off substrate, a 6H-SiC {0001} off substrate, or the like can be used. The off-angle of SiC substrate 10 is preferably selected from a range of 3 degrees to 10 degrees. The numbers of the 3C type, 2H type, 4H type, and 6H type indicate the repetition period in the c-axis direction, C indicates a cubic crystal, and H indicates a hexagonal crystal.

The first conductive layer 12 is an n ⁺ -type SiC layer formed of SiC and added with an n-type impurity as a first conductivity type. As the n-type impurity, phosphorus (P), nitrogen (N), arsenic (As), or the like can be used. The second conductive layer 14 is an n-type SiC layer or an n ⁻ -type SiC layer formed of SiC and doped with an n-type impurity. The impurity concentration of the second conductive layer 14 is at least lower than the impurity concentration of the first conductive layer 12. The second conductive layer 14 has a resistivity higher than that of the first conductive layer 12. Therefore, the second conductive layer 14 functions as a high resistance layer with respect to the first conductive layer 12. The first conductive layer 12 and the second conductive layer 14 are formed by chemical vapor deposition (Chemical Vapor Deposition method: CVD method), molecular beam epitaxy method (Molecular Beam Epitaxy method: MBE method), solution growth method, etc., respectively. It can be formed using a crystal growth technique. Therefore, each of first conductive layer 12 and second conductive layer 14 is formed with a polytype corresponding to the polytype of SiC substrate 10.

  The base region 16 is formed of SiC to which a p-type impurity as the second conductivity type is added. Aluminum (Al) or the like can be used as the p-type impurity. The emitter region 18 is made of SiC to which an n-type impurity is added. Since the emitter region 18 is formed in the base region 16, the emitter region 18 has an area smaller than the area of the base region 16 in a top view. Further, the base electrode 20 is provided in ohmic contact with a partial region of the surface of the base region 16. Similarly, the emitter electrode 22 is provided in ohmic contact with a partial region of the surface of the emitter region 18.

  Each of the base electrode 20 and the emitter electrode 22 can be composed of a single layer structure or a laminated structure of a metal material. For example, the base electrode 20 and the emitter electrode 22 can each be formed having a two-layer structure of a nickel layer and an aluminum layer. Each of the base electrode 20 and the emitter electrode 22 can also be formed with an n-layer structure (n is an integer of 3 or more).

  The emitter electrode 22 has a minority carrier in the emitter region 18 having a distance from the end 22a of the emitter electrode 22 to the boundary 17 between the base region 16 and the emitter region 18 (hereinafter simply referred to as “the distance”). It is formed so that the end 22a is disposed at a position on the surface of the emitter region 18 that is longer than the average diffusion distance of a certain hole. In this case, the inventor has a current amplification factor of 50 when the distance is 10 μm, a current amplification factor of 15 when the distance is 3 μm, and a current amplification factor when the distance is 2 μm. When the amplification factor was 10 and the distance was 1 μm, an experimental result was obtained that the current amplification factor was 5. Thereby, in this embodiment, for the purpose of improving the current amplification factor, as an example, the emitter electrode 22 is positioned at the surface position of the emitter region 18 where the distance between the end 22a and the boundary 17 is 2 μm or more. It is preferable to form. Note that the boundary 17 according to the present embodiment is a boundary located on the surface of the semiconductor device 1.

Here, in the present embodiment, the impurity concentration of the emitter region 18 is preferably 5 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ or less. This is based on the following knowledge obtained by the present inventors.

First, the emitter electron current density (J _n ) and the base hole current density (J _p ) of the bipolar transistor can be expressed by the following equations (1) and (2).

Where q is the amount of charge, ni is the intrinsic carrier concentration, D _p is the hole diffusion coefficient, D _n is the electron diffusion coefficient, V _BE is the forward voltage between the base and the emitter, k is the Boltzmann constant, and T is temperature, _{N a} is the acceptor concentration, _{N d} is the donor concentration, _{W E} is emitter width, _{W B} is base width. E _Ev is the conduction band energy level of the emitter in the emitter-base junction region, and E _Bv is the base conduction band energy level in the emitter-base junction region. Further, _EEc is the valence band energy level of the emitter in the emitter-base junction region, and _EBc is the valence band energy level of the base in the emitter-base junction region. The actual emitter current value is obtained by multiplying the emitter electron current density by the area of the emitter region, and the actual base current value is obtained by multiplying the base hole current density by the area of the base region.

  Here, the value of the collector current is substantially the same as the value of the emitter current when carrier recombination does not substantially occur in the base region. Therefore, the ratio between the emitter electron current density and the base hole current density is calculated as the current amplification factor. Therefore, as apparent from the above equations (1) and (2), the current amplification factor is determined by the impurity concentration in the emitter region, the impurity concentration in the base region, and the conduction band of the emitter and the conduction band of the base. , And the difference in the valence band energy between the emitter valence band and the base valence band.

  In general, the impurity concentration of the emitter region and the impurity concentration of the base region are set as high as possible in order to reduce the resistance of the emitter region and the base region and improve the characteristics of the bipolar transistor. In general, the current amplification factor is improved by setting the impurity concentration in the emitter region to be higher than the impurity concentration in the base region. However, the present inventors have found that in SiC, when impurity atoms are added to SiC to increase the impurity concentration of SiC, the energy levels of the conduction band and valence band of the emitter change due to the narrow band gap effect. We obtained the knowledge that the current gain decreased (that is, the band gap narrowed). Therefore, the present inventor measured changes in the current amplification factor of the bipolar transistor by changing the base concentration and the emitter concentration in various ways in the bipolar transistor as shown in FIG.

  FIG. 2 shows a current amplification factor distribution when the emitter concentration and the base concentration are variously changed in the semiconductor device according to the present embodiment.

Referring to FIG. 2, the present inventor has found that there is an optimum concentration range for the emitter concentration at which a good current amplification factor (for example, a current amplification factor of 1 or more) can be stably obtained. That is, the impurity concentration in the base region (base concentration in FIG. 2) is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less, and the impurity concentration in the emitter region (emitter concentration in FIG. 2) is 5 ×. The present inventor has found that the current amplification factor is a good value when the impurity concentration is 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ or less.

More specifically, referring to the above formula (1), when the donor concentration (N _d ) as the emitter concentration is high and the emitter width (W _E ) as the emitter depth is wide, the base hole current as the base current The density (J _p ) decreases. However, when _Nd is increased, the valence band energy level (E _Ev ) of the emitter is lowered, and the barrier of the emitter to holes is reduced, so that the effect of increasing J _p also occurs. Therefore, in order to reduce the J _p is required to widen the W _E to determine the N _d.

Similarly, referring to the above formula (2), when the acceptor concentration (N _a ), which is the base concentration, is low and the base width (W _B ) is narrow, the emitter electron current density (J _n ), which is the emitter current, increases. However, when the lower N _a, decreases the breakdown voltage is narrowed to W _B, there is a case where the operation of the semiconductor device 1 becomes difficult. Therefore, in order to increase the J _n is required to narrow the W _B to determine the N _a. Then, requires that the increase the current amplification factor _(J n / J _p), or increase the _{N d,} or _W or wider _E, or, or to lower the _{N a,} or to narrow the _{W B} but there is a case where the current amplification factor is not increased when a higher N _d.

In Figure 2, by setting the _{W E} 0.2 [mu] m, the _{W B} to 0.3 [mu] m, good current gain was examined emitter density obtained stably. In this case, either widen the W _E, or by narrowing the W _B, the current amplification factor is increased. Specifically, since _{W E} or _{W B} is the degree 5μm or less, the finding that the range of the emitter concentration is preferably 5 × ¹⁰ 17 ^{cm -3} to 5 × ¹⁰ 19 ^{cm -3} or less, the The inventor got. The semiconductor device 1 according to the embodiment of the present invention is based on such knowledge.

  In the present embodiment, the surface concentration of the emitter region 18 in contact with the base region 16 can be made lower than or comparable to the concentration of the emitter region 18 in contact with the intrinsic base region. Here, the surface concentration is a concentration in the vicinity of the surface of the emitter region 18, and is preferably a concentration inside the emitter region 18 of about 1 nm to 10 nm from the surface exposed to the outside. The intrinsic base region is the base region 16 immediately below the emitter region 18. Referring to FIG. 1, the intrinsic base region corresponds to, for example, a region substantially parallel to the surface of the semiconductor device 1 among the surfaces where the emitter region 18 and the base region 16 are in contact (for example, in FIG. 22 is a region where the base region 16 and the emitter region 18 are in contact with each other. The emitter region 18 in contact with the intrinsic base region is a junction surface region where the intrinsic base region and the emitter region 18 are joined.

  When the surface concentration of the emitter region 18 in contact with the base region 16 is made lower than or similar to the concentration of the emitter region 18 in contact with the intrinsic base region as in the present embodiment, the SiC substrate 10 is exposed from the surface side of the semiconductor device 1. Since the impurity concentration does not decrease toward the bottom of the semiconductor device 1, the band gap narrowing effect can be suppressed even when the semiconductor device 1 is manufactured by introducing impurities into the SiC substrate 10.

  The impurity concentration in the emitter region 18 can be changed from the front surface of the semiconductor device 1 toward the back electrode 25 side. For example, the impurity concentration can be gradually increased from the front surface side of the emitter region 18 toward the back electrode 25 side. In other words, the impurity concentration (hereinafter referred to as “surface concentration”) on the surface of the emitter region 18 is an interface between the base region 16 and the emitter region 18 and extends from the surface of the emitter region 18 in the depth direction of the semiconductor device 1. It can be made lower than the impurity concentration of the emitter region 18 in contact with the base region 16 (hereinafter referred to as “intrinsic base region”) that is farthest (that is, deepest) along the line.

(Semiconductor device manufacturing process)
3A and 3B show an example of the flow of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

First, an SiC substrate 10 having a predetermined polytype is prepared. Next, the n ⁺ -type first conductive layer 12 and the n-type second conductive layer 14 are grown in this order on the prepared SiC substrate 10. Thereby, the semiconductor laminated structure 1a as shown to (a) of FIG. 3A is obtained.

  Subsequently, as shown in FIG. 3A (b), a mask 30 having an opening 30a in a portion corresponding to the base region 16 to be formed is formed on the surface of the second conductive layer 14 of the semiconductor laminated structure 1a by a photolithography method. It forms using. Then, p-type impurity atoms are implanted from the opening 30a toward the surface of the second conductive layer 14 using an ion implantation method. As a result, as shown in FIG. 3A (b), the semiconductor stacked structure 1b in which the base region 16 as the p-type conductive region is formed in the second conductive layer 14 is obtained. Here, in the present embodiment, the ion implantation is performed by implanting p-type impurity atoms into a partial region of the second conductive layer 14 while changing the acceleration energy stepwise. Specifically, the acceleration energy is reduced stepwise (that is, the acceleration energy is changed in a stepwise reduction direction), and impurity atoms are implanted into the second conduction layer 14, whereby the second conduction layer 14. A base region 16 is formed therein.

  For example, ion implantation can be performed as follows. First, the first-stage ion implantation is performed with the first acceleration energy so that the impurity ions have the first dose amount. Next, second-stage ion implantation is performed so that the impurity ions have a second dose amount smaller than the first dose amount with a second acceleration energy smaller than the first acceleration energy. Then, the third-stage ion implantation is performed so that the impurity ions have a third dose amount smaller than the second dose amount with a third acceleration energy smaller than the second acceleration energy. The ion implantation is not limited to three stages, and can be performed in n stages (where n is an integer of 4 or more).

  Next, the mask 30 is removed and the semiconductor multilayer structure 1b is cleaned. 3B, a mask 31 having an opening 31a in a portion corresponding to the emitter region 18 to be formed on the surface of the second conductive layer 14 of the semiconductor multilayer structure 1b from which the mask 30 has been removed. Is formed using a photolithography method. Then, n-type impurity atoms are implanted from the opening 31a toward the surface of the base region 16 using an ion implantation method. Thus, as shown in FIG. 3B (a), the semiconductor laminated structure in which the emitter region 18 as the n-type conductive region is formed in the second conductive layer 14 and in a part of the base region 16. A body 1c is obtained. Here, the ion implantation method used for forming the emitter region 18 is also performed by changing the acceleration energy stepwise, as in the case of forming the base region 16. Specifically, the emitter region 18 is also formed by stepping down the acceleration energy and implanting n-type impurity atoms into the base region 16.

  Subsequently, the mask 31 is removed and the semiconductor multilayer structure 1c is cleaned. Then, the base electrode 20 is formed on a part of the surface of the base region 16 and the emitter electrode is formed on a part of the surface of the emitter region 18 by using a photolithography method, a vacuum deposition method (or a film forming technique such as a sputtering method) or the like. 22. Further, back electrode 25 is formed on the back surface of SiC substrate 10. Thereby, the semiconductor device 1 as shown in FIG. 3B (b) is obtained.

  After the base region 16 and the emitter region 18 are formed using the ion implantation method, the semiconductor laminated structure 1c from which the mask 31 has been removed is subjected to an annealing process in a predetermined atmosphere at a predetermined temperature for a predetermined time. It can also be applied. Further, a predetermined heat treatment is performed so as to make ohmic contact between the base electrode 20 and the base region 16, between the emitter electrode 22 and the emitter region 18, and between the back electrode 25 and the back surface of the SiC substrate 10. It can also be applied.

(Effect of embodiment)
Semiconductor device 1 according to the present embodiment has base region 16 and emitter region 18 formed by ion implantation in SiC substrate 10, and the impurity concentration of emitter region 18 is 5 × 10 ¹⁷ cm ⁻³ or more. Since it is controlled to × 10 ¹⁹ cm ⁻³ or less, the influence of the narrow band gap effect of SiC can be reduced, and a good current gain can be exhibited.

  Further, according to the method for manufacturing the semiconductor device 1 according to the present embodiment, the base region 16 and the emitter region 18 are formed by the ion implantation method, so that the surface of the semiconductor device 1 is substantially flat (that is, uneven). Less surface). Thereby, even when electrode wiring is provided on the surface of the semiconductor device 1, disconnection of the wiring can be reduced, so that the manufacturing yield of the semiconductor device 1 can be greatly improved. Also, for example, when the base region and the emitter region are continuously grown on the SiC substrate 10 and the emitter electrode and the base electrode are respectively formed in the removed region after etching away a part of the emitter region and the base region. In comparison, since the manufacturing method of the semiconductor device 1 according to the present embodiment does not require an etching process, the manufacturing process of the semiconductor device 1 can be simplified and the yield of the semiconductor device 1 can be improved.

  Hereinafter, semiconductor devices according to embodiments of the present invention will be described.

  FIG. 4 shows an outline of a cross section of the semiconductor device according to the example.

  The semiconductor device 2 according to the example has substantially the same configuration as the semiconductor device 1 according to the embodiment shown in FIG. Therefore, detailed description is omitted except for the differences.

The semiconductor device 2 includes a SiC substrate 10 of 4 degrees off, the ^{n +} -type SiC conductive layer 11 provided on the SiC substrate 10, provided on the ^{n +} -type SiC conductive layer 11, n-type having a thickness of 5μm SiC conductive layer 13, p-type base region 16 having a depth of 3 μm provided in n-type SiC conductive layer 13, and provided in base region 16, the surface being flush with the surface of base region 16 And an n-type emitter region 18 having a depth of 1.2 μm. Further, the semiconductor device 2 is provided on a base electrode 20 provided in a partial region of the surface of the base region 16, an emitter electrode 22 provided in a partial region of the surface of the emitter region 18, and a back surface of the SiC substrate 10. The back electrode 25 is provided.

The base region 16 of the semiconductor device 2 was formed by implanting Al as impurity atoms into the n-type SiC conductive layer 13 by using an ion implantation method and changing the acceleration energy stepwise from 20 keV to 300 keV. Specifically, first, the acceleration energy was set to 150 keV, and aluminum ions (Al ions) as impurities were ion-implanted so that the dose amount was 1 × 10 ¹³ cm ⁻² . Next, the acceleration energy was set to 100 keV, and Al ions were ion-implanted so that the dose amount was 4 × 10 ¹² cm ⁻² . Furthermore, the acceleration energy was set to 50 keV, and Al ions were ion-implanted so that the dose amount was 2 × 10 ¹² cm ⁻² . Thereafter, annealing was performed at a temperature ranging from 1700 ° C. to 1900 ° C. in argon or vacuum.

  The emitter region 18 was also formed by ion implantation in the same manner as the base region 16 using P as an impurity atom. The base electrode 20 and the emitter electrode 22 were each formed with a two-layer metal layer structure of a nickel layer and an aluminum layer. The distance from the end X1 of the emitter electrode 22 to the boundary 17 between the base region 16 and the emitter region 18 was 2 μm.

  FIG. 5 shows the impurity concentration distribution of the semiconductor device according to the example. Specifically, FIG. 5A shows the impurity concentration in the X1-X2 direction of FIG. 4 (the direction horizontal to the surface of the semiconductor device). FIG. 5B shows the distribution of impurity concentration in the Y1-Y2 direction (direction along the thickness of the semiconductor device) in FIG.

  Here, the semiconductor device was manufactured by changing the impurity concentration of the base region 16 and the impurity concentration of the emitter region 18 in various ways. The value of the impurity concentration of the emitter region 18 described below corresponds to the “emitter concentration” shown in FIGS. 5 (a) and 5 (b). That is, as shown in FIGS. 5A and 5B, the density of the portion corresponding to the intersection of the emitter density distribution and the base density distribution is defined as “emitter density”. This emitter concentration corresponds to “the concentration of the emitter region in contact with the intrinsic base region”. In “emitter concentration”, the emitter concentration and the base concentration are substantially the same value. However, in this embodiment, “the emitter concentration and the base concentration are substantially the same” means that the base concentration (or emitter concentration) is 2 to 3 of the emitter concentration (or base concentration) based on the emitter concentration (or base concentration). It is assumed that the density difference is about double.

  In the semiconductor device 2 according to the example, the “emitter concentration” is a distance of 3 μm from X1 that is the end of the emitter electrode 22 toward X2 that is the end of the base electrode 20 on the emitter electrode 22 side, The concentration is 1.2 μm deep from the interface between the emitter electrode 22 and the emitter region 18, that is, the position Y 1 on the surface of the emitter region 18 toward the back surface Y 2 of the SiC substrate 10.

As a result, when the impurity concentration (emitter concentration) of the emitter region 18 is less than 5 × 10 ¹⁷ cm ⁻³ , the emitter resistance is very high, or the current does not substantially flow through the semiconductor device 2, and the current amplification factor Was less than 1. When the emitter concentration exceeded 5 × 10 ¹⁹ cm ⁻³ , the emitter resistance was low, but the current amplification factor was less than 1. On the other hand, when the emitter concentration is in the range of 5 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ or less, the semiconductor device 2 having a current amplification factor of 1 or more can be stably manufactured.

From the above results, it was considered that when the emitter concentration was a low concentration of less than 5 × 10 ¹⁷ cm ⁻³ , the current amplification factor was lowered due to the increase in the base current density accompanying the decrease in the number of emitter Gummels. In addition, when the emitter concentration is higher than 5 × 10 ¹⁹ cm ⁻³ , the base current density is increased by the narrow band gap effect and the emitter electron current is also decreased, so that the current amplification factor is considered to be lowered. .

  Further, when the distance between the end X1 of the emitter electrode 22 and the boundary 17 was variously changed, the current amplification factor decreased when the distance was less than 2 μm. This is because the base current density has increased due to the fact that the average diffusion distance of holes, which are minority carriers injected into the n-type emitter region 18, is larger than the average diffusion distance of majority carriers. It was considered.

  While the embodiments and examples of the present invention have been described above, the embodiments and examples described above do not limit the invention according to the claims. It should be noted that not all combinations of features described in the embodiments and examples are necessarily essential to the means for solving the problems of the invention.

DESCRIPTION OF SYMBOLS 1, 2 Semiconductor device 1a, 1b, 1c Semiconductor laminated structure 10 SiC substrate 11 n ⁺ type SiC conductive layer 12 1st conductive layer 13 n type SiC conductive layer 14 2nd conductive layer 16 Base region 17 Boundary 18 Emitter region 20 Base Electrode 22 Emitter electrode 22a End 30, 31 Mask 30a, 31a Opening

Claims (5)

A semiconductor substrate;
A first conductive layer of a first conductivity type provided on the semiconductor substrate and formed of silicon carbide;
A second conductive layer of a first conductivity type provided on the first conductive layer and having an impurity concentration lower than that of the first conductive layer and formed of silicon carbide;
A base region of a second conductivity type provided in the second conductivity layer and having a conductivity type different from the first conductivity type;
A first conductivity type emitter region provided in the base region, having a surface flush with the surface of the base region and having an impurity concentration of 5 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ or less. A semiconductor device comprising: The semiconductor device according to claim 1, wherein the base region has an impurity concentration of 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ¹⁹ cm ⁻³ or less. An emitter electrode provided on a part of the surface of the emitter region;
The semiconductor device according to claim 2, wherein a distance from an end of the emitter electrode to a boundary between the base region and the emitter region is equal to or greater than an average diffusion distance of minority carriers in the emitter region.   The semiconductor device according to claim 3, wherein a surface concentration of the emitter region in contact with the base region is lower than a concentration of the emitter region in contact with an intrinsic base region formed between the base region and the emitter region. Preparing a semiconductor substrate;
Forming a first conductive layer of a first conductivity type formed of silicon carbide on the semiconductor substrate;
Forming a second conductive layer of a first conductivity type having an impurity concentration lower than that of the first conductive layer on the first conductive layer and made of silicon carbide;
Forming a base region in a partial region of the second conductive layer by ion-implanting impurity atoms of a second conductivity type different from the first conductivity type while gradually changing acceleration energy; When,
The surface is coplanar with the surface of the base region, and the impurity ions of the first conductivity type are ion-implanted into the partial region of the base region while changing the acceleration energy stepwise to 5 × 10 ^17. forming an emitter region having an impurity concentration of cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ or less.