JP5204794B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a method for manufacturing a semiconductor device, which includes a step of vapor-phase-growing a nitride semiconductor growth layer in a trench of a semiconductor base layer in which the trench is formed.

A technique is known in which a nitride semiconductor growth layer is vapor-phase grown on the surface of a nitride semiconductor underlayer. In general, in this type of vapor phase growth technique, in order to vapor-deposit a semiconductor growth layer, a source gas is supplied to the surface of the semiconductor underlayer with the semiconductor underlayer heated to a growth temperature. Furthermore, in order to prevent nitrogen from escaping from the semiconductor underlayer, the semiconductor underlayer is often exposed to an ammonia (NH ₃ ) atmosphere until the semiconductor underlayer reaches a growth temperature.

  In the process of manufacturing a semiconductor device, it is often necessary to form a trench in the surface of a semiconductor underlayer and to vapor-phase grow a semiconductor growth layer in the trench. However, in the vapor phase growth method using a nitride semiconductor as a semiconductor material, when the semiconductor underlayer is exposed to high temperature and exposed to an ammonia atmosphere, a phenomenon that the side surface of the trench collapses (called mass transport) occurs. It is known. When the shape of the trench is broken by the mass transport, the characteristics of the semiconductor device are deteriorated. For this reason, in the vapor phase growth method using a nitride semiconductor as a semiconductor material, a technique for suppressing mass transport is required.

Non-Patent Document 1 proposes that aluminum gallium nitride (AlGaN) is useful as a nitride semiconductor in order to suppress mass transport. Non-Patent Document 1 describes that the reason why mass transport is suppressed is due to the presence of an aluminum-nitrogen bond (Al-N), and it is important to increase this bond (Al-N). Has been. Non-Patent Document 1 exemplifies aluminum gallium nitride (Al _0.1 Ga _0.9 N) having an aluminum molar ratio of 0.1.

In-plane GaN / AlGaN heterostructure fabricated by selective mass transport planar technology, “S. Nitta et al, Materials Science and Engineering B93 (2002) 139-142”

  As disclosed in Non-Patent Document 1, it is desirable to increase the molar ratio of aluminum in the nitride semiconductor if only focusing on suppressing the mass transport. However, the nitride semiconductor has a property that the band gap width increases as the molar ratio of aluminum increases, and as a result, the physical properties change greatly. For this reason, depending on the type of semiconductor device, there are many scenes where a nitride semiconductor with an increased aluminum molar ratio cannot be used. That is, when the molar ratio of aluminum is increased, depending on the type of semiconductor device, there is a case where the suppression of mass transport and the characteristics of the semiconductor device are in conflict. The present specification aims to provide a technique for suppressing mass transport during vapor phase growth.

  The technique disclosed in the present specification is characterized in that a nitride semiconductor underlayer is doped with aluminum. Even if the molar ratio of aluminum is not so high as disclosed in Non-Patent Document 1, mass transport can be sufficiently suppressed. On the other hand, depending on the type of the semiconductor device, the characteristics of the semiconductor device may not be deteriorated by suppressing the molar ratio of aluminum. As in Non-Patent Document 1, as long as attention is focused only on suppression of mass transport, the idea of suppressing the molar ratio of aluminum cannot be obtained. The present inventors have found that there is a form in which the characteristics of the semiconductor device are deteriorated when the molar ratio of aluminum in the nitride semiconductor is increased. Created a technology to suppress

The technology disclosed in this specification can be embodied in a method for manufacturing a semiconductor device. The manufacturing method includes a vapor phase growth process in which a nitride semiconductor growth layer is vapor-phase grown in a trench of a nitride semiconductor base layer in which a trench is formed in a surface layer portion. Then, at least part of the surface of the semiconductor base layer exposed to the trenches, in _{In x Al y Ga (1-} xy) N (0 ≦ x ≦ 1,0.00001 ≦ y ≦ 0.01,0 <1-xy ≦ 1) The Al-doped nitride semiconductor shown. Not only surface exposed to the trench, the surface exposed to the non-trench _{In x Al y Ga (1-} xy) N (0 ≦ x ≦ 1,0.00001 ≦ y ≦ 0.01,0 <1-xy ≦ 1) It may be an Al-doped nitride semiconductor represented by In this type of technical field, when the molar ratio of aluminum contained is 0.01 or less, an impurity (aluminum) is doped into the nitride represented by In _x Ga _(1-x) N. It is regarded as Al-doped nitride semiconductor.

In the manufacturing method disclosed in this specification, it is preferable that the semiconductor underlayer has a partial region of a conductivity type different from that of the semiconductor growth layer in the surface layer portion. Furthermore, the trench extends through the partial regions, surface _{In x Al y Ga (1-} xy) parts region exposed to the trench N (0 ≦ x ≦ 1,0.00001 ≦ y ≦ 0.01,0 <1-xy An Al-doped nitride semiconductor represented by ≦ 1) is desirable. In addition, as for a partial region, only the surface of the partial region exposed to a trench may be an Al dope nitride semiconductor, and the whole may be an Al dope nitride semiconductor.

  In the case of the above manufacturing method, a structure in which a semiconductor growth layer and a partial region of a conductivity type different from the semiconductor growth layer are adjacent to the surface layer portion of the semiconductor underlayer is obtained. Specifically, in the case of the above manufacturing method, a semiconductor device having a structure in which a semiconductor growth layer is sandwiched between partial regions can be manufactured. When manufacturing a semiconductor device having such a structure, if the distance between adjacent partial regions deviates from a set value, the manufactured semiconductor device may not exhibit desired characteristics. In the above manufacturing method, since the surface of the partial region is made of an Al-doped nitride semiconductor, mass transport is suppressed and the distance between the partial regions can be controlled to a set value. In addition, with respect to different conductivity types, when one is n-type, the other is p-type or i-type, and when one is p-type, the other is n-type or i-type.

  In the manufacturing method described above, prior to the vapor phase growth step, the step of vapor-depositing the partial region in an atmosphere containing aluminum as a dopant gas, and the trench penetrating the partial region are formed by etching from the surface of the partial region. It is preferable to provide a process. Thereby, the whole partial region can be made of an Al-doped nitride semiconductor.

  As described above, the present specification discloses a technique including a step of vapor-phase-growing a nitride semiconductor growth layer in a trench of a nitride semiconductor base layer in which a trench is formed. In this case, when the semiconductor growth layer is grown, oxygen is easily taken into the semiconductor growth layer from the semiconductor underlayer. Oxygen taken into the semiconductor growth layer is replaced with nitrogen in the semiconductor growth layer and functions as a donor for the semiconductor growth layer. This makes it difficult to adjust the impurity concentration in the semiconductor growth layer. In order to suppress oxygen from being taken into the semiconductor growth layer from the semiconductor underlayer, it is desirable to set the growth temperature of the semiconductor growth layer to a high temperature. However, generally, when the vapor deposition temperature is raised, mass transport is likely to occur. The vapor phase growth method disclosed in this specification is useful in such a situation.

That is, in the manufacturing method disclosed in this specification, the growth temperature in the vapor phase growth step is set so that the oxygen concentration taken into the semiconductor growth layer from the semiconductor underlayer is 1 × 10 ¹⁶ cm ⁻³ or less. Preferably it is. Alternatively, the growth temperature in the vapor phase growth process is desirably 980 ° C. or higher. As described above, in the manufacturing method disclosed in this specification, since the semiconductor underlayer is doped with aluminum, mass transport can be suppressed. For this reason, according to the manufacturing method disclosed in this specification, the generation of mass transport is suppressed by the doping of aluminum, and the concentration of oxygen taken in by growing the semiconductor growth layer at a high temperature is suppressed to a low concentration. Can do. As a result, according to the manufacturing method disclosed in this specification, a semiconductor device with a stable donor concentration can be manufactured.

  When the growth temperature in the vapor phase growth step is such a temperature that suppresses the oxygen concentration taken into the semiconductor growth layer, the semiconductor device is provided on the semiconductor underlayer, and the nitriding current flows in the lateral direction. Preferably, a physical channel layer is provided. In the semiconductor underlayer, the surface in contact with the channel layer may be the c-plane, and the surface in contact with the side surface of the semiconductor growth layer may be the a- or m-plane. Compared with the c-plane, in the vapor phase growth from the a- or m-plane, oxygen is easily taken into the semiconductor growth layer. Even in such a case, the manufacturing method disclosed in the present specification can suppress the concentration of oxygen contained in the vapor phase growth layer while suppressing the mass transport of the semiconductor underlayer.

  As described above, according to the manufacturing method disclosed in the present specification, mass transport during vapor phase growth can be suppressed, and the concentration of oxygen contained in the vapor phase growth layer can also be suppressed. Therefore, the impurity concentration of the vapor phase growth layer formed in the trench of the semiconductor base layer can be adjusted to a desired concentration.

  A semiconductor device manufactured by the manufacturing method disclosed in this specification includes a front surface electrode that is electrically connected to the channel layer, and a back surface electrode that is electrically connected to the back surface of the semiconductor base layer. The current flowing between the back electrodes preferably flows through the channel layer and the semiconductor growth layer. That is, it is preferably a vertical semiconductor device. In the case of a vertical semiconductor device, the size and impurity concentration of the semiconductor growth layer greatly affect the characteristics of the device. By suppressing the amount of oxygen taken into the semiconductor growth layer while suppressing mass transport, the size and impurity concentration of the semiconductor growth layer can be adjusted to desired levels. Note that the channel layer may have a heterojunction.

The semiconductor device disclosed in this specification includes a semiconductor underlayer and a semiconductor growth layer. The semiconductor underlayer is a nitride semiconductor in which a trench is formed in the surface layer portion. The semiconductor growth layer is a nitride semiconductor filled in the trench. In this semiconductor device, at least a portion of the semiconductor base layer side surface of the interface between the semiconductor base layer and the semiconductor growth _{layer, In x Al y Ga (1} -xy) N (0 ≦ x ≦ 1,0.00001 ≦ y ≦ 0.01, 0 <1-xy ≦ 1) Al-doped nitride semiconductor.

  According to the technology disclosed in this specification, a semiconductor device can be manufactured while suppressing mass transport without affecting the characteristics of the semiconductor device.

FIG. 1 is a cross-sectional view of a main part of the semiconductor device according to the first embodiment. FIG. 2 shows a manufacturing process of the semiconductor device of Example 1 (1). FIG. 3 shows a manufacturing process of the semiconductor device of Example 1 (2). FIG. 4 shows a manufacturing process of the semiconductor device of Example 1 (3). FIG. 5 shows a manufacturing process of the semiconductor device of Example 1 (4). FIG. 6 shows a manufacturing process of the semiconductor device of Example 1 (5). FIG. 7 is a cross-sectional view of a main part of the semiconductor device according to the second embodiment. FIG. 8 shows a manufacturing process of the semiconductor device of Example 2 (1). FIG. 9 shows a manufacturing process of the semiconductor device of Example 2 (2). FIG. 10 shows a manufacturing process of the semiconductor device of Example 2 (3). FIG. 11 shows the manufacturing process of the semiconductor device of Example 2 (4). FIG. 12 shows the manufacturing process of the semiconductor device of Example 2 (5). FIG. 13 shows a manufacturing process of the semiconductor device of Example 2 (6). FIG. 14 is a cross-sectional view of main parts of the semiconductor device of Example 3. FIG. 15 shows a manufacturing process of the semiconductor device of Example 3 (1). FIG. 16 shows a manufacturing process of the semiconductor device of Example 3 (2). FIG. 17 shows a manufacturing process of the semiconductor device of Example 3 (3). FIG. 18 is a cross-sectional view of main parts of the semiconductor device of Example 4. FIG. 19 shows a manufacturing process of the semiconductor device of Example 4 (1). FIG. 20 shows a manufacturing process of the semiconductor device of Example 4 (2). FIG. 21 shows the manufacturing process of the semiconductor device of Example 4 (3). FIG. 22 shows a manufacturing process of the semiconductor device of Example 4 (4).

Before describing the embodiments, some of the technical features of the embodiments are briefly described below.
(Feature 1) The growth temperature of the semiconductor growth layer is not less than 980 ° C. and not more than 1100 ° C.
(Feature 2) When the partial region is n-type, the concentration of the n-type impurity is made higher than that of other n-type regions of the semiconductor base layer.

The semiconductor device 100 will be described with reference to FIG. The semiconductor device 100 is a vertical semiconductor device, and a current flows between the drain electrode 2 and the source electrode 16. In FIG. 1, two unit structures 100a and 100b are shown. The unit structures 100a and 100b have the same structure. The semiconductor device 100 will be described in order from the back surface. A drain electrode 2 is provided on the back surface of the semiconductor device 100. The drain electrode 2 is a laminated electrode in which titanium (Ti) and aluminum (Al) are laminated. The drain electrode 2 is an example of a back electrode, and is connected to the high voltage side of a power source (not shown). An n-type first low resistance n-type region 4 is provided on the surface of the drain electrode 2. The material of the first low resistance n-type region 4 is gallium nitride (GaN). Silicon (Si) is used as an impurity of the first low-resistance n-type region 4, and the impurity concentration is about 3 × 10 ¹⁸ cm ⁻³ . The drain electrode 2 is electrically connected to the first low resistance n-type region 4. An n-type high-resistance n-type region 6 is provided on the surface of the first low-resistance n-type region 4. The material of the high resistance n-type region 6 is gallium nitride. Silicon is used as an impurity of the high-resistance n-type region 6, and the impurity concentration is about 1 × 10 ¹⁶ cm ⁻³ .

A plurality of p-type buried regions 8 are provided at intervals on the surface layer side of the high-resistance n-type region 6. The material of the buried region 8 is gallium nitride. Magnesium (Mg) is used as the impurity of the buried region 8 and the impurity concentration is approximately 1 × 10 ¹⁹ cm ⁻³ . Further, aluminum is used as an impurity in the buried region 8, and the impurity concentration is approximately 1 × 10 ²⁰ cm ⁻³ . When the material of the buried region 8 is expressed by a general formula, it becomes Al _0.001 GaN. When the molar ratio of aluminum is about 0.001, normally, aluminum is not evaluated as a constituent element of the buried region 8. The buried region 8 is evaluated as an aluminum-doped nitride in which aluminum is doped with gallium nitride. In addition, it is preferable that the density | concentration of the aluminum contained in the embedding area | region 8 exists in the range of 1 * 10 < ¹⁸ > -1 * 10 < ²¹ > cm < ^-3 >. When indicating the material of the buried region 8 of the concentration range in the general _{formula, In x Al y Ga (1} -xy) N (x + y = 1, 0.00001 ≦ y ≦ 0.01) becomes. When the molar ratio of aluminum is 0.01 or less, it is evaluated that aluminum is doped with gallium nitride. In the following description, a region located between the adjacent buried regions 8 in the high resistance n-type region 6 is referred to as an aperture region 18.

The n-type first semiconductor layer 28 is provided on a part of the surface of the buried region 8 and the entire surface of the aperture region 18. The first semiconductor layer 28 is continuously formed between part of the surfaces of the adjacent buried regions 8. The material of the first semiconductor layer 28 is gallium nitride. Silicon is used as an impurity of the first semiconductor layer 28, and its impurity concentration is approximately 1 × 10 ¹⁴ cm ⁻³ . That is, the material of the first semiconductor layer 28 is equal to the material of the high resistance n-type region 6. Therefore, the first semiconductor layer 28 and the high resistance n-type region 6 can also be regarded as one continuous region. It can also be said that part of the buried region 8 is buried in a region formed by the first semiconductor layer 28 and the high resistance n-type region 6.

An i-type second semiconductor layer 26 is provided on the surface of the first semiconductor layer 28. The material of the second semiconductor layer 26 is aluminum gallium nitride (AlGaN). Impurities such as magnesium are not introduced into the second semiconductor layer 26. Incidentally, indicating the material of the second semiconductor layer 26 in the general _{formula, In x Al y Ga (1} -xy) N (x = 0, 0.10 ≦ y ≦ 0.30) becomes. Therefore, aluminum contained in the second semiconductor layer 26 can be regarded as a constituent element of the second semiconductor layer 26. The band gap of the second semiconductor layer 26 is wider than the band gap of the first semiconductor layer 28. Therefore, a heterojunction is formed between the second semiconductor layer 26 and the first semiconductor layer 28. In the following description, the second semiconductor layer 26 and the first semiconductor layer 28 are collectively referred to as a channel layer 30.

The n ⁺ -type second low resistance n-type region 24 is partially provided in the surface layer portion of the channel layer 30. The deep portion of the second low resistance n-type region 24 reaches the junction surface between the first semiconductor layer 28 and the second semiconductor layer 26. When the semiconductor device 100 is viewed in plan, a part of the buried region 8 is located between the second low resistance n-type region 24 and the aperture region 18. The source electrode 16 is electrically connected to the second low resistance n-type region 24. That is, the source electrode 16 is electrically connected to the channel layer 30. The source electrode 16 is a laminated electrode in which titanium and aluminum are laminated. The source electrode 16 is an example of a surface electrode and is grounded.

The gate electrode 20 faces the channel layer 30 with the gate insulating film 22 interposed therebetween. The material of the gate electrode 20 is polycrystalline silicon doped with phosphorus, and the material of the gate insulating film 22 is silicon oxide (SiO ₂ ). The material of the gate electrode 20 may be aluminum. When the semiconductor device 100 is viewed in plan, the gate electrode 20 includes a part of the second low resistance n-type region 24 and the buried region 8 positioned between the second low resistance n-type region 24 and the aperture region 18. It faces the aperture region 18. The gate electrode 20 is insulated from the source electrode 16 by an insulating film (not shown). The body electrode 14 is electrically connected to the buried region 8. The material of the body electrode 14 is nickel (Ni). The body electrode 14 is grounded.

  An operation of the semiconductor device 100 will be described. The buried region 8 faces the channel layer 30. In a state where no voltage is applied to the gate electrode 20, a depletion layer extends from the p-type buried region 8 toward the channel layer 30. The depletion layer reaches the heterojunction surface of the first semiconductor layer 28 and the second semiconductor layer 26. When the heterojunction surface is depleted, the energy level of the conductor at the heterojunction surface is present above the Fermi level. Therefore, a two-dimensional electron gas layer cannot exist at the heterojunction surface. In a state where no voltage is applied to the gate electrode 20, the semiconductor device 100 is off. The semiconductor device 100 performs a normally-off operation.

When a positive voltage is applied to the gate electrode 20, the width of the depletion layer extending from the p-type buried region 8 toward the channel layer 30 is reduced. A two-dimensional electron gas layer is formed on the bonding surface between the first semiconductor layer 28 and the second semiconductor layer 26. Thereby, electrons injected from the source electrode 16 can travel through the two-dimensional electron gas layer. The electrons move laterally from the second low-resistance n-type region 24 at the junction surface between the first semiconductor layer 28 and the second semiconductor layer 26, and the aperture region 18, the high-resistance n-type region 6, the first low-resistance n-type. The region 4 is moved in the vertical direction and reaches the drain electrode 2. The drain electrode 2 and the source electrode are electrically connected. Note that holes generated in the high-resistance n-type region 6 due to avalanche breakdown during the operation of the semiconductor device 100 are extracted outside the semiconductor device 100 through the buried region 8 and the body electrode 14. When the hole concentration is about 3 × 10 ¹⁷ cm ⁻³ , the mobility of holes in the buried region 8 is about 10 cm ² / vs. This is almost the same result as the mobility of holes in gallium nitride not doped with aluminum.

A method for manufacturing the semiconductor device 100 will be described with reference to FIGS. First, as shown in FIG. 2, an n-type high-resistance n-type region 6 is vapor-phase grown on the surface of an n-type semiconductor substrate (first low-resistance n-type region) 4, and a p-type semiconductor layer 8 is further grown. Is vapor-phase grown on the surface of the high resistance n-type region 6. The semiconductor layer 8 finally becomes the buried region 8 of FIG. Therefore, in the following description, the embedded region 8 will be described. The buried region 8 is vapor-phase grown in an atmosphere containing aluminum and magnesium as dopant gases. The surface of the buried region 8 is a c-plane ((0001) plane). When crystal-growing the buried region 8, the concentration of the dopant gas is adjusted so that the concentration of aluminum contained in the buried region 8 is 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . In the step of vapor phase growth of the high resistance n-type region 6 and the buried region 8, the source gas is supplied after the temperature of the atmosphere becomes approximately 980 ° C. or higher. In the following description, the first low resistance n-type region 4, the high resistance n-type region 6, and the buried region 8 are collectively referred to as a semiconductor base layer 10. Thereafter, a mask 40 having an opening 40 a is formed on the surface of the buried region 8.

Next, as shown in FIG. 3, a portion of the p-type buried region 8 corresponding to the opening 40a is etched from the surface, and a trench 42 penetrating the buried region 8 and reaching the high resistance n-type region 6 is formed. Form. As a result, a trench 42 is formed in the surface layer portion 12 of the semiconductor underlayer 10. When the semiconductor underlayer 10 includes the first low-resistance n-type region 4, the high-resistance n-type region 6, and the buried region 8, the buried region 8 corresponds to a partial region described in the claims. The sidewall 8a of the buried region 8 contains 1 * 10 < ¹⁸ > to 1 * 10 < ²¹ > cm < ^-3 > as an impurity. The sidewall 8a of the buried region 8 is an a-plane ((00-20) plane), an m-plane ((1-100) plane), or a crystal plane close to those planes. That is, the sidewall 8a of the buried region 8 is a surface other than the c-plane. Next, as shown in FIG. 4, the n-type first semiconductor layer 28 is vapor-phase grown in the trench 42 (see also FIG. 3) of the semiconductor base layer 10 and on the surface of the semiconductor base layer 10 (gas phase). Phase growth process). The first semiconductor layer 28 is also vapor grown from the exposed surfaces 6 a and 8 a of the high resistance n-type region 6. The first semiconductor layer 28 corresponds to the semiconductor growth layer described in the claims. In this vapor phase growth step, the source gas is supplied after the temperature of the atmosphere reaches approximately 980 ° C. or higher. In the first semiconductor layer 28, the portion located between the buried regions 8 is the aperture region 18 (see FIG. 1). The temperature at which the first semiconductor layer 28 is grown is preferably 1100 ° C. or lower. As will be described later, the amount of oxygen taken into the first semiconductor layer 28 can be suppressed by increasing the growth temperature of the first semiconductor layer 28. However, if the growth temperature is too high (higher than 1100 ° C.), crystal decomposition may begin to occur. As a result, the quality of the semiconductor device 100 may deteriorate.

  Next, as shown in FIG. 5, the n-type second semiconductor layer 28 is vapor-phase grown on the surface of the first semiconductor layer 28. Thereby, the channel layer 30 having a heterojunction is formed. Thereafter, a mask 44 having an opening 44 a is formed on the surface of the second semiconductor layer 26. Thereafter, silicon is ion-implanted toward the second semiconductor layer 26 corresponding to the opening 44 a of the mask 44. The ion implantation is performed so that the silicon implantation range 24 reaches the heterojunction surface of the first semiconductor layer 28 and the second semiconductor layer 26. After removing the mask 44, a mask 46 having an opening 46a is formed on the surface of the second semiconductor layer 26 as shown in FIG. The width of the mask 46 is wider than the width of the mask 44 (see also FIG. 5). Thereafter, the second semiconductor layer 26 and the first semiconductor layer 28 corresponding to the opening 46a of the mask 46 are ion-etched. Thereby, the second low resistance n-type region 24 is formed, and a part of the surface of the buried region 8 is exposed. Note that the second semiconductor layer 26 and the first semiconductor layer 28 may be ion-etched to expose a part of the surface of the buried region 8, and then silicon may be ion-implanted toward the second semiconductor layer 26.

  Thereafter, the source electrode 16 is formed on the surface of the second low resistance n-type region 24, the body electrode 14 is formed on the surface of the buried region 8, and the drain electrode 2 is formed on the first low resistance n-type region 4. The gate electrode 20 is formed on the surface of the second semiconductor layer 26 via the gate insulating film 22. Thereby, the semiconductor device 100 shown in FIG. 1 is completed. In addition, since the formation method of the electrodes 16, 14, 2, and 20 is well-known, description is abbreviate | omitted. In the above embodiment, the source gas is supplied after the atmospheric temperature exceeds approximately 980 ° C. in all the vapor phase growth of the high resistance n-type region 6, the buried region 8, and the first semiconductor layer 28. However, in the step of vapor-phase growing the high resistance n-type region 6 and the buried region 8, the source gas may be supplied after the ambient temperature exceeds approximately 900 ° C.

Here, the reason why 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ of aluminum is introduced into the buried region 8 will be described. As described above, in the semiconductor device 100, the current moves in the aperture region 18 in the vertical direction. For this reason, when the width of the aperture region 18 (the interval between the adjacent buried regions 8) becomes narrow, it becomes difficult for current to flow. When vapor phase growth of a nitride semiconductor is performed, the semiconductor underlayer 10 is heated in an ammonia (NH ₃ ) gas atmosphere up to a temperature at which vapor phase growth occurs (approximately 900 ° C.). Thereby, nitrogen (N) is prevented from escaping from the semiconductor underlayer 10. If aluminum is not introduced into the buried region 8, the surface of the buried region 8 shown in FIG. 3 may be mass transported and moved into the trench 42 in the process of heating the semiconductor underlayer 10. . As a result, the width of the trench 42 (the interval between the adjacent buried regions 8) may deviate from the design value, and the width of the aperture region 18 may deviate from the design value. In the worst case, the aperture region 18 becomes p-type and the on-resistance becomes extremely high. In this embodiment, the buried region 8 is doped with aluminum to suppress mass transport of the surface of the buried region 8.

Conventionally, it has been known that mass transport can be suppressed by using aluminum gallium nitride instead of gallium nitride. Therefore, if only the mass transport is suppressed, it is sufficient to form the buried region 8 with aluminum gallium nitride. However, if the material of the buried region 8 is aluminum gallium nitride, the mobility and hole concentration of holes in the buried region 8 are lowered. That is, the specific resistance of the buried region 8 increases. As a result, problems such as a decrease in the breakdown voltage of the semiconductor device 100 may occur. For this reason, it is difficult to accurately control the width of the aperture region 18 while maintaining a high breakdown voltage. In the present embodiment, the concentration of aluminum contained in the buried region 8 is set to 1 × 10 ²¹ cm ⁻³ or less. Thereby, an increase in the specific resistance of the buried region is suppressed. As described above, a nitride semiconductor having an aluminum molar ratio of 0.01 or less is not regarded as aluminum gallium nitride but is regarded as gallium nitride. Therefore, it was thought that mass transport could not be suppressed. However, in the semiconductor device 100 of the present embodiment, it is possible to suppress mass transport while suppressing an increase in specific resistance. If the aluminum doping concentration is less than 1 × 10 ¹⁸ cm ⁻³ , the effect of aluminum can no longer be obtained, and mass transport cannot be suppressed.

  Next, the reason why the buried region 8 is vapor grown at 980 ° C. or higher will be described. As described above, the sidewall 8a of the buried region 8 is the a-plane or the m-plane. When a nitride semiconductor is vapor-phase grown from a surface other than the c-plane, the growth proceeds by lateral growth or facet growth. In the lateral growth or facet growth, oxygen is easily taken into the growth film as compared with the c-plane growth. In particular, when vapor phase growth is performed at a low temperature (about 900 ° C.), a large amount of oxygen is taken into the growth film. Therefore, when the source gas is introduced at about 900 ° C., oxygen is excessively taken into the first semiconductor layer 28. When oxygen is excessively taken into the first semiconductor layer 28, the oxygen is replaced with nitrogen which is a material of the first semiconductor layer 28. The oxygen functions as a donor for the first semiconductor layer 28. That is, the concentration of the n-type impurity in the first semiconductor layer 28 increases. It becomes difficult to adjust the impurity concentration of the aperture region 18 to a desired value. When the semiconductor device 100 is off, a depletion layer extends from the buried region 8 toward the aperture region 18. If the impurity concentration of the aperture region 18 is not adjusted to a desired value, the breakdown voltage of the semiconductor device 100 may decrease or the leakage current may increase.

However, when the first semiconductor layer 28 is vapor-phase grown at 980 ° C. or higher as in this embodiment, the amount of oxygen taken into the growth film can be reduced. Specifically, the oxygen concentration taken into the first semiconductor layer 28 can be suppressed to 3 × 10 ¹⁶ cm ⁻³ or less. If the oxygen concentration is 3 × 10 ¹⁶ cm ⁻³ or less, the characteristics of the semiconductor device 100 can be maintained at a desired level.

  The first semiconductor layer 28 can be grown at 980 ° C. or more because the buried region 8 is doped with aluminum. As described above, if the buried region 8 is not doped with aluminum, mass transport occurs in the process of growing the first semiconductor layer 28. Since the mass transport becomes more noticeable as the temperature becomes higher, the first semiconductor layer 28 cannot be grown at 980 ° C. or higher unless the buried region 8 is doped with aluminum.

The semiconductor device 200 will be described with reference to FIG. The semiconductor device 200 is a modification of the semiconductor device 100, and the description of the substantially same structure as that of the semiconductor device 100 is omitted by giving the same reference numerals. The semiconductor device 200 has two unit structures 200a and 200b. The material of the high resistance n-type region 206 is gallium nitride. Silicon is used as the impurity of the high-resistance n-type region 206, and the impurity concentration is about 1 × 10 ¹⁶ cm ⁻³ . A plurality of p-type buried regions 208 are provided at intervals on the surface of the high-resistance n-type region 206. The material of the buried region 208 is gallium nitride. Magnesium (Mg) is used as the impurity of the buried region 208, and the impurity concentration is approximately 1 × 10 ¹⁹ cm ⁻³ . The buried region 208 is not doped with aluminum.

A plurality of aperture regions 218 are provided at intervals on the surface of the high resistance n-type region 206. The aperture region 218 is located between the embedded regions 208. The material of the aperture region 218 is gallium nitride. Silicon is used as an impurity in the aperture region 218, and the impurity concentration is about 3 × 10 ¹⁶ cm ⁻³ . Further, aluminum is used as an impurity in the aperture region 218, and the impurity concentration is about 1 × 10 ²⁰ cm ⁻³ . That is, the semiconductor device 200 is different from the semiconductor device 100 in that the buried region 208 is not doped with aluminum, the aperture region 218 is doped with aluminum, and the concentration of silicon doped in the aperture region 218. The concentration of silicon contained in the aperture region 218 is higher than the concentration of silicon contained in the high resistance n-type region 206. In the semiconductor device 200, the aperture region 218 is doped with aluminum. Therefore, when the concentration of silicon doped in the aperture region 218 is equal to the concentration of silicon doped in the high resistance n-type region 206, the resistance of the aperture region 218 is increased. In order to reduce the resistance of the aperture region 218, the concentration of silicon doped in the aperture region 218 is increased.

  A method for manufacturing the semiconductor device 200 will be described with reference to FIGS. First, as shown in FIG. 8, an n-type high-resistance n-type region 206 is vapor-phase grown on the surface of the n-type first low-resistance n-type region 4, and an n-type semiconductor layer 218 is further formed with a high-resistance n Vapor phase growth is performed on the surface of the mold region 206. The semiconductor layer 218 is vapor grown in an atmosphere containing aluminum as a dopant gas. The surface of the semiconductor layer 218 is a c-plane. Thereafter, a mask 60 having an opening 60 a is formed on the surface of the semiconductor layer 218.

Next, as shown in FIG. 9, etching is performed from the surface of the n-type semiconductor layer 218, thereby forming a trench 232 defined by the sidewall 218 a of the semiconductor layer 218 and the surface 206 a of the high-resistance n-type region 206. Thereby, the aperture region 218 shown in FIG. 7 is completed. Note that the trench 232 may penetrate the semiconductor layer 218 and reach the high resistance n-type region 206 in order to reliably remove the semiconductor layer 218. A semiconductor base layer 210 having a trench 232 is formed by the aperture region 218, the high resistance n-type region 206, and the first low resistance n-type region 4. The side wall 218a of the semiconductor layer 218 contains 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ^{−3 of} aluminum which is an impurity.

  Next, as shown in FIG. 10, the p-type semiconductor layer 208 is vapor-phase grown in the trench 232 (see also FIG. 9) of the semiconductor base layer 210 and on the surface of the semiconductor base layer 210 (vapor-phase growth). Process). In this embodiment, the p-type semiconductor layer 208 corresponds to the semiconductor growth layer described in the claims. The aperture region 218 corresponds to a partial region described in the claims. In the vapor phase growth process, the source gas is supplied after the temperature of the atmosphere reaches approximately 980 ° C. or higher. Next, as shown in FIG. 11, the semiconductor layer 208 is etched from the surface until the surface of the aperture region 218 is exposed. Thereby, the buried region 208 shown in FIG. 7 is completed. The buried region 208 fills the trench 232.

  Next, as shown in FIG. 12, the n-type first semiconductor layer 28 is vapor-phase grown on the surfaces of the aperture region 218 and the buried region 208. Next, the n-type second semiconductor layer 26 is vapor-phase grown on the surface of the first semiconductor layer 28, thereby forming the channel layer 30 having a heterojunction. Thereafter, a mask 62 having an opening 62 a is formed on the surface of the second semiconductor layer 26. Thereafter, silicon is ion-implanted toward the second semiconductor layer 26 corresponding to the opening 62 a of the mask 62. After removing the mask 62, a mask 64 having an opening 64 is formed on the surface of the second semiconductor layer 26 as shown in FIG. The width of the mask 64 is wider than the width of the mask 62 shown in FIG. Thereafter, the second semiconductor layer 26 and the first semiconductor layer 28 corresponding to the opening 64a of the mask 64 are ion-etched. Since the following manufacturing process is the same as that of the semiconductor device 100, it is omitted.

The semiconductor device 300 will be described with reference to FIG. The semiconductor device 300 is a modification of the semiconductor device 200, and the description of the substantially same structure as the semiconductor device 200 will be omitted by giving the same reference numerals. Here, only differences from the semiconductor device 200 will be described. The semiconductor device 300 has two unit structures 300a and 300b. In the semiconductor device 300, the n-type third semiconductor layer 370 is interposed between the buried region 308, the high-resistance n-type region 206, and the aperture region 218. The material of the third semiconductor layer 370 is gallium nitride. Silicon is used as the impurity of the third semiconductor layer 370, and the impurity concentration is about 1 × 10 ¹⁶ cm ⁻³ . The third semiconductor layer 370 is provided to prevent the buried region 308 from directly contacting the surface of the high resistance n-type region 206.

  The manufacturing method of the semiconductor device 300 and the effect of forming the third semiconductor layer 370 will be described with reference to FIGS. First, similarly to the semiconductor device 200, the steps of FIGS. Description of the steps from FIG. 8 to FIG. 9 is omitted. After forming the semiconductor base layer 210, an n-type third semiconductor layer 370 is vapor-phase grown on the entire surface of the semiconductor base layer 210 as shown in FIG. The vapor phase growth of the third semiconductor layer 370 is performed at a temperature of 980 ° C. or higher. The thickness of the third semiconductor layer 370 is approximately 0.5 μm. Even if the third semiconductor layer 370 is grown, the third semiconductor layer 370 does not completely fill the trench 232. Therefore, a trench 332 defined by the partial third semiconductor layer 370b grown from the side wall 218a of the aperture region 218 and the partial third semiconductor layer 370a grown from the exposed surface 206a of the high resistance n-type region 206 is formed. Note that the third semiconductor layer 370 is vapor-grown at 980 ° C. or higher, so that excessive oxygen can be prevented from being taken into the third semiconductor layer 370.

  Next, as shown in FIG. 16, the p-type buried region 308 is vapor-phase grown in the trench 332 and on the surface 370 c of the third semiconductor layer 370. In this embodiment, the p-type buried region 308 corresponds to the semiconductor growth layer described in the claims. Next, as shown in FIG. 17, the buried region 308 is etched until the surface of the aperture region 218 is exposed. Since the subsequent steps are the same as the steps after FIG. 12 of the method for manufacturing the semiconductor device 200, description thereof will be omitted.

  As described above, by providing the third semiconductor layer 370, the exposed surface 206a of the high resistance n-type region 206 shown in FIG. 9 is covered. As shown in FIGS. 8 and 9, the exposed surface 206 a is exposed by etching the semiconductor layer 218. Therefore, a defect due to etching is formed on the exposed surface 206a. When the p-type buried region 308 is formed directly on the exposed surface 206a, the impurity (magnesium) contained in the buried region 308 easily moves to the high-resistance n-type region 206 through the defect. When the exposed surface 206 a is covered with the third semiconductor layer 370, the impurity can be prevented from moving from the buried region 308 to the high resistance n-type region 206.

  Note that the third semiconductor layer 370 may contain aluminum as an impurity. It is possible to suppress the mass transport of the third semiconductor layer 370. As described above, the purpose of forming the third semiconductor 370 is to prevent the buried region 308 from directly contacting the exposed surface 206a of the high resistance n-type region 206. Further, as described above, the thickness of the third semiconductor layer 370 is very thin. Therefore, even if the third semiconductor layer 370 is mass transported, the characteristics of the semiconductor device 300 are hardly affected unless the aperture region 218 is mass transported. Therefore, it is not always necessary to dope the third semiconductor layer 370 with aluminum.

FIG. 18 is a cross-sectional view of the main part of the semiconductor device 400. The semiconductor device 400 is a horizontal semiconductor device. The semiconductor device 400 will be described in order from the back surface. The description of the structure substantially the same as that of the semiconductor devices 100, 2, 300 will be omitted by attaching the same reference numerals to the last two digits. A buffer layer 472 is provided on the surface of the sapphire substrate 471, and n-type semiconductor layers 474 and 476 are provided on the surface of the buffer layer 472. The material of the semiconductor layers 474 and 476 is gallium nitride. Silicon is used as an impurity of the semiconductor layers 474 and 476, and the impurity concentration is approximately 1 × 10 ¹⁴ cm ⁻³ . Therefore, the semiconductor layers 474 and 476 can be regarded as one semiconductor layer 475. An i-type second semiconductor layer 426 is provided on the surface of the semiconductor layer 476. The material of the second semiconductor layer 426 is aluminum gallium nitride (AlGaN). Impurities such as magnesium are not introduced into the second semiconductor layer 426.

A p-type buried region 408 is buried inside the semiconductor layer 475. The material of the buried region 408 is gallium nitride. Magnesium is used as the impurity of the buried region 408, and the impurity concentration is approximately 1 × 10 ¹⁹ cm ⁻³ . Further, aluminum is used as an impurity in the buried region 408, and the impurity concentration is approximately 1 × 10 ²⁰ cm ⁻³ . The semiconductor layer 476 and the second semiconductor layer 426 form a heterojunction. Of the semiconductor layer 476, a channel layer 430 is formed by the first semiconductor layer 428 and the second semiconductor layer 426 located on the buried region 408. An n ⁺ -type second low resistance n-type region 424 and an n ⁺ -type first low resistance n-type region 404 are provided in the second semiconductor layer 426 with a space therebetween. A source electrode 416 is electrically connected to the second low resistance n-type region 424, and a drain electrode 402 is electrically connected to the first low resistance n-type region 404.

  A gate electrode 420 is provided between the source electrode 416 and the drain electrode 402. The gate electrode 420 faces the second semiconductor layer 426 with the gate insulating film 422 interposed therebetween. When the semiconductor device 400 is viewed in plan, the gate electrode 420 faces the buried region 408. In the semiconductor device 400, a current flows laterally between the first low resistance n-type region 404 and the second low resistance n-type region 424.

  A method for manufacturing the semiconductor device 400 will be described with reference to FIGS. First, as illustrated in FIG. 19, the buffer layer 472 is formed on the surface of the sapphire substrate 471, and the n-type semiconductor layer 474 is formed on the surface of the buffer layer 472. Next, a semiconductor layer 408 containing magnesium and aluminum as impurities is grown in a vapor phase on the surface of the semiconductor layer 474. The semiconductor layer 408 eventually becomes the buried region 408 shown in FIG. Thereafter, a mask 480 having an opening 480 a is formed on the surface of the buried region 408.

  Next, as shown in FIG. 20, the buried region 408 exposed in the opening 480 a is dry-etched from the surface to expose a part of the surface of the semiconductor layer 474. The etched buried region 408 and the semiconductor layer 474 correspond to the semiconductor base layer 410. A trench 432 is formed by the side wall 408 a of the buried region 408 and the exposed surface 474 a of the semiconductor layer 474. The sidewall 408a of the buried region 408 is doped with aluminum. After removing the mask 480, as shown in FIG. 21, the semiconductor layer 476 is vapor-grown on the inside of the trench 432 and the surface of the buried region 408 (vapor-phase growth step). The impurity concentration of the semiconductor layer 476 is equal to that of the semiconductor layer 474. Of the semiconductor layer 476, the portion located on the buried region 408 is the first semiconductor layer 428. In this embodiment, the n-type semiconductor layer 476 corresponds to the semiconductor growth layer recited in the claims. Further, the p-type buried region 408 in the semiconductor underlayer 410 corresponds to a partial region described in the claims.

  Next, as shown in FIG. 22, the second semiconductor layer 426 is vapor-phase grown on the surface of the semiconductor layer 476. Thereby, the channel layer 430 is formed. Next, a mask 482 having an opening 482a is formed, and silicon is ion-implanted toward the opening 482a, whereby a second low-resistance n-type region 424 and a first low-resistance n-type region 404 are formed. Thereafter, by forming a source electrode and a drain electrode, the semiconductor device 400 shown in FIG. 18 is completed.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in the present specification or the drawings can achieve a plurality of objects at the same time, and has technical utility by achieving one of the objects.

8, 218, 408: Partial regions 10, 210, 410: Semiconductor underlayers 28, 208, 308, 476: Semiconductor growth layers 30, 430: Channel layers 42, 232, 332, 432: Trench 100, 200, 300, 400 : Semiconductor device

Claims (9)

A method for manufacturing a semiconductor device, comprising:
A vapor phase growth step of vapor-phase-growing a nitride semiconductor growth layer in the trench of the nitride semiconductor base layer in which a trench is formed in a surface layer portion;
At least a portion of a surface of said semiconductor base layer exposed to the trench, in _{In x Al y Ga (1-} xy) N (0 ≦ x ≦ 1,0.00001 ≦ y ≦ 0.01,0 <1-xy ≦ 1) A manufacturing method which is an Al-doped nitride shown. The semiconductor underlayer has a partial region of a conductivity type different from that of the semiconductor growth layer in a surface layer portion,
The trench penetrates the partial region,
The manufacturing method according to claim 1, wherein a surface of the partial region exposed in the trench is the Al-doped nitride. Prior to the vapor phase growth step,
Vapor-phase-growing the partial region in an atmosphere containing aluminum as a dopant gas;
The manufacturing method according to claim 2, further comprising: etching from a surface of the partial region to form the trench penetrating the partial region. The growth temperature in the vapor phase growth step is set so that the oxygen concentration taken into the semiconductor growth layer from the semiconductor underlayer is 1 × 10 ¹⁶ cm ⁻³ or less. The manufacturing method according to one item.   The growth method of the said vapor phase growth process is 980 degreeC or more, The manufacturing method as described in any one of Claims 1-4. The semiconductor device includes:
Provided on the semiconductor underlayer, comprising a nitride channel layer through which current flows laterally;
6. The manufacturing method according to claim 4, wherein the surface of the semiconductor underlayer that contacts the channel layer is a c-plane, and the surface that contacts the side surface of the semiconductor growth layer is an a- or m-plane. The semiconductor device includes:
A surface electrode electrically connected to the channel layer;
A back electrode electrically connected to the back surface of the semiconductor underlayer, and
The manufacturing method according to claim 6, wherein a current flowing between the front surface electrode and the back surface electrode flows through the channel layer and the semiconductor growth layer.   The manufacturing method according to claim 6, wherein the channel layer has a heterojunction. A semiconductor device,
A nitride semiconductor underlayer having a trench formed in the surface layer portion;
A nitride semiconductor growth layer filled in the trench, and
Wherein at least a portion of said semiconductor base layer side of the surface of the interface between the semiconductor base layer and the semiconductor growth _{layer, In x Al y Ga (1} -xy) N (0 ≦ x ≦ 1,0.00001 ≦ y ≦ 0.01 , 0 <1-xy ≦ 1), a semiconductor device that is an Al-doped nitride.

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