JP2008205175A - Method of manufacturing nitride semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a nitride semiconductor element capable of bringing a contact electrode into ohmic contact with a p-type group III nitride semiconductor layer (channel layer) satisfactorily. <P>SOLUTION: In a process for manufacturing a field effect transistor composed of a group III nitride semiconductor, an n-type GaN layer 2 and a p-type GaN layer 3 are formed on a substrate 12. Then, on the p-type GaN layer 3, the contact electrode 15 is formed. After the contact electrode 15 is formed, an n-type GaN layer 4 is formed in a region from the p-type GaN layer 3 to the contact electrode 15, and a contact hole 14 from the surface of the n-type GaN layer 4 to the contact electrode 15 is formed. A source electrode 11 is embedded in the contact hole 14. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a nitride semiconductor device using a group III nitride semiconductor.

Conventionally, power devices using silicon semiconductors are used in power amplifier circuits, power supply circuits, motor drive circuits, and the like.
However, due to the theoretical limits of silicon semiconductors, the increase in breakdown voltage, reduction in resistance, and increase in speed of silicon devices are reaching their limits, and it is becoming difficult to meet market demands.
Therefore, development of GaN devices having characteristics such as high breakdown voltage, high temperature operation, large current density, high-speed switching, and low on-resistance has been studied (for example, see Non-Patent Document 1).

  Examples of GaN devices proposed so far include, for example, an n-type GaN drain layer to which a drain electrode is connected, a p-type GaN channel layer facing a gate electrode across a gate insulating film, and an n-type to which a source electrode is connected. A vertical n-channel MIS (Metal Insulator Semiconductor) field effect transistor having a stacked structure including a p-type GaN source layer can be exemplified (see, for example, Patent Document 1).

  By the way, in such a GaN device, when the potential of the p-type GaN channel layer fluctuates without stabilizing to a constant potential, the gate threshold voltage fluctuates with the potential fluctuation of the p-type GaN channel layer. Due to the influence of the substrate bias effect, it becomes difficult to control the gate threshold voltage. As a result, there is a problem in that a leak current flows in the device during transistor operation.

Therefore, in order to stabilize the potential of the p-type GaN channel layer, for example, a countermeasure can be considered in which the p-type GaN channel layer and the source electrode are brought into ohmic contact and short-circuited.
For example, in the case of the configuration of the GaN device described in Patent Document 1, in order to make ohmic contact between the p-type GaN channel layer and the source electrode in the manufacturing process, the p-type GaN channel layer is formed from the surface of the n-type GaN source layer. The n-type GaN source layer is dry-etched until the source electrode is formed, and the source electrode is formed so as to be in contact with the p-type GaN channel layer exposed by this dry etching.
JP 2003-163354 A Satoshi Okubo, “GaN is behind the evolution of equipment, not just shining”, June 5, 2006, Nikkei Electronics, p. 51-60

  However, in the above-described GaN device manufacturing process, the surface of the p-type GaN channel layer is exposed by performing dry etching, so that the surface of the p-type GaN channel layer may be eroded and roughened. Therefore, it is difficult to satisfactorily make ohmic contact between the source electrode and the surface of the p-type GaN channel layer, and stabilization of the potential of the p-type GaN channel layer may not be achieved. Of course, as described above, the contact electrode is not in ohmic contact with the p-type GaN channel layer, but the contact electrode is in ohmic contact with the p-type GaN channel layer, and the source electrode is connected to the contact electrode. In some cases, there is a similar problem.

  Accordingly, an object of the present invention is to provide a method of manufacturing a nitride semiconductor device capable of satisfactorily making ohmic contact of a contact electrode with a p-type group III nitride semiconductor layer (channel layer).

  In order to achieve the above object, the invention as set forth in claim 1 is a first layer forming step of forming an n-type first layer made of a group III nitride semiconductor, and a group III nitride on the first layer. A second layer forming step of stacking a second layer containing a p-type impurity made of a semiconductor; a p-type contact electrode forming step of forming a p-type contact electrode on the second layer; and forming the p-type contact electrode And a third layer forming step of stacking an n-type third layer made of a group III nitride semiconductor on the second layer after the step.

  According to this method, after the first layer and the second layer are formed in this order, the p-type contact electrode is formed on the second layer before the third layer is formed. Since the surface of the second layer is not roughened at the stage where the second layer is formed, the p-type contact electrode is changed to the second layer by appropriately selecting the material of the p-type contact electrode. Good ohmic contact can be achieved. In addition, after the p-type contact electrode is formed, the third layer is laminated on the second layer.

  Thus, for example, the source electrode is provided so as to be in contact (ohmic contact) with the p-type contact electrode and the third layer, and the gate insulating film is formed so as to straddle the first, second and third layers. A vertical MIS (Metal Insulator Semiconductor) field effect transistor is provided by providing a gate electrode so as to face the second layer across the film and further providing a drain electrode so as to be electrically connected to the first layer. (Hereinafter, this transistor is simply referred to as “MISFET”).

  In this case, since the second layer and the p-type contact electrode are in ohmic contact, and the source electrode and the p-type contact electrode are in ohmic contact, the source electrode is connected to a predetermined reference potential (for example, ground potential). By doing so, the potential of the second layer becomes a predetermined reference potential via the p-type contact electrode. As described above, since the potential of the second layer can be stabilized at a predetermined reference potential, fluctuations in the gate threshold voltage can be suppressed. As a result, it is possible to prevent a leak current from flowing in the device due to the fluctuation of the gate threshold voltage. That is, the gate threshold voltage controllability can be improved. Note that the p-type contact electrode may be directly connected to a predetermined reference potential (for example, ground potential) without using the source electrode. Also by this, the potential of the second layer becomes a predetermined reference potential via the p-type contact electrode.

  In addition, by making the nitride semiconductor element a basic structure as a MISFET, it is possible to easily realize a normally-off operation, that is, an operation in which the source and drain are turned off when no bias is applied to the gate electrode. . Furthermore, since the MISFET has a vertical structure, a large current can be easily flown by integration, and a high breakdown voltage can be easily ensured by increasing the thickness of the first layer. . Therefore, an effective power device can also be provided. Of course, the field effect transistor is made up of a group III nitride semiconductor layer, which has features such as high breakdown voltage, high temperature operation, large current density, high-speed switching, and low on-resistance compared to devices using silicon semiconductors. You can also enjoy it. In particular, since a high voltage and low loss operation is possible, a good power device can be realized.

Note that a group III nitride semiconductor is a semiconductor in which a group III element and nitrogen are combined, and aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN) are representative examples. In general, it can be expressed as Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).
Next, the operation of this MISFET will be described. First, a bias is applied between the source and the drain so that the drain side is positive. At this time, since a reverse voltage is applied to the pn junction at the interface between the first and second layers, the source and drain are cut off. In this state, when a bias voltage equal to or higher than a predetermined voltage value (gate threshold voltage) that is positive with respect to the second layer is applied to the gate electrode, a region in the vicinity of the surface facing the gate electrode in the second layer ( Electrons are induced in the channel region, and an inversion layer (channel) is formed. Through this inversion layer, the first and third layers are conducted, and the source and drain are conducted. In this way, the source-drain conducts when an appropriate bias is applied to the gate electrode, while the source-drain is cut off when no bias is applied to the gate electrode. That is, a normally-off operation is realized.

The invention according to claim 2 further includes a contact hole forming step of forming a contact hole penetrating the third layer and reaching the p-type contact electrode after the third layer forming step. The method for producing a nitride semiconductor device according to the above.
According to this method, after the third layer is formed, a contact hole that reaches the p-type contact electrode through the third layer is formed. Therefore, by burying the source electrode in this contact hole, the source electrode and the p-type contact electrode can be brought into ohmic contact.

According to a third aspect of the present invention, there is provided a wall surface forming step of forming a wall surface straddling the first, second and third layers, a gate insulating film forming step of forming a gate insulating film along the wall surface, The method for manufacturing a nitride semiconductor device according to claim 1, further comprising: a gate electrode forming step of forming a gate electrode so as to face the second layer with a gate insulating film interposed therebetween.
By this method, the MISFET having the above-described configuration can be obtained.

  According to a fourth aspect of the present invention, there is provided a wall surface forming step for forming a wall surface straddling the first, second, and third layers, and a semiconductor surface portion of the second layer exposed by the wall surface forming step. A fourth layer forming step of forming a fourth layer having different conduction characteristics from the two layers, a gate insulating film forming step of forming a gate insulating film in contact with the fourth layer, and the gate insulating film sandwiched between The method for manufacturing a nitride semiconductor device according to claim 1, further comprising a gate electrode forming step of forming a gate electrode so as to face the fourth layer.

According to this method, a wall surface straddling the first, second, and third layers is formed, and the second surface of the semiconductor surface exposed by the wall surface formation is a region having a different conduction characteristic from the second layer. Four layers are formed. A gate insulating film is formed so as to be in contact with the fourth layer, and a gate electrode is formed so as to face the fourth layer with the gate insulating film interposed therebetween.
As a result, the region where the inversion layer (channel) is formed becomes the fourth layer during the operation of the MISFET configured as described above. Therefore, when the fourth layer is a p-type semiconductor having an acceptor concentration lower than that of the second layer, for example, the conduction characteristic of the region where the inversion layer is formed is the same as the conduction characteristic of the second layer. As compared with, the gate voltage value required for forming the inversion layer can be kept low. The factor that determines the voltage value of the reach-through breakdown is the acceptor concentration of the second layer. As a result, it is possible to reduce the gate threshold voltage while ensuring the high breakdown voltage of the transistor, and to realize a good power device. it can.

  The fourth layer may be a p-type semiconductor having an acceptor concentration lower than that of the second layer described above. For example, an n-type semiconductor, an i-type semiconductor, and n-type and p-type impurities may be used. Any of the included semiconductors may be used. When the fourth layer is an n-type semiconductor, the concentration of the n-type impurity can be appropriately controlled in order to realize a normally-off operation of the field effect transistor.

Furthermore, the invention according to claim 5 is characterized in that the third layer forming step includes a step of growing an n-type group III nitride semiconductor at a temperature lower than the melting point of the p-type contact electrode. It is a manufacturing method of the nitride semiconductor device given in any 1 paragraph.
According to this method, since the n-type group III nitride semiconductor is grown at a temperature lower than the melting point of the p-type contact electrode, the p-type contact electrode is prevented from being melted by heat at the time of forming the third layer. be able to.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view for explaining the structure of a field effect transistor manufactured by the manufacturing method of the present invention, and shows the first structure.
The field effect transistor (nitride semiconductor device) includes a substrate 12 and a nitride semiconductor multilayer structure portion 1 made of a GaN compound semiconductor layer grown on the substrate 12.

As the substrate 12, for example, an insulating substrate such as a sapphire substrate, or a conductive substrate such as a GaN substrate, a ZnO substrate, a Si substrate, a GaAs substrate, and a SiC substrate can be applied.
The nitride semiconductor multilayer structure portion 1 includes an n-type GaN layer 2 (first layer), a p-type GaN layer 3 (second layer), and an n-type GaN layer 4 (third layer). The layers are stacked in this order. The n-type GaN layer 2, the p-type GaN layer 3, and the n-type GaN layer 4 are not limited to GaN compounds as long as they are group III nitride semiconductors in which a group III element and nitrogen are combined. For example, aluminum nitride (AlN), indium nitride (InN), etc., which are generally nitride semiconductors that can be expressed as Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) I just need it.

  The nitride semiconductor multilayer structure 1 is etched in a direction crossing the multilayer interface from the n-type GaN layer 4 to a depth at which the n-type GaN layer 2 is exposed so as to have a trapezoidal cross section (mesa shape). The n-type GaN layer 2 is drawn from both sides of the nitride semiconductor multilayer structure 1 in the lateral direction along the multilayer interface of the nitride semiconductor multilayer structure 1 (hereinafter, this direction is referred to as “width direction”). It has a drawn part 5. A drain electrode 6 is formed in contact with the surface of the lead portion 5. That is, the lead-out portion 5 drawn out in the width direction from the nitride semiconductor multilayer structure portion 1 is constituted by an extension portion of the n-type GaN layer 2 in this embodiment.

On the other hand, in the vicinity of the middle in the width direction of the nitride semiconductor multilayer structure portion 1, a wall surface 7 extending over the n-type GaN layer 2, the p-type GaN layer 3, and the n-type GaN layer 4 is formed as the lead-out portion 5 is formed. Has been.
The region 10 (fourth layer) in the vicinity of the wall surface 7 in the p-type GaN layer 3 is a semiconductor having conductivity different from that of the p-type GaN layer 3, for example, p having an acceptor concentration lower than that of the p-type GaN layer 3. ^{-Made of} type semiconductor. The thickness of the region 10 in the direction orthogonal to the wall surface 7 is, for example, several nm to 100 nm. Note that the region 10 is not limited to a p ⁻ type semiconductor as long as it has a conductivity different from that of the p-type GaN layer 3. For example, an n-type semiconductor containing an n-type impurity or an i-type semiconductor containing almost no impurities. A semiconductor containing n-type and p-type impurities may be used. In the vicinity of the surface of the region 10, an inversion layer (channel) that electrically connects the n-type GaN layers 2 and 4 is formed by applying an appropriate bias voltage to the gate electrode 9.

A contact hole 14 is formed in the nitride semiconductor multilayer structure portion 1. The contact hole 14 is formed to a depth from the n-type GaN layer 4 to the p-type GaN layer 3. A contact electrode 15 and a source electrode 11 are embedded in the contact hole 14.
In this embodiment, the contact electrode 15 is embedded from the bottom of the contact hole 14 to a height approximately at the center of the n-type GaN layer 4, and the lower contact electrode 16 embedded in the bottom of the contact hole 14. And the upper contact electrode 17 buried on the lower contact electrode 16 are joined together.

  The lower contact electrode 16 is made of a material capable of forming an ohmic junction with the p-type GaN layer 3, for example, a metal material containing Pd or Ni. More specifically, it can be composed of a Pd—Au alloy, a Pd—Ti—Au alloy, a Pd—Pt—Au alloy, a Ni—Au alloy, or the like. Since these metals have low contact resistance to the p-type GaN layer 3, the lower contact electrode 16 is formed on the bottom surface of the contact hole 14 in the p-type GaN layer 3 by forming the lower contact electrode 16 with these metal materials. 16 can be in good ohmic contact with the p-type GaN layer 3.

  The upper contact electrode 17 is made of a material having resistance to dry etching, more specifically, a material that is difficult to be etched by dry etching (low etching rate), for example, a metal material such as Au. If the upper contact electrode 17 is made of these metal materials, the upper contact electrode 17 automatically stops etching (etching stop) when the contact hole 14 is formed by dry etching in the manufacturing process described later. In addition, the contact electrode 15 (upper contact electrode 17) can be prevented from being eroded by dry etching.

  In this embodiment, the source electrode 11 fills the contact hole 14 from the middle of the thickness of the n-type GaN layer 4 and further covers the edge of the contact hole 14 on the upper surface of the n-type GaN layer 4. Is provided. Thereby, the bottom surface of the source electrode 11 is joined to the upper surface of the upper contact electrode 17, and the source electrode 11 and the contact electrode 15 (upper contact electrode 17) are electrically connected (short-circuited) to each other. . The source electrode 11 is bonded to the upper surface of the n-type GaN layer 4, and the source electrode 11 and the n-type GaN layer 4 are electrically connected (ohmic contact) with each other.

  In the nitride semiconductor multilayer structure portion 1, a region excluding a region where the drain electrode 6 is formed on the upper surface of the n-type GaN layer 2 and a region where the source electrode 11 is formed on the upper surface of the n-type GaN layer 4. Gate insulating film 8 is formed in contact with the region excluding. Further, a gate electrode 9 is formed on the gate insulating film 8 so as to face the region 10 with the gate insulating film 8 interposed therebetween.

The nitride semiconductor multilayer structure portion 1 is formed on a substrate 12 by, for example, so-called MOCVD growth (Metal Oxide Chemical Vapor Deposition).
For example, when the substrate 12 having a c-plane (0001) as the main surface is used, the nitride semiconductor multilayer structure 1 grown on the substrate 12 by epitaxial growth, that is, the n-type GaN layer 2, the p-type GaN layer 3, and The n-type GaN layer 4 is also laminated with the c-plane (0001) as the main surface. The plane orientation of the wall surface 7 of the nitride semiconductor multilayer structure portion 1 having a trapezoidal cross section (mesa shape) is, for example, a plane inclined in a range of 15 ° to 90 ° with respect to the c plane (0001) (other than the c plane) Surface). More specifically, for example, it becomes a semipolar surface such as (10-13), (10-11), (11-22). In this way, the wall surface 7 is a surface inclined with respect to the c-plane (0001), that is, a surface that obliquely intersects the polarization direction, whereby the interface between the p-type GaN layer 3 and the gate insulating film 8 is obtained. It is possible to suppress generation of extra polarization charges due to natural polarization of the p-type GaN layer 3 in the vicinity.

The gate insulating film 8 can be configured using, for example, an oxide or a nitride. More specifically, it may be configured using silicon oxide (SiO ₂ ), gallium oxide (Ga ₂ O ₃ ), magnesium oxide (MgO), scandium oxide (Sc ₂ O ₃ ), silicon nitride (SiN), or the like. In particular, it is preferable to use silicon oxide (SiO ₂ ), gallium oxide (Ga ₂ O ₃ ), or both.

  Examples of the gate electrode 9 include platinum (Pt), aluminum (Al), nickel-gold alloy (Ni-Au alloy), nickel-titanium-gold alloy (Ni-Ti-Au alloy), palladium-gold alloy (Pd). -Au alloy), palladium-titanium-gold alloy (Pd-Ti-Au alloy), palladium-platinum-gold alloy (Pd-Pt-Au alloy), and a conductive material such as polysilicon can be applied.

  The drain electrode 6 is preferably made of a metal containing at least Al. For example, the drain electrode 6 can be made of a Ti—Al alloy. Similarly to the drain electrode 6, the source electrode 11 is preferably made of a metal containing Al, and can be made of, for example, a Ti—Al alloy. By configuring the drain electrode 6 and the source electrode 11 with a metal containing Al, good contact with a wiring layer (not shown) can be obtained. In addition, the drain electrode 6 and the source electrode 11 may be Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide) as long as they can form ohmic junctions with the n-type GaN layers 2 and 4. ), Or W or a W compound (for example, tungsten silicide).

Next, the operation of the field effect transistor will be described.
A bias voltage that is positive on the drain electrode 6 side is applied between the source electrode 11 and the drain electrode 6. As a result, a reverse voltage is applied to the pn junction at the interface between the n-type GaN layer 2 and the p-type GaN layer 3, and as a result, between the n-type GaN layer 4 and the n-type GaN layer 2, that is, the source -The drain is cut off. In this state, when a bias voltage equal to or higher than a predetermined voltage value (gate threshold voltage) that is positive with respect to the region 10 is applied to the gate electrode 9, electrons are induced in the vicinity of the surface of the region 10, and the inversion layer (Channel) is formed. The n-type GaN layer 2 and the n-type GaN layer 4 are electrically connected through the inversion layer.

Thus, conduction between the source and the drain is established. At this time, since the region 10 is made of a p ⁻ type semiconductor having a lower acceptor concentration than the p-type GaN layer 3, electrons can be induced in the region 10 with a lower gate threshold voltage. If the p-type impurity concentration in the region 10 is appropriately determined, the source-drain conducts when an appropriate bias is applied to the gate electrode 9, while the source-drain is not applied when the gate electrode 9 is not biased. Is cut off. That is, a normally-off operation is realized.

2A to 2H are schematic sectional views showing a method of manufacturing the field effect transistor according to the present invention in the order of steps.
When manufacturing this field effect transistor, first, as shown in FIG. 2A, an n-type group III nitride semiconductor and a p-type group III nitride semiconductor are sequentially formed on a substrate 12, for example, by MOCVD growth. Are grown (first layer forming step and second layer forming step). Thus, the n-type GaN layer 2 and the p-type GaN layer 3 are formed on the substrate 12.

  For example, Si may be used as an n-type impurity when growing an n-type group III nitride semiconductor. Further, for example, Mg, C, or the like may be used as a p-type impurity when growing a p-type group III nitride semiconductor. As a growth method for forming the n-type GaN layer 2 and the p-type GaN layer 3, a liquid phase epitaxial growth method (LPE method), a vapor phase epitaxial growth method (VPE method) or a molecular beam epitaxial growth method (MBE method) can be used. Any method may be applied.

Next, as shown in FIG. 2B, a contact electrode 15 is formed on the p-type GaN layer 3 (contact electrode formation step). The contact electrode 15 is formed by a known vapor deposition method such as a resistance heating vapor deposition method or an electron beam vapor deposition method.
For example, the case where the lower contact electrode 16 is made of a Pd—Au alloy and the upper contact electrode 17 is made of Au will be described in more detail. First, the substrate 12 on which the p-type GaN layer 3 is formed includes: It puts in the chamber of a vacuum evaporation system. Next, a metal mask (not shown) having an opening in a region where the contact electrode 15 is to be formed is installed between the substrate 12 and an evaporation source (Pd and Au) placed in a container such as a crucible. The evaporation source (Pd and Au) is heated by a filament or an electron beam, and a shutter provided between the evaporation source and the substrate 12 is opened. Thereby, Pd and Au are vapor-deposited on the p-type GaN layer 3 through the opening of the metal mask, and the lower contact electrode 16 made of a Pd—Au alloy is formed. After the lower contact electrode 16 is formed, only the shutter between the Pd and the substrate 12 is closed, and only Au is deposited on the p-type GaN layer 3 to form the upper contact electrode 17 made of Au. The

  Next, as shown in FIG. 2C, the n-type GaN layer 4 is laminated in a region extending from the p-type GaN layer 3 to the contact electrode 15 (third layer forming step). Formation of n-type GaN layer 4 is performed, for example, by growing an n-type group III nitride semiconductor at a temperature lower than the melting point of contact electrode 15. If the n-type group III nitride semiconductor is grown at such a temperature, it is possible to prevent the contact electrode 15 from being dissolved by the heat generated when the n-type GaN layer 4 is formed.

Examples of a method for growing an n-type group III nitride semiconductor include known growth methods such as a molecular beam epitaxial growth method (MBE method) and a pulse laser deposition method (PLD method). MBE method) is preferred.
As the growth temperature, for example, if the lower contact electrode 16 is a Pd—Au alloy (melting point: about 1060 ° C.) and the upper contact electrode 17 is Au (melting point: about 1060 ° C.), the n-type group III nitride semiconductor is used. Is preferably grown in the range of room temperature to 900 ° C.

  After the n-type GaN layer 4 is formed, as shown in FIG. 2D, nitriding is performed so that the wall surface 7 having a plane orientation inclined in a range of 15 ° to 90 ° with respect to the c-plane (0001) is cut out. The physical semiconductor laminated structure 1 is etched in a stripe shape (wall surface forming step). As a result, a trapezoidal (mesa-shaped) groove 13 extending from the n-type GaN layer 4 through the p-type GaN layer 3 to the middle layer thickness of the n-type GaN layer 2 is formed on the substrate 12. A plurality of nitride semiconductor multilayer structure portions 1 (only two are shown in FIG. 2D) are shaped into stripes, and lead portions 5 formed by extending portions of the n-type GaN layer 2 and the n-type GaN layer 2 are formed. The wall surface 7 composed of the p-type GaN layer 3 and the n-type GaN layer 4 is formed simultaneously.

  The groove 13 can be formed, for example, by dry etching (anisotropic etching) using a chlorine-based gas. Further, if necessary, a wet etching process for improving the wall surface 7 in the groove 13 damaged by the dry etching may be performed. For wet etching, potassium hydroxide (KOH), aqueous ammonia, or the like is preferably used. Thereby, the surface layer of the damaged wall surface 7 is removed, and the damaged wall surface 7 can be obtained. By reducing the damage on the wall surface 7, the crystal state of the region 10 can be kept good, and the interface between the wall surface 7 and the gate insulating film 8 can be made a good interface. Can be reduced. Thereby, the channel resistance can be reduced and the leakage current can be suppressed. Note that a low-damage dry etching process can be applied instead of the wet etching process.

Next, the gate insulating film 8 is formed on the nitride semiconductor multilayer structure portion 1 by, for example, ECR (electron cyclotron resonance) sputtering. When forming the gate insulating film 8 by the ECR sputtering method, first, the substrate 12 on which the nitride semiconductor multilayer structure portion 1 is formed is put into an ECR film forming apparatus, for example, Ar ⁺ plasma having an energy of about 30 eV is generated. Irradiate for a few seconds. By irradiation with this Ar ⁺ plasma, as shown in FIG. 2E, the region near the wall surface 7 in the p-type GaN layer 3 (the semiconductor surface portion of the second layer) is altered and is different from the p-type GaN layer 3. For example, a p ⁻ type semiconductor region 10 having a conductivity characteristic and having a lower acceptor concentration than the p type GaN layer 3 is formed (fourth layer forming step).

  Thereafter, as shown in FIG. 2F, an insulating film 18 (silicon oxide, gallium oxide, etc.) covering the entire surface of the nitride semiconductor multilayer structure portion 1 is formed. Then, after the insulating film 18 is formed, as shown in FIG. 2G, unnecessary portions of the insulating film 18 (portions other than the gate insulating film 8) are removed by etching, whereby the gate insulating film 8 is formed. (Gate insulating film formation process). Further, a contact hole 14 that penetrates the n-type GaN layer 4 and reaches the contact electrode 15 (upper contact electrode 17) is formed from the upper surface of the n-type GaN layer 4 exposed by etching the insulating film 18 (see FIG. Trench formation step).

  The contact hole 14 can be formed by dry etching (anisotropic etching) using a chlorine-based gas, for example, as in the formation of the groove 13. At this time, since the upper contact electrode 17 is made of a material having resistance to dry etching (for example, Au), the dry etching is automatically stopped (etching stopped) at the upper contact electrode 17. Further, the contact electrode 15 (upper contact electrode 17) can be prevented from being eroded by dry etching. In addition, after the dry etching, a wet etching process for improving the inner wall surface of the contact hole 14 damaged by the dry etching may be performed as necessary. By performing a wet etching process and reducing damage to the inner wall surface of the contact hole 14, the source electrode 11 can be satisfactorily brought into ohmic contact with the n-type GaN layer 4.

  Subsequently, the substrate 12 is put into a vacuum deposition apparatus, and an evaporation source (for example, platinum, aluminum, etc.) used as a material for the gate electrode 9, the drain electrode 6 and the source electrode 11 by a method similar to the method for forming the contact electrode 15. ) Is deposited. As a result, as shown in FIG. 2H, the drain electrode 6 so that the gate electrode 9 facing the region 10 across the gate insulating film 8 is in contact with the upper surface of the lead portion 5 (extension portion of the n-type GaN layer 2). Are formed respectively. A source electrode 11 is formed in the contact hole 14 and at the edge of the contact hole 14 on the surface of the n-type GaN layer 4.

Thus, the field effect transistor having the structure shown in FIG. 1 can be obtained.
In the manufacturing method described above, the gate insulating film 8 is formed by the ECR sputtering method. However, the present invention is not limited to the ECR sputtering method, and there is, for example, a forming method in which the gate insulating film 8 is formed by the magnetron sputtering method. Depending on the formation method and formation conditions of the gate insulating film 8, for example, oxygen, which is an n-type impurity, is ion-implanted on the wall surface 7 of the p-type GaN layer 3 when the gate insulating film 8 is formed. Even when the insulating film 8 is formed, the region near the wall surface 7 in the p-type GaN layer 3 is altered. That is, the step of forming the region 10 and the step of forming the gate insulating film 8 are performed in parallel.

Furthermore, the region 10 is formed, for example, from the surface of the n-type GaN layer 2, the p-type GaN layer 3, and the n-type GaN layer 4 after the nitride semiconductor multilayer structure portion 1 shown in FIG. 2D is formed. The GaN layer containing impurities may be formed by epitaxial growth.
In addition to the step of forming the gate insulating film 8, a step of irradiating the region of the wall surface 7 in the p-type GaN layer 3 with plasma or an electron beam, or a step of ion implantation in the region of the wall surface 7 in the p-type GaN layer 3. May be further provided. By these steps, the region near the wall surface 7 in the p-type GaN layer 3 can be altered to form the region 10 made of an n-type semiconductor.

The nitride semiconductor multilayer structure portion 1 only needs to include at least an n-type group III nitride semiconductor layer, a p-type group III nitride semiconductor layer, and an n-type group III nitride semiconductor layer. In addition to the n-type GaN layer 2, the p-type GaN layer 3, and the n-type GaN layer 4, an i-type GaN layer or the like may be formed between the substrate 12 and the n-type GaN layer 2. Good.
In FIG. 1, the region 10 is shown only on the wall surface 7 in the p-type GaN layer 3, but actually, an altered region is also formed on the wall surface 7 in the n-type GaN layer 2 and the n-type GaN layer 4. Has been. However, even if an altered region is formed on the wall surface 7 in the n-type GaN layer 2 or the n-type GaN layer 4, the device effect is not changed, and thus the altered region is omitted in FIG.

Furthermore, each of the plurality of nitride semiconductor multilayer structures 1 formed in a stripe pattern on the substrate 12 forms a unit cell. The gate electrode 9, the drain electrode 6, and the source electrode 11 of the plurality of nitride semiconductor multilayer structures 1 are commonly connected at positions not shown. The drain electrode 6 can be shared between adjacent nitride semiconductor multilayer structures 1.
As described above, according to this embodiment, after the n-type GaN layer 2 and the p-type GaN layer 3 are formed, the contact electrode 15 is formed before the n-type GaN layer 4 is formed. At the stage where the p-type GaN layer 3 is formed, the surface of the p-type GaN layer 3 is not roughened by, for example, erosion caused by dry etching. The p-type GaN layer 3 can be satisfactorily brought into ohmic contact. In particular, in this embodiment, the portion of the contact electrode 15 that contacts the p-type GaN layer 3 is the lower contact electrode 16 made of a material that can form an ohmic junction with the p-type GaN layer 3. The contact electrode 15 (lower contact electrode 16) can be brought into ohmic contact with the p-type GaN layer 3 more satisfactorily.

  In the obtained field effect transistor, the upper contact electrode 17 joined to the lower contact electrode 16 is electrically connected to the source electrode 11 in the contact hole 14. Therefore, by connecting the source electrode 11 to a predetermined reference potential (for example, ground potential), the potential of the p-type GaN layer 3 becomes a predetermined reference potential via the contact electrode 15 connected to the source electrode 11. Become. Thus, since the potential of the p-type GaN layer 3 can be stabilized at a predetermined reference potential, fluctuations in the gate threshold voltage can be suppressed. As a result, leakage current can be prevented from flowing in the field effect transistor due to fluctuations in the gate threshold voltage. That is, the gate threshold voltage controllability can be improved.

  Further, by adopting a structure in which the gate insulating film 8 is formed so as to be in contact with the region 10 formed on the surface exposed to the wall surface 7 in the p-type GaN layer 3, the gate voltage value required for forming the inversion layer is reduced. be able to. As a result, the gate threshold voltage can be lowered and good transistor operation can be performed while the acceptor concentration of the p-type GaN layer 3 is kept high so that reach-through breakdown does not occur, and a good power device can be realized. it can.

  If a p-type nitride semiconductor layer containing In, such as InGaN or AlInGaN, is used instead of the p-type GaN layer 3, the band gap energy of the p-type nitride semiconductor layer can be reduced. The contact resistance of the physical semiconductor layer can be lowered. As a result, the contact electrode 15 (lower contact electrode 16) can be satisfactorily brought into ohmic contact with the p-type nitride semiconductor layer. For example, even if the wet etching process is not performed after the contact hole 14 is formed by dry etching and the inner wall surface of the contact hole 14 is damaged, the inner wall surface of the damaged contact hole 14 is The contact electrode 15 can be in good ohmic contact.

Furthermore, a normally-off operation is possible by controlling the impurity concentration and film thickness of the region 10, and the vertical transistor structure in which the n-type GaN layer 2, the p-type GaN layer 3 and the n-type GaN layer 4 are stacked. It is also possible to realize a field-effect transistor with a high breakdown voltage that can pass a current.
As mentioned above, although embodiment of this invention was described, this invention can also be implemented in another embodiment.

  For example, in the above-described embodiment, the lower contact electrode 16 is a metal having a low contact resistance with respect to the p-type GaN layer 3 (for example, Pd—Au alloy, Pd—Ti—Au alloy, Pd—Pt—Au alloy, Ni— Although it is in ohmic contact with the p-type GaN layer 3 by being composed of an Au alloy or the like, for example, it is composed of a metal other than those exemplified above (for example, Al or the like). The p-type GaN layer 3 can also be brought into ohmic contact by being formed on the p-type GaN layer 3 and then annealed so that the interface with the p-type GaN layer 3 is alloyed.

In the above-described embodiment, the contact electrode 15 is configured by joining the lower contact electrode 16 and the upper contact electrode 17 to each other. For example, the upper contact electrode 17 is not provided, and the p-type is provided. The lower contact electrode 16 having a low contact resistance with respect to the GaN layer 3 alone may be used as the contact electrode 15.
In the above-described embodiment, the contact hole 14 is formed to expose the contact electrode 15 (upper contact electrode 17) covered with the n-type GaN layer 4. However, the n-type GaN layer 4 includes the contact electrode 15 ( In some cases, the contact electrode 15 (upper contact electrode 17) may be exposed when the n-type GaN layer 4 is stacked, since the upper contact electrode 17) may not be stacked regularly. In that case, the contact hole 14 need not be formed separately, and the source electrode 11 may be formed so as to be in contact with the exposed contact electrode 15 (upper contact electrode 17).

In the above-described embodiment, the wall surface 7 is formed so as to be a semipolar surface such as (10-13), (10-11), (11-22), but as shown in FIG. For example, it may be formed to be a nonpolar surface such as an m-plane (10-10) or a-plane (11-20).
In the above-described embodiment, the drain electrode 6 is formed in contact with the surface of the lead portion 5. For example, a conductive substrate is applied as the substrate 12, and the nitride semiconductor of this conductive substrate is used. It may be formed in contact so as to cover the entire surface opposite to the surface on which the laminated structure portion 1 is formed. Further, in the field effect transistor manufacturing process, the substrate 12 is removed by, for example, a laser lift-off method, a CMP (chemical mechanical polishing) process, an etching process, or the like, and the n-type GaN layer 2 exposed by this removal is removed. It may be formed in contact so as to cover the entire surface.

Furthermore, in the above-described embodiment, the source electrode 11 and the drain electrode 6 are formed in contact with the n-type GaN layers (2, 4). However, they are electrically connected to the n-type GaN layers (2, 4). For example, a GaN layer may be further interposed between the source electrode 11 and the drain electrode 6 and each n-type GaN layer (2, 4).
In addition, various design changes can be made within the scope of matters described in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view for explaining a structure of a field effect transistor manufactured by a manufacturing method of the present invention, and shows a first structure. It is an illustration sectional view showing the manufacturing method of the field effect transistor of this invention in order of a process. FIG. 3B is a schematic sectional view showing the method for manufacturing the field effect transistor according to the present invention in the order of steps, and showing a step subsequent to FIG. 2A. FIG. 3B is a schematic cross-sectional view showing the method for manufacturing the field effect transistor according to the present invention in the order of steps, and showing a step subsequent to FIG. 2B. FIG. 2D is a schematic cross-sectional view showing the method of manufacturing the field effect transistor according to the present invention in the order of steps, and showing a step subsequent to FIG. 2C. FIG. 3D is a schematic cross-sectional view showing the method for manufacturing the field effect transistor according to the present invention in the order of steps, and showing a step subsequent to FIG. 2D. FIG. 2D is a schematic cross-sectional view showing the method for manufacturing the field effect transistor according to the present invention in the order of steps, and showing a step subsequent to FIG. 2E. FIG. 2D is an illustrative cross-sectional view showing the method for manufacturing the field effect transistor according to the present invention in the order of steps, and showing a step subsequent to FIG. 2F. It is an illustration sectional view showing the manufacturing method of the field effect transistor of this invention in order of a process, and is a figure showing the next process of Drawing 2G. It is an illustration sectional view for explaining the structure of the field effect transistor manufactured by the manufacturing method of this invention, and is a figure showing the 2nd structure.

Explanation of symbols

2 n-type GaN layer 3 p-type GaN layer 4 n-type GaN layer 7 wall surface 8 gate insulating film 9 gate electrode 10 region 14 contact hole 15 contact electrode 16 lower contact electrode 17 upper contact electrode

Claims (5)

A first layer forming step of forming an n-type first layer made of a group III nitride semiconductor;
A second layer forming step of stacking a second layer containing a p-type impurity made of a group III nitride semiconductor on the first layer;
A p-type contact electrode forming step of forming a p-type contact electrode on the second layer;
And a third layer forming step of stacking an n-type third layer made of a group III nitride semiconductor on the second layer after the p-type contact electrode forming step.   2. The method for manufacturing a nitride semiconductor device according to claim 1, further comprising a contact hole forming step of forming a contact hole penetrating the third layer and reaching the p-type contact electrode after the third layer forming step. . A wall surface forming step of forming a wall surface straddling the first, second and third layers;
A gate insulating film forming step of forming a gate insulating film along the wall surface;
The method for manufacturing a nitride semiconductor device according to claim 1, further comprising: a gate electrode forming step of forming a gate electrode so as to face the second layer with the gate insulating film interposed therebetween. A wall surface forming step of forming a wall surface straddling the first, second and third layers;
A fourth layer forming step of forming a fourth layer having a conduction characteristic different from that of the second layer on the semiconductor surface portion of the second layer exposed by the wall surface forming step;
Forming a gate insulating film so as to be in contact with the fourth layer;
The method for manufacturing a nitride semiconductor device according to claim 1, further comprising: a gate electrode forming step of forming a gate electrode so as to face the fourth layer with the gate insulating film interposed therebetween.   5. The nitride semiconductor according to claim 1, wherein the third layer forming step includes a step of growing an n-type group III nitride semiconductor at a temperature lower than a melting point of the p-type contact electrode. Device manufacturing method.

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