JPS5857745A - Preparation of complementary semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a minute complementary metal oxide semiconductor (CMOS) device by forming isolatedly the epitaxial layers through self-alignment manner in the form of island in such a method as partly including the surface of amorphous dielectric material on the single crystal Si substrate. CONSTITUTION:The thermal oxide film 42 on the n type Si substrate 41 is selectively removed, and the smooth n type single crystal Si 43 is formed over the substrate at 950-1,100 deg.C with a pressure of 80Torr using H2 as the carrier and SiH2Cl2. After the oxide film 44 is formed, the p well 45 is formed selectively by the ordinary method, then the oxide film 46 is newly formed, the n well is then formed, and threshold voltages of these are respectively adjusted. Next, the phosphorus (P) additive poly-Si gate electrode 47 is formed and the n layer 49, p layer 50 are formed by the ion implantation selectively using the resist mask 48. After the appealing, such layers are covered with the phospho-silicate glass (PSG), the Al electrode 52 is provided and the Al-Si alloy is obtained under the H2 atmosphere, thus completing a device. According to this structure, a minute CMOS device can be obtained which remarkably reduces diffusion capacitance and moreover prevents existence of single- and poly-crystal transitional regions.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to p-type channel field effect transistors and all
The present invention relates to a method of manufacturing a complementary semiconductor formed with a channel field effect transistor.

As a complementary semiconductor device, a CMC consisting of an insulated gate using a silicon oxide film as a gel insulator and a field effect transistor is used.
Tary Metal (Jid 8emicondu
ctor) is well known. In the conventional CMO8, a region (so-called well) with a polarity different from the conductivity type of the substrate is provided in a part of a silicon single crystal substrate, and a piJl channel MUiS transistor is provided in either the substrate region or the well region. However, this conventional structure has the following drawbacks: A bipolar transistor is formed parasitically through a well in between. This is because when a surge voltage is applied when power is input, majority carriers are generated and a forward bias is created in the pn junction of the source or drain. This leads to the disadvantage that a phenomenon in which a current flows in the substrate or well (so-called latch-up) is likely to occur.In order to prevent this double-up phenomenon, the distance between the Kp channel transistor and the n-type channel transistor Og formation region is increased. Conventionally, a method has been adopted in which a guard ring layer is provided around each region with a distance of 10 μm or more, but it is not possible to obtain favorable results.There are various reasons for this. This leads to an increase in the chip area of integrated circuits.

The second is that p
Since there are many tm and n-type diffusion regions, the number of parasitic pn junctions increases, which becomes an obstacle to increasing the speed.

S08 is a method to improve these drawbacks of the conventional structure.
(Dan i11con on qapphire) A CMOB using the My board has been proposed. However, epitaxial silicon films grown on such heterogeneous substrates have a high density of defects, and junction leakage due to defects is likely to occur.J), I! tcFi80S
Due to problems such as the rising cost of substrates, they were only used for special purposes.

In order to solve some of these problems, a silicon substrate with a partially formed amorphous dielectric film is used to form a field effect transistor using polycrystalline silicon deposited on the amorphous dielectric film. C as the source/drain region of
The MO8 structure was proposed and arrived at. This is BO-C
MOS (BuriedQxide CMO8)
rnal of Applied Physics) magazine,
Reported in 1979, Vol. 18, pp. 45-50. However, in such conventional so-called HO-CMUS configurations, the silicon deposited on the dielectric surface becomes polycrystalline, making it difficult to use it for the channel region of a transistor or a part thereof, which determines the switching speed. Adashi.

Furthermore, since there is a transition region between the single crystal and polycrystalline silicon, it is necessary to allow for a margin when designing the device, which is a disadvantage in terms of miniaturization of the device.

The present invention is @p'! In a method of manufacturing a complementary semiconductor device formed with an L-channel field effect transistor and an NFI-channel field effect transistor, an amorphous dielectric is partially formed on a single crystal silicon substrate, and four steps are performed to form the amorphous dielectric. a step of depositing at least one layer of epitaxial silicon by controlling the type and concentration of impurities so that the thickness of the dielectric becomes at least 4 thick; a step of forming a gate insulating film on the epitaxial silicon film; * The epitaxial silicon I deposited on the amorphous WWL body includes at least one of the source diffusion region of the pWl channel transistor, the drain diffusion region of the pWl channel transistor, and at least one of the gate regions or the source diffusion region of the nm channel transistor. , drain diffusion plate, and gate region.

The present invention provides a method for manufacturing a complementary semiconductor device characterized by comprising: and t-a.

Below, as a preparation for detailed explanation of the present invention, the conventional B
The O-CMυSTg configuration and the new configuration to be manufactured by the present invention will be explained using the drawings while comparing them. FIG. 1 is a schematic cross-sectional view of a cmos inverter shown to explain the features of a conventional BO-chtos configuration. Normally, 1 is an n-type silicon substrate, 2 is a p-well, 3 is a dielectric @, In the row, silicon oxide film, 4 is epitaxial silicon I! , 5 is the polycrystalline silicon film deposited during epitaxial growth, and 6 is the field oxidation 1lli!
, 7 is a gate oxide film, 8 and 9 are n-type channel MO8
) 10 and 11 are p! polycrystalline silicon for gate and source/drain diffusion regions of transistor, respectively. ! The polycrystalline silicon for the gate and the enlarged fBt region for the source and drain of the channel Pm0S transistor, respectively, 12 is an interlayer insulation wedge, for example, PS u@ by CVD method, and 13 is
An aluminum configuration is often used in which the contact hole is wired over the contact hole.

A characteristic of this conventional configuration is that most of the source and drain of the transistor are connected to the substrate via an oxide film with #S framework, which reduces the junction capacitance and is expected to achieve high-speed operation. be done. However, since the silicon film deposited on the #C1l conductor is polycrystalline, its carrier mobility, which significantly affects the switching characteristics, is small.
It is difficult to use it in the channel region or a part thereof (Fig. 2 is a schematic cross-sectional view showing the characteristic configuration of the present invention in comparison with Fig. 1), and normally 101
II! I silicon substrate, 102 is p-well, 103 is amorphous dielectric, 91 is silicon oxide film, 104 is epitaxial silicon@, tOS is gate oxide IK,
106 and 107 are the gate polycrystalline silicon and source/drain diffusion regions of the n-type channel MO8 transistor, and 108 and 109 are the pII channel MO8 transistors.
110 is the polycrystalline silicon for the gate and the source/train diffusion region of each transistor, and 110 is the interlayer insulation 1[
, 111 is Al(=Kum).The feature here is that epitaxial silicon is deposited on the dielectric 103, and the epitaxial silicon is deposited thicker than the thickness of the dielectric 103. As a result, a single crystal silicon film is formed a certain distance from the dielectric edge.

6 - This distance depends on the difference between the epitaxial silicon film thickness and the frame thickness and the orientation of the substrate used. By setting the thickness of the epitaxial silicon layer and the medium dimensions of the dielectric, there is an advantage that a selective epitaxial silicon substrate can be deposited at any location in the island shape shown in FIG. 92 without a mask 9 alignment step.

Such selective epitaxial growth 1j is mainly carried out using dichlorosilane (a gas containing salt atoms such as silicon chloride) and hydrogen as a carrier gas, and hydrogen chloride produced by a thermal decomposition reaction is used as a carrier gas for silicon. It was possible to put this into practical use for the first time by making use of the tragic phenomenon discovered by the present inventors that contributes to etching.Currently, it is possible to put this into practical use for the first time on a substrate where single crystal silicon and amorphous #electronic material coexist. When a silicon layer is deposited using the above reaction, it begins to grow as a semi-crystal on monocrystalline silicon and as a polycrystal on an amorphous dielectric. The etching rate of the polycrystalline silicon formed on the polycrystalline silicon exceeds the deposition rate], whereas the etching rate on the polycrystalline silicon is lower than the deposition rate, so the monocrystalline silicon is deposited not only on the single crystal. Then, a single crystal layer grows in one direction on the amorphous 5ILC body using this single crystal silicon as a vertebral crystal.Such selective epitaxial growth is performed on single crystal silicon. When carried out on a substrate provided with an amorphous dielectric, the single crystal silicon layer first fills the holes in the amorphous dielectric layer, and then increases its layer thickness, extending in the co-lateral direction and forming the amorphous dielectric. Of course, such growth is possible even if the single crystal silicon surface and the amorphous dielectric surface are aligned on the same plane at the starting point. Furthermore, it is possible to separate and form epitaxial silicon into islands in a self-aligned manner so as to include a portion of the amorphous #electrode surface.

In addition, O epitaxial silicon II on amorphous S electric body
Since not only the K source/drain region but also the channel region or a part thereof is formed, the junction area of the source/F° drain region is smaller compared to the conventional BO--0MO8. Furthermore, there is no transition region between monocrystalline silicon and polycrystalline silicon.

Obtaining the advantage of simultaneously achieving miniaturization of elements. Next, embodiments of the present invention will be described in detail with reference to the drawings. Figure #I3 shows the manufacturing process of a CMOS inverter circuit to realize the present invention in accordance with the request, in which approximately 5000A4f oxide 1[42] is formed on an I mW silicon substrate 41 by a thermal oxidation method, and then 1 is processed using normal photo-etching technology. Then, the silicon oxide film in the region to be the gate region of the transistor is removed by etching.

After sonication, dichlorosilane (8iH, CI,) was used as a source gas.

A volume of water is introduced into the reaction system as a carrier gas, and 80 to
When silicon is epitaxially grown by thermal decomposition under the reduced pressure of rrf1MK at a substrate temperature of 950°C to 1100°C, the single crystal silicon of nfJIl becomes smooth to include the silicon substrate surface and a part of the oxide film 42.
3 can be deposited to obtain -11311(a).

In this case, the difference between the epitaxial silicon WI thickness and the oxide film thickness is determined by the oxidation I [when half of the pattern size of the formation area is about the same, the silicon on the oxide film is connected from both sides in a monophonic state, and the oxide film The region is filled. After forming the oxide I[44], impurities are controlled and introduced into the 0*** area only in the area where the j%Il type channel transistor is to be formed by means such as ordinary photolithography and ion implantation. After heat treatment, the Pg well i! has the desired S degree due to ion implantation. ii 4S is formed, its vk and oxide 8I 44 are removed, and a gate oxide 1[46 is formed again using a thermal dipping method, and the threshold voltages of both n-channel and p-channel transistors are adjusted by ion implantation. Adjust the value to the desired value,
To obtain Figure 3(b), polycrystalline silicon 47 doped with an impurity such as phosphorus that causes n-type conductivity is deposited by, for example, CVD, and then photolithographic and etching techniques are used. When the polycrystalline silicon 47 is etched to form the gate electrode of the transistor, Figure 183 (C)
The 0-order p-type channel transistor forming region is covered with a resist 48, and using the resist as a mask, impurities that produce n-type conductivity such as arsenic or phosphorus are ion-implanted at a dose of 10 cm or more to form an n5 channel transistor. A source/drain m region 49 is formed, as shown in FIG. 3(d).
get. Sixth, when the substrate temperature rises to about 300 degrees Celsius during ion implantation, it is convenient to use a cyclized butadiene resist with strong heat resistance for the resist Fi used as an ion implantation mask.Subsequently, n-type channel transistor formation S
Similarly, the t-hole is covered with a resist 48, and using the resist as an ion implantation mask, an impurity such as boron that causes p-type thickness IE characteristics is implanted at a dose of about 10 cm.
Figure 3(e) is obtained by forming the source/drain mV50 type channel transistor. After recovering the damage caused by ion implantation by performing appropriate heat treatment, PSG! is used as an interlayer insulating film. [51 is deposited, for example, by the CVD method, and the surface is smoothed by XfL.Next, the contact hole pattern f? , ! (FIG. 3(f) is a finished view of the structure according to the present invention, in which the conductive IC material, e.g., aluminum 52, is broken and the patterned electrode is patterned.) Then, if necessary, deposit a protective film using the CVD method, and remove the protective film on the electrode pad (using photolithography and etching methods).The transistor characteristics of the thus obtained transistor of the present invention are extremely good. For example, when the drain voltage is 5, the drain leakage current is less than 10/-! 1 channel ML) 8
) As explained above, according to the configuration of the present invention, the drain diffusion region to which voltage is applied is dielectrically separated from the substrate and the channel stopper diffusion region, which is the same as in the conventional configuration. It is possible to achieve high speeds that could not be achieved with conventional CMOf9) transistors using silicon substrates.
It has become clear that it is possible to achieve high reliability and low cost that could not be achieved with 08 transistors, and also brings the advantage that miniaturization and high integration can be easily achieved. As stated in the range (
Crystalline silicon deposited on an amorphous dielectric:
It can also be used for the source/drain 784 (Dlh) region and the source/drain 784 (Dlh shift), and is not limited to the implementation shown as a column in Figure 3.

Although the above embodiments have been described using a silicon oxide film as the amorphous dielectric, a silicon nitride film, P 8 G, etc. may also be used, and the crystallinity of the epitaxial silicon grown thereon may vary. It was equally effective when looking at the effect of ・r! jlArtno easy txta
q FIG. 1 is a schematic IIfr of a conventional polycrystalline silicon gate type CMOS inverter showing a row of 30 MO8 structures.
In the top view, FIG. 2 is a schematic diagram showing the structure of the present invention in comparison with FIG. 1! ? The numbers in Figure 1, which is a front view, are 1.101-
7 Rico 7jk board, 2,102-p type Riel, 3.103
... Amorphous 'iIt dielectric film, 4,104 - epitaxial silicon film, 5 - Polycrystalline silicon, 6...
Field oxide film, 7,105-...Goo) # conversion film, 8
．． 106-1111 Channel transistor gate polycrystalline silicon, 9,107-...N-noodle channel transistor north drain dispersion region, 10,108-pa!
! Channel transistor gate polycrystalline silicon, 11
, 109-pfjl channel transistor source/drain diffusion region, 12, 110 interlayer insulating film, 13.1
11-.Aluminum wiring is shown, respectively.

Figure 3 shows the manufacturing process for realizing the present invention at step A11.
This is a cross-sectional view showing VC, and the numbers in the figure are.

41-Silicon substrate, 42-Amorphous spindle, crystalline silicon, 48-Resist serving as ion implantation mask, 49-.
source drain region of n-type channel transistor, 50
- source/drain regions of p-type channel transistors;
An interlayer insulating film 51 and a metal wiring 51 are shown, respectively.

Figure l Figure 3

Claims (1)

[Claims] A method for manufacturing a complementary m-semiconductor device in which a 2m-channel field effect transistor and an n-type channel field-effect transistor are formed side by side, in which an amorphous n-frame is partially formed on a single-crystal crystalline substrate. The general process is to deposit at least 4 or more layers of epitaxial silicon with the type and concentration of impurities set to ltllmL so that the film thickness is at least thicker than the amorphous 'lK# region body, 1! * Step 11 of forming a gate insulating layer on the epimexial silicon layer Depositing the gate insulating layer on the amorphous wax body
Source diffusion of fine channel transistors, drain expansion l&region. At least one of the gate regions is Fi above mW.
A process for providing at least one of the following: channel transistor O source diffusion region, drain diffusion region, and gate region.
! , and a method for manufacturing a complementary semiconductor device.