JPH0332028A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0332028A JPH0332028A JP16744989A JP16744989A JPH0332028A JP H0332028 A JPH0332028 A JP H0332028A JP 16744989 A JP16744989 A JP 16744989A JP 16744989 A JP16744989 A JP 16744989A JP H0332028 A JPH0332028 A JP H0332028A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- layer
- collector
- electrode
- base region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 238000005516 engineering process Methods 0.000 claims description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 238000002347 injection Methods 0.000 abstract description 4
- 239000007924 injection Substances 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 35
- 238000009792 diffusion process Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- XUKUURHRXDUEBC-KAYWLYCHSA-N Atorvastatin Chemical compound C=1C=CC=CC=1C1=C(C=2C=CC(F)=CC=2)N(CC[C@@H](O)C[C@@H](O)CC(O)=O)C(C(C)C)=C1C(=O)NC1=CC=CC=C1 XUKUURHRXDUEBC-KAYWLYCHSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体集積回路装置に関し、特にバイポーラ
型トランジスタ装置において、従来のブレーナ技術に加
えてＳ ＯＩ （Ｓｉｌｉｃｏｎ ｏｎ Ｉｎ５ｕｌ
ａｔｏｒ）技術を適用した改良トランジスタに関するも
のである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular to a bipolar transistor device, in addition to the conventional brainer technology, it is possible to
This invention relates to an improved transistor to which the ator technology is applied.
従来例によるバイポーラ型ｎｐｎ）ランジスタの概要構
成を第２図に示す、第２図において、１はＰ−型半導体
基板、２ａはＰ型半導体集積回路基板ｌ上に形成された
ｎ゛型埋込み層、２ｂは同コレクタウオール層、３はｎ
０埋め込み層２ａ上に形成されたれ一エピタキシャル層
、４は素子分離用のフィールド酸化膜、５はチャネルカ
ット用のＰ型拡散層である。また６ａはｎ−型エピタキ
シャル層３上に形成されたＰ型ベース拡散層における真
性ベース領域、６ｂは同外部ベース領域であり、さらに
７はｎ゛型エミッタ層、８は眉間絶縁膜、９はシリサイ
ド部、１０はベース電極、１１はエミッタ電極、１２は
コレクタ電極、１３は各電極下のバリアメタル層である
。A schematic structure of a conventional bipolar type npn) transistor is shown in FIG. 2. In FIG. 2, 1 is a P-type semiconductor substrate, and 2a is an n-type buried layer formed on a P-type semiconductor integrated circuit substrate l. , 2b is the collector all layer, 3 is n
0 is an epitaxial layer formed on the buried layer 2a, 4 is a field oxide film for element isolation, and 5 is a P-type diffusion layer for channel cut. Further, 6a is the intrinsic base region of the P-type base diffusion layer formed on the n-type epitaxial layer 3, 6b is the extrinsic base region, 7 is the n-type emitter layer, 8 is the glabella insulating film, and 9 is the In the silicide part, 10 is a base electrode, 11 is an emitter electrode, 12 is a collector electrode, and 13 is a barrier metal layer under each electrode.
次に製造方法について説明する。Next, the manufacturing method will be explained.
Ｐ−型半導体基′ｕｉｌ上にＮ型埋め込みＪｉ２ａを形
成し、この上にエピタキシャル層３を成長させる。An N-type buried Ji2a is formed on the P-type semiconductor substrate 'ui1, and an epitaxial layer 3 is grown thereon.
次に素子を分離するためにシリコンエッチをし、チャネ
ルカット層５を形成した後、厚い酸化膜４を形成する。Next, silicon is etched to separate the elements, and after forming a channel cut layer 5, a thick oxide film 4 is formed.
そして、Ｎ型のコレクタウオール層２ｂ、真性ベース領
域６ａ、外部ベース領域６ｂをそれぞれＰ“ （リン）
、Ｂ”（ボロン）、Ｂ゛のイオン注入により形成する。Then, the N-type collector all layer 2b, the intrinsic base region 6a, and the extrinsic base region 6b are each made of P" (phosphorus).
, B'' (boron), and B'' are formed by ion implantation.
さらに眉間膜をデポジションし、エミッタ、コレクタ、
ベースのコンタクトを開孔した後、ベースをカバーし、
Ａｓ” （砒素）の注入によってエミッタ拡散層７を
形成する。Furthermore, the glabellar membrane is deposited, emitter, collector,
After drilling the base contact, cover the base,
An emitter diffusion layer 7 is formed by implanting As'' (arsenic).
その後コンタクト部を選択的にシリサイド９化し、バリ
アメタル１３．Ａｌ配線によりベース電極１０．エミッ
タ電極１１．コレクタ電極１２を形成する。Thereafter, the contact portion is selectively silicided 9, and the barrier metal 13. Base electrode 10. by Al wiring. Emitter electrode 11. A collector electrode 12 is formed.
従来の半導体集積回路装置は、以上のように構成されて
いるので、コレクタウオール層２ｂおよび外部ベース領
域６ｂ、それぞれの面積、および両者間の距離は大きく
、またｎ゛型埋込Ｎ２ａの面積も大きく、このようにト
ランジスタ動作としては不要な領域を削減することがで
きず、コレクタベース間接合容Ｉｅｔｃ、およびコレク
タ基板間接合容量ＣＴ！が大きくなり、トランジスタの
高速動作に必要な容量低減ができないなどの問題点があ
った。Since the conventional semiconductor integrated circuit device is configured as described above, the areas of the collector all layer 2b and the external base region 6b, and the distance between them are large, and the area of the n-type buried N2a is also large. In this way, it is not possible to reduce the area that is unnecessary for transistor operation, and the collector-base junction capacitance Ietc and the collector-substrate junction capacitance CT! There were problems such as the capacitance required for high-speed operation of the transistor could not be reduced.
この発明は上記の様な問題点を解消するためになされた
もので、トランジスタの寄生接合容量を低減することに
より、高速動作を可能としたバイポーラ型半導体集積回
路装置を得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a bipolar semiconductor integrated circuit device that enables high-speed operation by reducing the parasitic junction capacitance of transistors.
この発明に係る半導体集積回路装置は、半導体基板上に
アイソブレーナ技術によりバイポーラ型トランジスタを
形成する半導体集積回路装置において、上記従来のプレ
ーナ技術に加え、５ｏｌ（Ｓｉｌｉｃｏｎ ｏｎ Ｉｎ
５ｕｌａｔｏｒ）技術を用いて高エネルギー酸素注入を
行い、トランジスタの不要領域を酸化膜にしたものであ
る。A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device in which bipolar transistors are formed on a semiconductor substrate by isoplanar technology, in addition to the conventional planar technology described above.
High-energy oxygen implantation is performed using the 5ulator technology to form an oxide film in unnecessary areas of the transistor.
この発明における半導体集積回路装置は、高エネルギー
酸素注入により形威される酸化膜を利用することにより
、トランジスタの不要領域を酸化膜にして、トランジス
タの寄生接合容量を低減することができる。The semiconductor integrated circuit device according to the present invention uses an oxide film formed by high-energy oxygen implantation, so that unnecessary regions of the transistor can be made into an oxide film, thereby reducing the parasitic junction capacitance of the transistor.
以下、この発明の一実施例を図を用いて説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図において、１はＰ−型半導体基板、２ａはＰ−型
半導体基Ｆｉｌ上に形威されたｎ゛型埋込層、２ｂは同
コレクタウオール層、３はｎ９型埋込１ｉ２ａ上に形威
されたｎ−型エピタキシャル層、４は素子分離用のフィ
ールド酸化膜、１４は高エネルギー（ＭｅＶ）酸素注入
により形威された酸化膜、５はチャネルカット用のＰ型
拡散層、６ａはｎ−型エピタキシャル層３上に形成され
たＰ型ベース拡散層における真性ベース領域、６ｂは同
外部ベース領域であり、さらに７はｎ０型エミッタ層、
８は眉間絶縁膜、９はシリサイド部、１０はベース電極
、１１はエミッタ電極、１２はコレクタ電極、１３は各
電極下のバリアメタル層である。In FIG. 1, 1 is a P-type semiconductor substrate, 2a is an n-type buried layer formed on the P-type semiconductor base Fil, 2b is the same collector all layer, and 3 is an n9-type buried layer formed on the n9-type semiconductor substrate 1i2a. A shaped n-type epitaxial layer, 4 a field oxide film for element isolation, 14 an oxide film shaped by high-energy (MeV) oxygen implantation, 5 a P-type diffusion layer for channel cut, 6a a An intrinsic base region 6b is an extrinsic base region in the P-type base diffusion layer formed on the n-type epitaxial layer 3, and 7 is an n0-type emitter layer.
8 is an insulating film between the eyebrows, 9 is a silicide part, 10 is a base electrode, 11 is an emitter electrode, 12 is a collector electrode, and 13 is a barrier metal layer under each electrode.
次に本実施例の製造方法について説明する。Next, the manufacturing method of this example will be explained.
上記従来装置の製造方法と同様に、Ｐ型半導体基板１上
にＮ型埋め込み層２ａ及び後のチャネルカット層５を形
威し、この上にエピタキシャル層３を成長させる。Similar to the method for manufacturing the conventional device described above, an N-type buried layer 2a and a later channel cut layer 5 are formed on a P-type semiconductor substrate 1, and an epitaxial layer 3 is grown thereon.
次に、マスク（例えばＳｉｇｈマスク）をかけて高エネ
ルギー（ＭｅＶ）酸素注入を行い、熱処理をして厚い酸
化膜１４を形成する。Next, high energy (MeV) oxygen is implanted using a mask (for example, a high mask), and heat treatment is performed to form a thick oxide film 14.
そして、窒化膜をマスクにしてフィールド酸化を行い、
薄い酸化膜４を形威する。Then, field oxidation is performed using the nitride film as a mask.
A thin oxide film 4 is formed.
さらに、コレクタウオール１ｉ２ｂ、真性ベース領域６
ａ、外部ベース領域６ｂをそれぞれＰ’ （リン＞、
Ｂ”、Ｂ”のイオン注入により形威し、層間膜をデポジ
ションし、エミッタ、コレクタ。In addition, collector all 1i2b, intrinsic base region 6
a, external base region 6b, respectively P'(phosphorus>,
The shape is formed by ion implantation of B'' and B'', and an interlayer film is deposited to form the emitter and collector.
ベースのコンタクトを開孔した後、ベースをカバーし、
Ａｓ” （砒素）の注入によって工果ツタ拡散７Ｉｉ
７を形成する。After drilling the base contact, cover the base,
Artificial ivy diffusion 7Ii by injection of As” (arsenic)
form 7.
その後コンタクト部を選択的にシリサイド９化し、バリ
アメタル１３．Ａｌ配線により、ベース電極１０．エミ
ッタ電極１１． コレクタ電極１２を形成する。Thereafter, the contact portion is selectively silicided 9, and the barrier metal 13. Base electrode 10. Emitter electrode 11. A collector electrode 12 is formed.
本実施例の半導体集積回路装置は以上の様に構成されて
おり、第１図に示す様に、外部ベース領域６ｂの周囲は
ほぼ、高エネルギー酸素注入により形成した酸化膜１４
により覆われている。従って、コレクタベース間接合容
ｆ Ｃｒ ｃを低減でき、またｎ゛型埋込層２ａの面積
も小さくなり、コレクタ基板間接合容量ＣｔＸをも低減
することができる。The semiconductor integrated circuit device of this embodiment is constructed as described above, and as shown in FIG.
covered by. Therefore, the collector-base junction capacitance f Cr c can be reduced, and the area of the n-type buried layer 2a can also be reduced, so that the collector-substrate junction capacitance CtX can also be reduced.
以上の様に、この発明によれば、従来のプレーナ技術に
加え、ＳＯ■技術を用いて高エネルギー酸素注入を行い
、トランジスタの不要領域に酸化膜を形成することによ
り、該不要領域を削減するようにしたので、コレクタベ
ース間容量及びコレクタベース間容量を低減することが
でき、高速動作が可能なバイポーラ型半導体集積回路装
置が得られるという効果がある。As described above, according to the present invention, in addition to conventional planar technology, high-energy oxygen implantation is performed using SO technology to form an oxide film in unnecessary areas of transistors, thereby reducing the unnecessary areas. As a result, the collector-base capacitance and the collector-base capacitance can be reduced, and a bipolar semiconductor integrated circuit device capable of high-speed operation can be obtained.
第１図はこの発明の一実施例によるバイポーラ型半導体
集積回路装置を示す断面図、第２図は従来のバイポーラ
型半導体集積回路装置を示す断面図である。
１・・・Ｐ−半導体基板、２ａ・・・ｎ゛型埋込層、２
ｂ・・・コレクタウオール層、３・・・ｎ−型エピタキ
シャル層、４・・・フィールド酸化膜、５・・・チャネ
ルカット用Ｐ型拡散層、６ａ・・・真性ベース領域とな
るＰ型拡散層、６ｂ・・・外部ベース領域となるＰ型拡
散層、７・・・ｎ＋型エミッタ層、８・・・層間絶縁膜
、９・・・シリサイド、１０・・・ベース電極、１１・
・・エミッタ電極、１２・・・コレクタ電極、１３・・
・バリアメタル層、１４・・・高エネルギー酸素注入に
より形成された酸化膜。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a sectional view showing a bipolar type semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional bipolar type semiconductor integrated circuit device. 1...P-semiconductor substrate, 2a...n-type buried layer, 2
b...Collector all layer, 3...N-type epitaxial layer, 4...Field oxide film, 5...P-type diffusion layer for channel cut, 6a...P-type diffusion that becomes the intrinsic base region Layer, 6b... P type diffusion layer serving as external base region, 7... N+ type emitter layer, 8... Interlayer insulating film, 9... Silicide, 10... Base electrode, 11...
...Emitter electrode, 12...Collector electrode, 13...
- Barrier metal layer, 14...An oxide film formed by high-energy oxygen implantation. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
ーラ型トランジスタを形成してなる半導体集積回路装置
において、 トランジスタ素子を分離する酸化膜の一部に、高エネル
ギー酸素注入により形成した酸化膜を用いたことを特徴
とする半導体集積回路装置。(1) In a semiconductor integrated circuit device in which bipolar transistors are formed on a semiconductor substrate using isoplanar technology, an oxide film formed by high-energy oxygen implantation is used as part of the oxide film that separates transistor elements. A semiconductor integrated circuit device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16744989A JPH0332028A (en) | 1989-06-29 | 1989-06-29 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16744989A JPH0332028A (en) | 1989-06-29 | 1989-06-29 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0332028A true JPH0332028A (en) | 1991-02-12 |
Family
ID=15849907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16744989A Pending JPH0332028A (en) | 1989-06-29 | 1989-06-29 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0332028A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5654063A (en) * | 1979-10-08 | 1981-05-13 | Mitsubishi Electric Corp | Semiconductor device |
| JPS61296767A (en) * | 1985-06-26 | 1986-12-27 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6224670A (en) * | 1985-01-30 | 1987-02-02 | テキサス インスツルメンツ インコ−ポレイテツド | Bipolar transistor and making thereof |
-
1989
- 1989-06-29 JP JP16744989A patent/JPH0332028A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5654063A (en) * | 1979-10-08 | 1981-05-13 | Mitsubishi Electric Corp | Semiconductor device |
| JPS6224670A (en) * | 1985-01-30 | 1987-02-02 | テキサス インスツルメンツ インコ−ポレイテツド | Bipolar transistor and making thereof |
| JPS61296767A (en) * | 1985-06-26 | 1986-12-27 | Fujitsu Ltd | Manufacture of semiconductor device |
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