JPH01241164A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To obtain vertical PNP transistors of high performance and high quality which are almost free from dispersion on the quality of products, by forming a P<+> type buried layer as the collector layer of the vertical PNP transistor independently of an N<+> type buried layer. CONSTITUTION:After forming an N<+> type buried layer 22 on the surface part of a P-type semiconductor substrate 21, the first epitaxial layer 23 is formed on the substrate 21. A P<+> type buried layer 26a as a collector layer as well as a P<+> type buried isolation layer 26b for isolation are formed and the second epitaxial layer 27 is formed on the first epitaxial layer. In this way, the P<+> type buried layer 26a which acts as the collector layer of a vertical PNP transistor is formed independently of the N<+> type buried layer 22. Thus, high performance and high-grade vertical PNP transistors which are almost free from dispersion on the quality of products are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application!l!?) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a vertical PNP transistor.

(Prior Art) FIG. 3 is a process sectional view showing a conventional method for manufacturing a vertical PNP transistor.

First, as shown in Figure 3+8), the specific resistance is 10 to 40Ω.
An oxide film 2 with a thickness of about 1 μm is formed on a P-type semiconductor substrate 1 with a thickness of 1 μm.
After forming, an N+ buried layer pattern 3 is formed in the oxide film 2 by a known photolithography technique, and then antimony is diffused to form a junction depth of 2 to 5 μm and a sheet resistance 10.
An N+ buried layer 4 having a resistance of 0 to 20 Ω/hole is formed on a P-type semiconductor substrate 1.

Next, after removing the oxide film 2, as shown in FIG. A bi-buried layer pattern 6a and a bi-buried isolation pattern 6b are formed using a resist 6 as a resist-removed portion.Then, boron is implanted using an ion implantation method at an energy of 60 keV and a dose of 1.
~5X10cI11 implant, 100 after removing resist 6
By performing N2 annealing at 0° C., a Bi buried layer 7a is formed in the N++ buried layer 4, and a P+ buried isolation layer 7b is formed in the substrate region surrounding the N+ buried layer 4.

Next, after removing the oxide film 5, as shown in FIG.
A phosphorus-doped N-type epitaxial layer 8 having a specific resistance of 2 to 2.5 Ω·cm and a thickness of 3 to 4 μm is formed on the substrate 1. Subsequently, after performing oxidation and patterning to form a collector lead-out pattern 10a and a separation pattern 10b on the oxide film 9 on the epitaxial layer 8, boron is diffused using a vapor phase diffusion method or the like. Then, the isolation diffusion layer 11b and the collector extraction layer 11a of the PNP transistor are formed so as to reach the bi-buried isolation fi7b and the bi-buried layer 7a. At this time, the P'' buried layer 7a and the P''
1. The boron used in the buried isolation layer 7b has a larger diffusion coefficient than the antimony used in the N++ buried layer 4, for example, 1.
In separation diffusion at 100℃, the diffusion coefficient of boron is 2×10
cxl/ s e c 1 That of antimony is I X
10-14 aj/sec, therefore, during epitaxial growth or isolation diffusion, the P+ buried layer 7a is diffused upwards by the N+ layer R4 to form the collector layer of the PNP transistor. At the same time, the Bi-embedded portion l/l@7b also diffuses upward, which has the effect of shortening the separation and diffusion.

Next, as shown in FIG. 3(d), P
+N1 diffusion N13 for diffusion layer 12 and base electrode extraction
are formed in the epitaxial layer 8 on the P1 buried layer 7a to complete a vertical PNP transistor. Thereafter, an oxide film 14 is formed on the epitaxial layer 8, a contact hole 15 is opened, and wiring (not shown) is formed.

FIG. 4 shows an example of the impurity concentration distribution in the epitaxial layer and the buried layer portion (PNP transistor forming portion) in such a conventional manufacturing method.

Bipolar semiconductors that require PNP transistors
In general, in Mi circuits, NPN transistors are often formed at the same time, and in order to lower the ON resistance of the transistors, the N++-containing layer 4 is formed by antimony diffusion with a thickness of 10" am-3 or more, as shown in Figure 4. The N++ buried layer 4 also has the function of electrically separating the P+ buried layer 7a, which becomes the collector layer of the PNP transistor, from the P type semiconductor substrate 1. From this point of view as well, it is necessary to increase the concentration.

(Issues to be Solved by the Inventionffj)However, when the N+ buried rf!I4 is made to have a high concentration as described above, in the above conventional manufacturing method, the collector layer of the PNP transistor is formed in the N++ buried layer 4. Since the P+ buried layer 7a is formed, the P+ buried layer 7a is also
As shown in the figure, it is necessary to form a boron diffusion with a high concentration of 10 "am-' or more. If the P+ buried layer 7
If a is made to have a low concentration, it will be compensated by the high concentration N++-containing layer 4, and there will be a problem that the sheet resistance will increase or a P+ layer will not be formed. However, when both the N+ buried Fi4 and the P+ buried layer 7a are formed at high concentrations, P
There is a problem in that the collector capacitance of the NP transistor becomes large and the operating speed of the transistor decreases. In addition, since the N1 buried layer 4 and the P+ buried layer 7m are formed by double diffusion, the conventional method has the problem of easily inducing crystal defects and deteriorating breakdown voltage. Since the buried layer 7a has a high concentration and it is difficult to control the amount of upward diffusion, it is difficult to control the base width, and it is difficult to control the breakdown voltage and current amplification factor (hpε).

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device, which solves the above-mentioned problems and makes it possible to obtain a high-performance, high-quality vertical PNP transistor with little manufacturing variation.

(Means for Solving the Problems) The present invention provides a method for manufacturing a vertical PNP transistor, in which an N++-containing layer is formed on the surface of a P-type semiconductor substrate, and then a first epitaxial layer is formed on the substrate. A P" buried layer as a collector layer and a Bi buried separation layer for isolation are formed in the first epitaxial layer, and a second epitaxial layer is formed on the first epitaxial layer.

(Function) In the above manufacturing method, vertical PNP
) The P+ buried layer as the collector layer of the transistor is N+
It becomes possible to form independently from the +-containing layer.

(Embodiment) An embodiment of the present invention will be described above with reference to the drawings. FIG. 1 (al~(, 1 is a process sectional view showing an embodiment of the present invention.

First, as in the conventional example, as shown in FIG.
After forming the ++-containing layer 22, a phosphorus-doped N-type first epitaxial layer 23 having a resistivity of 2 to 2.5 Ω·m and a thickness of 1 to 2 μm is formed on the substrate 21 as shown in the figure.

Next, as shown in FIG.
After forming a thin oxide film 24 with a thickness of 500 to 1000 on the surface of the oxide film 24, a P buried layer pattern 25a and a P+ buried layer pattern 25b are formed using a resist 25.
is formed as the resist removed portion. After that, using the resist 25 as a mask, the pattern 25a of the resist removed portion is
, 25b by ion implantation with an energy of 40 keV.

By implanting at a dose of 0.5 to 1×10 cm and performing N2 annealing after removing the resist 25, the structure shown in FIG.
As shown in b), a P" buried layer 26a and a P+ buried isolation layer 26b are formed in the first epitaxial layer 23. Here, the P+ buried layer 26a is located on the N++ buried layer 22. Further, the P+ buried isolation layer 26b is formed so as to be located on the second N+ buried layer.

Next, after removing the oxide film 24, as shown in FIG.
The specific resistance of the same conductivity type as 3 is 2 to 2.5 Ω・Cm.

Phosphorus-doped second epitaxial layer 2 with a thickness of 2 to 3 μm
form 7.

Thereafter, as shown in FIG. 1(d), an oxide film 28 is formed on the second epitaxial layer 27, and a collector lead-out pattern 29a and a separation pattern 29b are formed as openings in this oxide film 28, as in the conventional example. , by diffusing boron through the openings (patterns 29a, 29b) by vapor phase diffusion, etc., into the second epitaxial layer 27.
P+ isolation diffusion [
30b, and a collector extraction layer 30a is formed so as to reach the P+ buried layer 26m.

Then, P+ implantation [second epitaxial layer 2 on 26a]
As shown in FIG. 1te+, a P+ diffusion layer 31 as an emitter layer and an N++ diffused layer 32 for leading out the pace electrode are formed on 7 (pace report) in the same manner as in the conventional example, as shown in FIG. 1te+. This completes the vertical PNP transistor. Thereafter, an oxide film 33 is formed on the second epitaxial layer 27, a contact hole 34 is opened, and a wiring (not shown) is formed.

FIG. 2 shows an example of the impurity concentration distribution in the collector lead layer, epitaxial layer, and buried layer portions in the manufacturing method according to the embodiment of the present invention.

In the above embodiment, N++ is applied to the P-type semiconductor substrate 21.
After forming the mixed layer 22, a first epitaxial layer 23 is formed on the substrate 21, and this first epitaxial layer 23 is coated with P.
+By forming the embedded rB26a, the vertical P
Since the P+ buried layer 26a serving as the collector layer of the N.P.
a can be formed with a lower concentration of 10 cIn or less.

(Effects of the Invention) As detailed above, according to the manufacturing method of the present invention, P0 as the collector layer of the vertical PNP transistor
By forming the buried layer independently from the N1 buried layer,
Since the concentration of the P4 buried layer can be lowered, even if N
Even if the ++-containing layer has a high concentration, the collector capacitance of the PNP transistor can be reduced and the operation speed of the transistor can be increased. By the way, if the concentration of the P+ buried layer can be lowered, it becomes easier to control the amount of upward diffusion of the P+ buried layer, which makes it easier to control the base width, making it easier to control the breakdown voltage and current amplification factor. . Furthermore, the P+ buried layer is N+
If it is formed independently from the buried layer, high-concentration double diffusion is eliminated, so that crystal defects can be prevented from occurring. As described above, according to the manufacturing method of the present invention, it is possible to manufacture a high performance, high quality vertical PNP transistor with little manufacturing variation.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing an embodiment of the semiconductor device manufacturing method of the present invention, FIG. 2 is an impurity concentration distribution diagram according to the above embodiment, and FIG. 3 is a conventional method of manufacturing a vertical PNP transistor. The process sectional view, FIG. 4, is an impurity concentration distribution diagram according to a conventional method. 21...P-type semiconductor substrate, 22...N'' buried layer,
23... First epitaxial layer, 26a... P" buried layer, 26b... P+ buried separation layer, 27... Second epitaxial layer, 30a... Collector extraction layer, 30b
...Separation diffusion layer, 31...P+ diffusion layer. The present invention - Tora finger stop J/) Process elbow 2 Fig. 1 Fig. 3

Claims (1)

[Claims] (a) forming an N^+ buried layer on the surface of a P-type semiconductor substrate; (b) forming an N-type first layer on the substrate having the N^+ buried layer; an epitaxial layer is formed, and the first epitaxial layer includes a vertical PN layer located on the N^+ buried layer.
a P^+ buried layer as a collector layer of a P transistor;
(c) forming a second epitaxial layer of the same conductivity type on the first epitaxial layer; The second epitaxial layer has P^ so as to reach the P^+ buried isolation layer.
+ separation diffusion layer and P to reach the above P^+ buried layer
^+ Step of forming a collector pull-out layer, and (d) thereafter,
A method for manufacturing a semiconductor device comprising the step of forming a P^+ diffusion layer as an emitter layer of a vertical PNP transistor in a second epitaxial layer serving as a base layer of the vertical PNP transistor on the P^+ buried layer. .