JPH01225155A - Bipolar semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance performance and to improve mass productivity of a bipolar semiconductor integrated circuit device by making a semiconductor substrate and its epitaxial layer of the same conductivity type (N-type), and forming the collector layer of a P-N-P transistor and isolating an N-P-N transistor forming part by using a low concentration p-type buried layer. CONSTITUTION:A semiconductor substrate 21 and its epitaxial layer 28 are formed in N-type, and the collector layer of a P-N-P transistor is formed by a low concentration P-type buried layer 24b. Accordingly, a contact part of the layer 24b with a high concentration N-type layer 21 is eliminated in the P-N-P transistor part, thereby reducing the collector capacity of the P-N-P transistor. Since P-type buried layers 24a, 24b are of low concentration, the influence of automatic doping is reduced in a step of forming an epitaxial layer. Thus, a bipolar semiconductor integrated circuit device having high performance can be obtained by enhancing its mass productivity without increasing the number of steps.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bipolar semiconductor integrated circuit device in which a vertical NPN transistor and a vertical PNP transistor are mounted on the same substrate, and a method for manufacturing the same.

(Prior Art) A conventional method of manufacturing a bipolar type semicircular integrated circuit device as described above will be explained with reference to FIG.

First, as shown in Figure 2(a), the specific resistance is 10 to 40Ω.
- Thickness 1 on the surface of P-type semiconductor substrate 1 made of boron doug
An oxide film layer 2 of approximately μm thickness is formed, and then a window 3a for forming an N+ buried layer is formed in the oxide film layer 2 by a photolithography process.
, 3b, the window 3a.

By performing antimony diffusion at 1200° C. for about 60 minutes through 3b, a bonding depth of 2 μm is formed on the substrate l.

N+ buried layers 4a and 4b with sheet resistance of about 100Ω/hole
form.

Next, as shown in FIG. 2(b), a film with a thickness of 1 μm was placed on the substrate 1.
After re-creating the oxide film layer 5 of about 100 mL, a P+ buried layer forming window 6 is formed on the N+ buried layer 4b in the oxide film layer 5 by a photolithography process, and then boron is implanted through the window 6 by ion implantation. Dose ft 1x IQ”
y++-” l Implanted with energy 60keV, 100
By performing annealing at 0° C. for about 60 minutes, a P+ buried layer 7 is formed in the N+ buried layer 4b.

Next, after removing the oxide film layer 5, a resistivity of 2Ω to 2.5Ω is deposited on the substrate 1, as shown in FIG. 2(c).

A phosphorus N-type epitaxial layer 8 having a thickness of about 3 to 3.5 μm is formed by CVD.

Next, B C1! ! By performing green deposition using gas at approximately 1000°C and subsequent drive-in at <1100°C for approximately 60 minutes, the first region of the epitaxial layer on the N+ buried layer 4a and the upper part of the P+ buried layer 7 are formed. A P+ isolation diffusion layer 9 for separating the second region of the epitaxial layer from each other is formed in the epitaxial layer 8 so as to reach the P type semiconductor substrate 1 and the P+ buried layer 7, as shown in FIG. 2(d).

Here, the P+ isolation diffusion layer 9 reaching the P+ buried layer 7 also functions as a collector extraction region of the vertical PNP transistor. Also, when forming this P+ isolation diffusion layer 9,
The N+ buried layers 4a, 4b and the P+ buried layer 7 are diffused upward, but the boron used for the P+ buried layer 7 is heated to 1100°C.
The diffusion coefficient is 2 x 1O-13o1/see
and antimony I X 10-1' cli/see
Therefore, the P+ buried layer 7 is formed above the N+ buried layers 4a and 4b.

After that, as shown in Fig. 2(e), the bonding depth is 1 μm.
, the P+ diffusion layer 10 is formed into the first region (NPN transistor formation part) and the second region (PNP transistor formation part) of the epitaxial layer 8 under the condition that the sheet resistance is 200Ω/hole.
Vertical NPN I'? The N+ diffusion layer 11 is formed as the base of the transistor and the emitter of the vertical PN transistor, and the N+ diffusion layer 11 is formed in the first region and the second region, and K is the second region under the conditions of a % junction depth of 0.7 μm and a sheet resistance of 20 Ω/gate. The emitter of the vertical NPN transistor, the collector extraction region, and the vertical fiPNP are in the epitaxial layer region adjacent to the region.
Formed as a layer for transistor spacing and isolation. As a result, a vertical NPN transistor is completed in the first region, and a vertical PNP transistor is completed in the second region. Finally, the insulation vj on the epitaxial layer 8
, 12, by making contact holes for each diffusion layer, M etc.
Nine turns 13 of electrode wiring are formed.

FIG. 4 shows the impurity concentration distribution in the epitaxial layer and buried layer portions of the conventional device manufactured in this manner.

The N+ buried layer 4b, which is represented by antimony diffusion in this concentration distribution, serves to electrically isolate the collector layer of the PNP transistor formed by the P+ buried layer 7 from the P-type semiconductor base &1.

(Problem to be Solved by the Invention) However, in the above conventional manufacturing method, the N+ buried layer 4b
is formed under the same conditions as the N+ buried layer 4a of the NPN transistor, and has a very high r8 degree, so the vertical P
The first problem is that the NP transistor has a large deflector capacitance, which reduces the operating speed of the transistor.

In addition, in the conventional method described above, since the epitaxial layer 8 is formed on the substrate l which is doped with boron at a high concentration of 1018 or more at the surface by forming the P+ buried layer 7, this boron is autodoped, and the epitaxial layer 8 is doped with boron. There was a second problem in that precise control of specific resistance was difficult. In order to solve this second problem, if the P+ buried layer 7 is simply made to have a low concentration, it will be compensated by the high concentration N+ buried layer 4b, and the sheet resistance will increase (usually 5Ω/hole) or the P+ There is a problem that the buried layer 7 is not formed.

Therefore, the N0 buried layer is made into a 2-layer type, that is, NPN
The N+ buried layer 4a in the transistor part remains high concentration as before, and the N+ buried layer 4a in the PNP transistor part
A conceivable method is to solve the first problem by setting b to a low concentration, and further to solve the second problem by lowering the concentration of the P+ buried layer 7.

However, this method has the problem of increasing the number of photolithography steps and diffusion steps because it forms an N+ buried layer of two types of glue, and is not a satisfactory method in terms of mass production.

The purpose of the present invention is to eliminate the above-mentioned problems of increasing the collector capacitance of vertical PNP transistors and auto-dogging in epitaxial layer formation, and to provide a bipolar semiconductor integrated circuit device with high performance and excellent mass productivity. year,
The purpose of the invention is to provide a method for producing the same.

(Means for Solving the Problem) In this invention, the semiconductor substrate and the epitaxial layer thereon are of the same conductivity type (N type), and the collector I-formation of the PNP transistor is performed using the P-type buried layer with low carbon content. ,NPN
The transistor forming portion is separated.

(Function) If the semiconductor substrate and the epitaxial layer are N-type as described above, and the collector layer of the PNP transistor is formed from a low concentration P-type buried layer, the P-type buried layer and high concentration The contact portion of the N-type layer disappears, and the collector capacitance of the PNP transistor decreases. Furthermore, if the concentration of the P-wall buried layer is low, the influence of autodog will be reduced in the epitaxial layer forming process.

In addition, when the low concentration of the P-type buried layer is expressed numerically, the peak value is about 1X10' to 1X10''.

(Example) An example of the present invention will be described in detail below with reference to the manufacturing process sectional view of FIG. 1.

First, as shown in Fig. 1(a), the specific resistance is 5 to 10Ω・
A 1μ thick layer is applied to the surface of the N-type semiconductor substrate 21.
After forming the oxide film layer 22 with a thickness of approximately m, windows 23a and 23b for forming a low concentration P-type buried layer are formed in the oxide film layer 22 by a photolithography process, and then these windows 23a are formed.
, 23bt-, boron is implanted into the substrate 21 by ion implantation at a dose of 4ItlX 10"m-", with an energy of 6
Implanted at 0 keV, 1000°C.

By performing annealing for about 60 minutes, low concentration P buried layers 24a and 24b are formed in the substrate 21. Here, the P-type buried layer 24a is formed for the function of the vertical NPN transistor forming portion, and the P-type buried layer Kl 24b is formed as a collector layer of the vertical PNP transistor.

Next, as shown in FIG. 1(b), a layer of 1 μm thick is placed on the substrate 21.
After recreating the oxide film layer 25 with a thickness of about m, a window 2 for forming an N+ buried layer is formed in the oxide film layer 25 by a photolithography process.
form 6. ζHere, the N0 buried layer forming window 26 is formed above the P type buried layer 24& and located inside this buried layer 24a. Then, if the window 26 is formed in this way, then the temperature will be 1200°C through the window 26.

By performing antimony diffusion for about 60 minutes, a junction depth of 2 μm and a sheet resistance of 10
An N+ buried layer 27 for reducing the collector resistance of a vertical NPN transistor of approximately 0 Ω/hole is formed.

Next, after removing the oxide film layer 25, a resistivity of 20φα to 2.50· is deposited on the substrate 21 as shown in FIG.
d. An N-type epitaxial layer 28 having a thickness of about 3 to 3.5 μm is formed.

Next, grinding with Bα1 gas at about 1000°C and subsequent (1100°C, about 60 minutes)
By doing a drive-in, N+ embedded 1i12
1st region of the Evita midshall layer on 7 and P wall embedded 1i11
A sufficiently gradual P diffusion layer 29 is formed in the epitaxial layer 28 so as to reach the P wall buried layers 24a and 24b, as shown in FIG. . Here, the P wall buried layer 24b
The P sufficiently gradually diffused layer 29 which has reached 100 nm also acts as a collector extraction region of the branch mPNP transistor. Also,
When forming the pin separation diffusion If429 with the buried layers 24a, 2
4b, 27 are diffused upward, but the PU buried layers 24a, 2
4b is 10 degrees compared to the N+ buried layer 27, so
It does not diffuse above the N+ buried layer 27.

After that, as shown in Figure 1(e), the fitting depth is 1 μm.
, under the condition that the sheet resistance is 200 Ω/mouth, P+ diffusion no. Formed as an emitter, and furthermore, the junction depth is 0.
．． N10 diffusion layer 3 under the conditions of 7μm, sheet resistance 20Ω/mouth
1 is formed in the first region and the second region, and further in the epitaxial layer region adjacent to the second region, as an emitter of a vertical NPN transistor, a collector extraction region, a paste extraction region of a vertical PNP transistor, and a layer for isolation. do. As a result, a vertical NPN transistor is completed in the first region, and a vertical PNP transistor is completed in the second region. Finally, the insulation on the epitaxial layer 28 [
A contact hole is opened in 32 for each diffusion layer, and an electrode wiring pattern 33 is formed using M or the like.

In addition, Fig. 1(e) shows a floating grid in which the emitter of the NPN transistor is connected to ground (lowest potential), the emitter of the PNP transistor is connected to VDD (highest potential), and both collectors are connected in common. FIG. 3, which shows an example of forming a mental circuit, shows the impurity concentration distribution in the serial and buried portions of the terminal in a fixed device manufactured in this way. As is clear from this figure, according to this device and the manufacturing method described above, although the P-wall buried layers 24a and 24b are formed, the impurity concentration of Ron is reduced to 1/10 compared to the conventional example. I understand. Therefore, the problem of auto-douging when forming the epitaxial layer 28 is alleviated, and the resistivity of the epitaxial layer can be precisely controlled.

Furthermore, if the substrate 21 and the epitaxial layer 28 are N-type as described above, and the collector 1- of the PNP transistor is formed by the lightly doped PM buried layer 24b, the P-wall buried layer and the heavily doped N-type layer are formed in the PNP transistor part. The contact portion of the PNP transistor is eliminated, and the collector capacitance of the PNP transistor is reduced.

In turn, the operating speed of the transistor can be increased.

(Effects of the Invention) As described in detail above, according to the present invention, it is possible to form an epitaxial layer, reduce the influence of autodog at 9 o'clock, accurately control the resistivity of the epitaxial layer, and By reducing the collector capacitance of a PNP transistor, the operation speed of the transistor can be increased, and such a high-performance bipolar semiconductor integrated circuit device can be obtained with improved mass productivity without increasing the number of steps.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the manufacturing process for explaining an embodiment of the present invention, FIG. 2 is a cross-sectional view of the manufacturing process of a conventional bipolar semiconductor device manufacturing method, and FIG. 3 is a cross-sectional view of the manufacturing process for explaining an embodiment of the present invention. Impurity concentration distribution diagram, FIG. 4 is an impurity concentration distribution diagram in a conventional manufacturing method. 21... N-type semiconductor substrate, 24a, 24b... P wall buried layer, 27..., N buried layer, 28... epitaxial layer, 29... P sufficiently diffused layer, 30...・
P ten diffusion layer, 31...N ten diffusion layer.

Claims (2)

[Claims] (1) (a) An epitaxial layer of the same conductivity type is formed on an N-type semiconductor substrate, and (b) a low-concentration first layer is provided at the bottom of the epitaxial layer for partial isolation to form a vertical NPN transistor. (c) In the first P-type buried layer, an upper epitaxial layer and a second low-concentration P-type buried layer are formed as a collector layer of a vertical PNP transistor. an N-type buried layer for reducing the collector resistance of the vertical NPN transistor is formed in contact therewith; (d) a first region of the epitaxial layer having the N-type buried layer at the bottom;
A second region of the epitaxial layer having the second P-type buried layer at the bottom is electrically isolated from each other by an isolation diffusion layer; (e) the first region includes the remaining diffusion layer of the vertical NPN transistor; A bipolar semiconductor integrated circuit device in which a remaining diffusion layer of a vertical PNP transistor is formed in the region. (2) (a) A first low-concentration P-type buried layer for isolation and a second low-concentration P-type buried layer as a collector layer of the vertical PNP transistor on the surface of the N-type semiconductor substrate. (b) Next, forming an N-type buried layer for reducing the collector resistance of the vertical NPN transistor in the first P-type buried layer; (c) Then, forming an N-type semiconductor substrate. (d) forming an isolation diffusion layer in the epitaxial layer and forming the epitaxial layer into a first region having the N-type buried layer at the bottom and the first region having the N-type buried layer at the bottom; (e) forming the remaining diffusion layer of the vertical NPN transistor in the first region, and forming the remaining diffusion layer of the vertical PNP transistor in the second region; A method for manufacturing a bipolar semiconductor integrated circuit device, comprising the step of forming a remaining diffusion layer.