JPH033953B2 - - Google Patents

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Publication number
JPH033953B2
JPH033953B2 JP57095334A JP9533482A JPH033953B2 JP H033953 B2 JPH033953 B2 JP H033953B2 JP 57095334 A JP57095334 A JP 57095334A JP 9533482 A JP9533482 A JP 9533482A JP H033953 B2 JPH033953 B2 JP H033953B2
Authority
JP
Japan
Prior art keywords
region
type
base
transistor
concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57095334A
Other languages
Japanese (ja)
Other versions
JPS58212158A (en
Inventor
Haruyasu Yamada
Toyoki Takemoto
Tadanaka Yoneda
Tsutomu Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57095334A priority Critical patent/JPS58212158A/en
Priority to EP83103726A priority patent/EP0093304B1/en
Priority to DE8383103726T priority patent/DE3361832D1/en
Publication of JPS58212158A publication Critical patent/JPS58212158A/en
Priority to US07/124,423 priority patent/US4826780A/en
Priority to US07/295,380 priority patent/US5066602A/en
Publication of JPH033953B2 publication Critical patent/JPH033953B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8228—Complementary devices, e.g. complementary transistors
    • H01L21/82285—Complementary vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H01L27/0244—I2L structures integrated in combination with analog structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H01L27/0826—Combination of vertical complementary transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は半導体集積回路装置の製造方法に関
し、特に高速のバイポーラトランジスタを含む半
導体集積回路装置の製造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor integrated circuit device including a high-speed bipolar transistor.

半導体集積回路装置にはPNPトランジスタ、
NPNトランジスタ等が一体化構成されている。
ここで、一般にNPNトランジスタのスイツチン
グ速度は高速にすることが出来る反面、PNPト
ランジスタは構造が複雑であつたり、横方向形成
されたものは高速にすることが出来ない欠点を有
する。従つて、PNPトランジスタ、NPNトラン
ジスタとを含む半導体集積回路装置はその両トラ
ンジスタの速度的なアンバランスが生じる故に全
体として見た場合、回路的にも多くの制限があつ
た。 Semiconductor integrated circuit devices include PNP transistors,
NPN transistor etc. are integrated.
Generally, the switching speed of NPN transistors can be increased, but PNP transistors have a complicated structure or are formed laterally, which has the drawback that high switching speeds cannot be achieved. Therefore, a semiconductor integrated circuit device including a PNP transistor and an NPN transistor has many limitations in terms of the circuit when viewed as a whole due to the speed imbalance between the two transistors.

第１図はPNPトランジスタを、集積回路の標
準であるNPNトランジスタの製造工程を利用し
て一体化形成した従来の半導体集積回路装置を示
す。 FIG. 1 shows a conventional semiconductor integrated circuit device in which a PNP transistor is integrally formed using a manufacturing process for an NPN transistor, which is a standard for integrated circuits.

第１図において、１はｐ形基板、２は高濃度ｎ
形埋込層、３はｎ形エピタキシヤル層、４は予備
分離拡散層を示す。５はエピタキシヤル層３表面
から形成された分離拡散層で、予備分離拡散層４
と途中で接続され、活性領域の分離を行つてい
る。 In FIG. 1, 1 is a p-type substrate, 2 is a high concentration n
3 is an n-type epitaxial layer, and 4 is a preliminary isolation diffusion layer. 5 is a separation diffusion layer formed from the surface of the epitaxial layer 3, and is a preliminary separation diffusion layer 4.
It is connected in the middle to separate the active region.

６ｅ，６ｃ，７ｂはｐ形拡散層である。ここ
で、NPNトランジスタ部分においては７ｂはベ
ースとなるｐ形領域で、ラテラルPNPトランジ
スタ部分においては６ｅ，６ｃはそれぞれエミツ
タとコレクタを形成している。８ｂはPNPトラ
ンジスタのベース領域用のコンタクト、９ｅは
NPNトランジスタのエミツタ、９ｃはNPNトラ
ンジスタのコレクタコンタクトのための高濃度ｎ
形拡散層である。第１図で一体化形成された
NPN、PNPトランジスタにおいて、PNPの横型
トランジスタはベース幅（領域６ｅと６ｃ間距
離）が平面的、つまりマスクのパターン精度で定
まる。一般的に、マスク精度はそれほど正確なも
のではないため、通常短いもので3μｍ程度であ
る。従つて、ベース幅の狭いPNPトランジスタ
を形成出来ない。また、NPNトランジスタのベ
ース領域７ｂにおいては拡散によつて濃度傾斜が
ついているため、電界傾斜がベース領域で形成さ
れるのでキヤリアの加速がなされ高速化が実現す
る。しかし、PNPトランジスタのベース領域３
はエピタキシヤル層そのものであり、濃度傾斜が
なく高速化が実現されない。さらに、PNPトラ
ンジスタのコレクタ領域６ｃの濃度がベース領域
３よりむしろ高く、ベース幅を縮小していつた場
合、コレクタ、エミツタ間耐圧が急速に下がる。 6e, 6c, and 7b are p-type diffusion layers. Here, in the NPN transistor portion, 7b is a p-type region serving as a base, and in the lateral PNP transistor portion, 6e and 6c form an emitter and a collector, respectively. 8b is the contact for the base region of the PNP transistor, 9e is the contact for the base region of the PNP transistor, and 9e is the contact for the base region of the PNP transistor.
The emitter of the NPN transistor, 9c is a high concentration n for the collector contact of the NPN transistor.
It is a shaped diffusion layer. integrally formed in Figure 1
In NPN and PNP transistors, the base width (distance between regions 6e and 6c) of the PNP lateral transistor is determined in a plane, that is, by the pattern accuracy of the mask. Generally, the mask accuracy is not very accurate, and the short one is usually about 3 μm. Therefore, a PNP transistor with a narrow base width cannot be formed. Furthermore, since the base region 7b of the NPN transistor has a concentration gradient due to diffusion, an electric field gradient is formed in the base region, so carriers are accelerated and high speed is achieved. However, the base region 3 of the PNP transistor
is an epitaxial layer itself, and there is no concentration gradient, making it impossible to achieve high speed. Furthermore, the concentration of the collector region 6c of the PNP transistor is higher than that of the base region 3, and when the base width is reduced, the breakdown voltage between the collector and emitter decreases rapidly.

以上の様に、第１図では製造工程を追加するこ
となくPNPトランジスタを一体化出来るが、第
１図のPNPトランジスタはベースの幅が広い拡
散プロフアイルにより電界傾斜がついていない、
PNPトランジスタのコレクタ濃度がベース濃度
よりも高く耐圧が低い等の３つの理由により横型
PNPトランジスタは縦型NPNトランジスタに比
べて著しく特性が劣るのが通常である。従つて、
第１図に示す半導体集積回路装置においては全体
としての特性が不十分なものとなつていた。 As mentioned above, the PNP transistor shown in Fig. 1 can be integrated without any additional manufacturing process, but the PNP transistor shown in Fig. 1 does not have an electric field gradient due to the diffusion profile with a wide base.
Horizontal type due to three reasons such as collector concentration of PNP transistor is higher than base concentration and lower breakdown voltage.
PNP transistors usually have significantly inferior characteristics compared to vertical NPN transistors. Therefore,
The semiconductor integrated circuit device shown in FIG. 1 had insufficient characteristics as a whole.

次に、これを改善した半導体集積回路装置の従
来例を第２図に示す。第２図の場合は製造工程を
追加し、縦型のPNPトランジスタを一体形成し
たものである。 Next, FIG. 2 shows a conventional example of a semiconductor integrated circuit device that has improved this. In the case of Fig. 2, a manufacturing process is added and a vertical PNP transistor is integrally formed.

第２図において、１１はｐ形基板、１２は高濃
度ｎ形埋込層、１３はｎ形エピタキシヤル層、１
４はｐ形予備分離拡散層で、１５は分離拡散層で
ある。この分離拡散層１４及び１５により、活性
領域を分離させている。１６はｎ形埋込層１２上
にイオン注入法等で製作されたｐ形領域で、縦形
PNPトランジスタのコレクタとなる領域である。
１７，１８はそれぞれ分離拡散層１４，１５の領
域形成時に同時形成されるもので、コレクタ領域
１６の引出し拡散層となつている。１９はベース
１３の引出し拡散層である。２０はp+の拡散層
で分離拡散層１５と同時に形成され、縦型PNP
トランジスタのエミツタとなる領域である。２１
は通常のNPNトランジスタのエミツタ層、２２
はベース層、２３はエミツタ２１と同時に形成さ
れたコレクタ・コンタクト部である。 In FIG. 2, 11 is a p-type substrate, 12 is a high concentration n-type buried layer, 13 is an n-type epitaxial layer, 1
4 is a p-type preliminary separation diffusion layer, and 15 is a separation diffusion layer. The active regions are separated by the isolation diffusion layers 14 and 15. 16 is a p-type region manufactured by ion implantation method etc. on the n-type buried layer 12, and is a vertical type region.
This is the region that becomes the collector of the PNP transistor.
17 and 18 are formed simultaneously when forming the isolation diffusion layers 14 and 15, respectively, and serve as lead-out diffusion layers for the collector region 16. 19 is a drawer diffusion layer of the base 13. 20 is a p + diffusion layer formed at the same time as the separation diffusion layer 15, and is a vertical PNP.
This is the area that becomes the emitter of the transistor. 21
is the emitter layer of a normal NPN transistor, 22
23 is a base layer, and 23 is a collector contact portion formed at the same time as the emitter 21.

さて、第２図でp+エミツタ拡散層２０、ベー
スとなるｎ形エピタキシヤル層１３、p+形コレ
クタ層１６によつて縦型PNPトランジスタが形
成される。このPNPトランジスタは第１図で示
した横型PNPトランジスタと違い、ベース幅が
マスクの寸法及び寸法精度によつて決定されてお
らず、エピタキシヤル層１３の厚み、p+拡散コ
レクタ領域１６及びp+エミツタ拡散層２０の深
さに依存しているため、拡散制御によつてベース
幅は狭く出来る利点がある。しかしこの構造にお
いても多くの欠点がある。まず第１にベース幅で
あるが、これはエピタキシヤル層１３の厚みから
エミツタ２０の拡散深さとｐ形コレクタ領域１６
の上方拡散幅とを引いたものによつて決定される
ので、ベース幅の分布が非常に大きい。それに加
えるにｐ形コレクタ領域１６の濃度は埋込層１２
の濃度との加減によつてきまるため、上方拡散
は、ｐ形コレクタ領域１６のドーピング量によつ
て一義的に決まらず、従つて、ベース幅の分布は
ますます大きくなつてしまい、ベース幅がパター
ン精度で制限されないというもののベース幅の決
定制御が困難である。しかも、このトランジスタ
においてもエピタキシヤル層がベースであり第１
図で示したPNPトランジスタでみられた欠点で
あるベース領域での濃度勾配がない点及びコレク
タ１２の濃度がベースよりも高い問題は改善され
ていない。すなわち、このトランジスタもベース
幅の決定制御が困難、濃度勾配がない、耐圧が低
いという３つの問題を有している。 Now, in FIG. 2, a vertical PNP transistor is formed by the p + emitter diffusion layer 20, the n type epitaxial layer 13 serving as a base, and the p + type collector layer 16. This PNP transistor differs from the lateral PNP transistor shown in FIG . Since it depends on the depth of the emitter diffusion layer 20, there is an advantage that the base width can be narrowed by diffusion control. However, this structure also has many drawbacks. First of all, the base width is determined by the thickness of the epitaxial layer 13, the diffusion depth of the emitter 20, and the p-type collector region 16.
subtracting the upper diffusion width of the base width, the distribution of the base width is very large. In addition, the concentration of the p-type collector region 16 is higher than that of the buried layer 12.
Therefore, the upward diffusion is not uniquely determined by the doping amount of the p-type collector region 16, and therefore the base width distribution becomes wider and wider. Although it is not limited by pattern accuracy, it is difficult to determine and control the base width. Moreover, in this transistor as well, the epitaxial layer is the base and the first layer is the base layer.
The drawbacks of the PNP transistor shown in the figure, namely, that there is no concentration gradient in the base region and that the concentration of the collector 12 is higher than that of the base, have not been improved. That is, this transistor also has three problems: it is difficult to determine and control the base width, there is no concentration gradient, and the breakdown voltage is low.

本発明は従来の欠点に鑑みてなされたもので、
高速のPNPバイポーラトランジスタと高抵抗素
子とを形成しかつこれと高性能なNPNバイポー
ラトランジスタを含む半導体集積回路装置をプロ
セス上有利な方法で提供することを目的とする。
すなわち、本発明は第１図の横型PNPバイポー
ラトランジスタの低速性と第２図の縦型PNPバ
イポーラトランジスタのベース幅を制御性良く決
定出来ない点及び耐圧を改善するとともに、通常
の半導体集積回路で形成される高速のNPNバイ
ポーラトランジスタを含む半導体集積回路装置の
製造工程を大幅に増加することなく一体化形成可
能とする方法を提供せんとするものである。さら
に、上記方法に加えるに高抵抗素子を同時に一体
化形成可能とする半導体集積回路装置の製造方法
を提供せんとするものである。 The present invention has been made in view of the conventional drawbacks.
An object of the present invention is to form a high-speed PNP bipolar transistor and a high-resistance element, and to provide a semiconductor integrated circuit device including the same and a high-performance NPN bipolar transistor using a process advantageous method.
That is, the present invention improves the low speed of the horizontal PNP bipolar transistor shown in FIG. 1, the inability to determine the base width of the vertical PNP bipolar transistor shown in FIG. 2 with good controllability, and improves the withstand voltage. The present invention aims to provide a method that enables integrated formation of a semiconductor integrated circuit device including a high-speed NPN bipolar transistor without significantly increasing the number of manufacturing steps. Furthermore, it is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit device which, in addition to the above-mentioned method, can simultaneously form a high-resistance element in an integrated manner.

以下、本発明の一実施例を図面を用いて説明す
る。第３図は本発明の一実施例の方法により形成
された半導体集積回路装置の構造断面図を示すも
のである。本実施例においては縦型のPNPトラ
ンジスタと縦型NPNトランジスタ及び高抵抗素
子を一体化形成したものであり、縦型PNPトラ
ンジスタの部分に改良を加え一体化形成したもの
である。 An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows a cross-sectional view of the structure of a semiconductor integrated circuit device formed by a method according to an embodiment of the present invention. In this embodiment, a vertical PNP transistor, a vertical NPN transistor, and a high resistance element are integrally formed, and the vertical PNP transistor is improved and integrally formed.

第３図において、３１はｐ形半導体基板、３２
はｎ形高濃度埋込領域、３３は0.5〜1.0Ωcm程度
のｎ形エピタキシヤル層で３〜4μｍの厚さに成
長される。３４はｐ形高濃度の予備拡散埋め込み
領域で、エピタキシヤル層３３表面から形成され
るｐ形高濃度拡散領域３５と対をなし、エピタキ
シヤル層３３の分離をおこないPNPバイポーラ
トランジスタ形成領域、高抵抗素子の形成領域及
びNPNトランジスタのコレクタ領域を形成して
いる。この分離領域３４，３５は酸化膜分離によ
つて行なつても本発明の効果は変わらない。３６
はｐ形の高濃度埋込領域で、埋込領域３２の内側
に設置され、分離領域３４と同時に形成されてい
る。高濃度埋込領域３６の表面濃度は、基板３１
上の埋込領域３２が高濃度のためにかなり下がつ
ており、このため上方への拡散は少なくて、拡散
領域３４ほど高くはならない。３７は拡散領域３
５と同時に形成されたp+拡散領域で、コレクタ
抵抗の削減のために設置されたものである。３８
はn+の拡散領域で、埋込領域３２と接続される。
３９は本発明にて形成される主要領域の１つで、
低ドーズのイオン注入法により形成され、シート
抵抗値として通常のNPNトランジスタのベース
抵抗の200Ω／□に比べて１桁以上高い2KΩ／□
〜4KΩ／□程度のp-領域でありPNPトランジス
タのコレクタ領域となる。４０はコレクタ領域３
９と同時に形成されたp-領域で、この中に高抵
抗素子を形成する。４１は本発明の主要領域の１
つであるｎ形ウエルで、イオン注入法でp-領域
３９内に形成されPNPトランジスタのｎ形ベー
ス領域となる。４２はベース領域４１と同時に形
成されたｎ形ウエルで高抵抗素子を形成する。４
３はｎ形ベース領域４１内に形成される約200
Ω／□程度のｐ形領域でPNPトランジスタのエ
ミツタ領域であり、縦型のNPNトランジスタの
コレクタ領域内に形成されるｐ形ベース領域４４
と同時に形成される。４５は高抵抗素子のp-領
域４０のコンタクト用拡散領域で、領域４３，４
４と同時形成される。４６はベース領域４１のｎ
形コンタクト拡散領域であり、NPNトランジス
タのエミツタ領域４７と同時に形成される。これ
と同時に拡散領域４８を形成し、高抵抗素子のコ
ンタクト部を構成する。４９はNPNトランジス
タのコレクタ３３のｎ形コンタクト領域である。 In FIG. 3, 31 is a p-type semiconductor substrate, 32
33 is an n-type epitaxial layer of about 0.5 to 1.0 Ωcm grown to a thickness of 3 to 4 μm. Reference numeral 34 designates a p-type high concentration pre-diffusion buried region, which pairs with the p-type high concentration diffusion region 35 formed from the surface of the epitaxial layer 33, separates the epitaxial layer 33, and forms a PNP bipolar transistor formation region and a high resistance region. It forms the element formation region and the collector region of the NPN transistor. Even if these isolation regions 34 and 35 are formed by oxide film isolation, the effects of the present invention will not change. 36
is a p-type high concentration buried region, which is placed inside the buried region 32 and formed simultaneously with the isolation region 34. The surface concentration of the high concentration buried region 36 is the same as that of the substrate 31.
The upper buried region 32 is quite down due to the high concentration, so there is less upward diffusion and it does not go as high as the diffusion region 34. 37 is diffusion area 3
This is a p + diffusion region formed at the same time as No. 5, and was installed to reduce collector resistance. 38
is an n + diffusion region and is connected to the buried region 32.
39 is one of the main areas formed in the present invention,
Formed using a low-dose ion implantation method, the sheet resistance is 2KΩ/□, which is more than an order of magnitude higher than the base resistance of a normal NPN transistor, which is 200Ω/□.
It is a p - region of ~4KΩ/□ and serves as the collector region of a PNP transistor. 40 is collector area 3
A high resistance element is formed in the p - region formed at the same time as 9. 41 is one of the main areas of the present invention
This n-type well is formed in the p - region 39 by ion implantation and becomes the n-type base region of the PNP transistor. 42 is an n-type well formed at the same time as the base region 41 and forms a high resistance element. 4
3 is approximately 200 mm formed within the n-type base region 41.
The p-type base region 44 is a p-type region of about Ω/□ and is the emitter region of the PNP transistor, and is formed within the collector region of the vertical NPN transistor.
formed at the same time. 45 is a contact diffusion region of the p - region 40 of the high resistance element;
Formed simultaneously with 4. 46 is n of the base region 41
The contact diffusion region is formed at the same time as the emitter region 47 of the NPN transistor. At the same time, a diffusion region 48 is formed to constitute a contact portion of a high resistance element. 49 is an n-type contact region of the collector 33 of the NPN transistor.

以上の説明ならびに第３図から明らかなよう
に、ｐ形エミツタ領域４３、ｎ形ベース領域４
１、ｐ形コレクタ領域３９で縦型PNPトランジ
スタが形成され、ｎ形エミツタ領域４７、ｐ形ベ
ース領域４４、ｎ形コレクタ領域３３で縦型
NPNトランジスタが形成され、n-形領域４２で
高抵抗素子が形成されていることがわかる。 As is clear from the above explanation and FIG. 3, the p-type emitter region 43 and the n-type base region 4
1. A vertical PNP transistor is formed in the p-type collector region 39, and a vertical PNP transistor is formed in the n-type emitter region 47, the p-type base region 44, and the n-type collector region 33.
It can be seen that an NPN transistor is formed and a high resistance element is formed in the n - type region 42.

ここで、以上の方法で形成された縦型PNPト
ランジスタの特性を第４図に示す。第３図の縦型
PNPトランジスタの各領域の深さ方向の不純物
濃度分布を基に説明する。従来の第１図、第２図
のPNPトランジスタの問題点が解消出来ること
を説明する。ベースであるｎ形領域４１が、低濃
度のp-コレクタ領域３９内に形成されており、
狭いベース幅が得られ、そのｐ形不純物の濃度の
制御及び深さの制御がp-領域３９上から打ち込
まれている不純物のイオン注入によつて精度良く
定められ、ｐ形エミツタ領域も同様に形成でき
る。従つて、ベース幅（エミツタ領域４３の低部
からベース領域４１の低部までの距離）は、ｎ形
ベース領域４１とｐ形エミツタ領域４３の不純物
の制御のみによつて決定されるので制御性が良
い。つまり、第２図の場合は３つのパラメータで
あつたが、本実施例では領域４１と４３の形成と
いう２つのパラメータでベース幅が決定される。
また、ｎ形ベース領域４１は最終的にはイオン注
入後の不純物のドライブインによつて決められる
ため、第４図から明らかなように、上から下方向
に濃度が下がる濃度勾配がついており、電界加速
が行なわれる構造になつているのでキヤリアの走
行速度が増大し、高速動作が可能となるとともに
n+ベースコンタクト領域４６にてベースコンタ
クトを確実に形成できる。また、コレクタとなる
ｐ形コレクタ領域３９の濃度は第４図からも明か
なように従来と異なり、ベース領域よりも低濃度
のp-であるため、耐圧も高く、高濃度ｐ形領域
３６の存在のためコレクタ抵抗は低くできる。 FIG. 4 shows the characteristics of the vertical PNP transistor formed by the above method. Vertical type in Figure 3
The explanation will be based on the impurity concentration distribution in the depth direction of each region of the PNP transistor. It will be explained that the problems of the conventional PNP transistors shown in FIGS. 1 and 2 can be solved. An n-type region 41, which is a base, is formed within the lightly doped p - collector region 39,
A narrow base width is obtained, and the concentration and depth of the p-type impurity are precisely determined by the impurity ion implantation implanted from above the p - region 39, and the p-type emitter region is similarly controlled. Can be formed. Therefore, the base width (the distance from the lower part of the emitter region 43 to the lower part of the base region 41) is determined only by controlling the impurities in the n-type base region 41 and the p-type emitter region 43, so that controllability is improved. is good. That is, in the case of FIG. 2, there were three parameters, but in this embodiment, the base width is determined by two parameters: the formation of regions 41 and 43.
Furthermore, since the n-type base region 41 is ultimately determined by the impurity drive-in after ion implantation, as is clear from FIG. 4, there is a concentration gradient in which the concentration decreases from the top to the bottom. Since the structure uses electric field acceleration, the traveling speed of the carrier increases and high-speed operation is possible.
A base contact can be reliably formed in the n + base contact region 46. Furthermore, as is clear from FIG. 4, the concentration of the p-type collector region 39, which serves as the collector, is different from the conventional one, and is lower in p - concentration than the base region, so the withstand voltage is high, and the high concentration p-type region 36 has a higher concentration. Because of its presence, the collector resistance can be lowered.

さらに、第３図の縦型PNPトランジスタの特
長を、深さ方向不純物分布を示す第４図を参照し
て述べる。この第４図において、埋込領域３２は
例えばAs（砒素）のような拡散係数の小さいもの
を使用し、ｐ形領域３６はボロン等を使用するこ
とにより、基板３１からの上方拡散が図示したよ
うになる。またｐ形エミツタ領域４３、ｎ形ベー
ス領域４１及び領域３６よりも低濃度のｐ形コレ
クタ領域３９は、イオン注入法でそれぞれボロ
ン、リン等を打ち込みその後の熱処理により制御
性良く形成される。第４図で明らかなように、領
域３９よりも高濃度のｎ形ベース領域４１はその
濃度傾斜が大きく、ベースに電界傾斜が得られ
る。さらに、コレクタ領域３９が極めて低濃度と
出来るため、ベース領域４１の形成はその深さ
も、ベースへの不純物の添加量とエミツタ領域４
３の不純物量の両者により実質的に定められ、コ
レクタ領域３９の不純物濃度に依存することがな
いので、その制御に困難性はない。 Furthermore, the features of the vertical PNP transistor shown in FIG. 3 will be described with reference to FIG. 4, which shows the impurity distribution in the depth direction. In FIG. 4, the buried region 32 is made of a material with a small diffusion coefficient, such as As (arsenic), and the p-type region 36 is made of boron, etc., thereby illustrating upward diffusion from the substrate 31. It becomes like this. Further, the p-type emitter region 43, the n-type base region 41, and the p-type collector region 39 having a lower concentration than the region 36 are formed with good controllability by implanting boron, phosphorus, etc., respectively, by ion implantation and subsequent heat treatment. As is clear from FIG. 4, the n-type base region 41, which has a higher concentration than the region 39, has a large concentration gradient, and an electric field gradient is obtained at the base. Furthermore, since the collector region 39 can be made with an extremely low concentration, the depth of the base region 41 is determined by the amount of impurity added to the base and the emitter region 4.
Since it is substantially determined by both the impurity amounts of No. 3 and does not depend on the impurity concentration of the collector region 39, there is no difficulty in controlling it.

以上のPNPトランジスタと同時に高抵抗素子
が形成される。高抵抗素子４２の電極コンタクト
領域は両端のn+拡散領域４８である。これは
NPNトランジスタのベース領域４４を利用した
抵抗体のシート抵抗値よりも大きく、かつp-拡
散領域４０のシート抵抗よりも小さいシート抵抗
値の抵抗体を形成することが出来る。ここで得ら
れるシート抵抗体が500〜1KΩ／□という値は高
速のロジツク回路に使用するのに適当な大きさで
ある。 A high resistance element is formed simultaneously with the above PNP transistor. The electrode contact regions of the high resistance element 42 are the n + diffusion regions 48 at both ends. this is
It is possible to form a resistor having a sheet resistance larger than that of a resistor using the base region 44 of an NPN transistor and smaller than the sheet resistance of the p - diffusion region 40. The sheet resistor obtained here has a value of 500 to 1 KΩ/□, which is suitable for use in high-speed logic circuits.

また一般に拡散層の濃度が高いほど抵抗の温度
係数が小さいが、このｎ拡散領域４２の拡散深さ
はp-拡散領域４０に比べて浅いので濃度は比較
的高く、従つて温度特性が優れている。また、高
抵抗素子４２は低濃度のp-拡散層４０との接合
面を有するので、抵抗素子の寄生接合容量が小さ
く優れた高周波特性を有する。 Generally, the higher the concentration of the diffusion layer, the lower the temperature coefficient of resistance, but since the diffusion depth of the n diffusion region 42 is shallower than that of the p - diffusion region 40, the concentration is relatively high, and therefore the temperature characteristics are excellent. There is. Further, since the high resistance element 42 has a junction surface with the low concentration p - diffusion layer 40, the resistance element has a small parasitic junction capacitance and has excellent high frequency characteristics.

また、本実施例に係る構造では、高抵抗島領域
４０とPNPトランジスタのコレクタ領域３９が
共通プロセスであり、NPNトランジスタのベー
ス領域４４がPNPトランジスタのエミツタ領域
４３及び高抵抗素子の島領域４０のコンタクト４
５と共通プロセスで形成されるため、縦型PNP
トランジスタを形成するために、新たなプロセス
として、単にベースとなるｎ形領域４１を形成し
かつ同時に高抵抗４２を形成するプロセスの追加
にすぎなく非常に簡便な構造となつている。 Furthermore, in the structure according to this embodiment, the high resistance island region 40 and the collector region 39 of the PNP transistor are formed in a common process, and the base region 44 of the NPN transistor is formed in the emitter region 43 of the PNP transistor and the island region 40 of the high resistance element. contact 4
Vertical PNP because it is formed by the same process as 5.
In order to form a transistor, a new process is simply added to form an n-type region 41 serving as a base and a high resistance 42 at the same time, resulting in a very simple structure.

次に本発明の他の実施例について第５図を用い
て説明する。同図において第３図と同一の部分は
同一番号を付してある。５０は領域３６と同時に
形成されるｐ形の高濃度埋込領域、５１は抵抗の
分離島領域である。ｐ領域４０は通常接地電位に
してｎ領域４２と逆バイアスする。一方、ｎ領域
５１の中にNPNトランジスタのベース領域４４
と同じ拡散層からなる抵抗を形成した場合には島
５１の電位はp-領域４０とは逆に電源電圧に上
げる必要がある。この場合、ｎ領域４２の下部の
p-島領域４０の厚さが狭いとパンチスルーある
いは欠陥等により領域５１，４２が接続される可
能性がある。そこで埋込拡散領域５０をp-島領
域４０の下部に形成することにより、歩留りの低
下を防ぐことができる。 Next, another embodiment of the present invention will be described using FIG. 5. In this figure, the same parts as in FIG. 3 are given the same numbers. 50 is a p-type high concentration buried region formed at the same time as region 36, and 51 is a resistor isolation island region. P region 40 is normally at ground potential and reverse biased to n region 42 . On the other hand, the base region 44 of the NPN transistor is located in the n region 51.
If a resistor made of the same diffusion layer is formed, the potential of the island 51 needs to be raised to the power supply voltage, contrary to that of the p - region 40. In this case, the lower part of the n region 42
If the thickness of the p - island region 40 is narrow, the regions 51 and 42 may be connected due to punch-through or defects. Therefore, by forming the buried diffusion region 50 under the p - island region 40, it is possible to prevent the yield from decreasing.

以上の様に、本発明は、高耐圧、高速、高密度
な縦型PNPトランジスタと高速の縦型NPNトラ
ンジスタと、高密度、ロジツク回路に適した高抵
抗素子とを工程数を大幅に増やすことなく一体形
成出来、高耐圧、高速半導体集積回路を製造する
上で優れた工業的効果を有するものである。 As described above, the present invention is capable of producing a high-voltage, high-speed, high-density vertical PNP transistor, a high-speed vertical NPN transistor, and a high-resistance element suitable for a high-density, logic circuit by significantly increasing the number of manufacturing steps. It can be integrally formed without any problem, and has excellent industrial effects in manufacturing high-voltage, high-speed semiconductor integrated circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第２図は従来の半導体集積回路装置
の構造断面図、第３図は本発明の一実施例の方法
にて縦型PNPトランジスタ、縦型NPNトランジ
スタ、高抵抗素子を一体化した半導体集積回路装
置の構造断面図、第４図は第３図の縦型PNPト
ランジスタの不純物分布図、第５図は第３図にお
ける高抵抗体を改良した本発明の他の実施例を示
す構造断面図である。 ３９，４０……p-領域、４１，４２……ｎ領
域、４３，４４，４５……ｐ領域、４６，４７，
４８，４９……n+領域。 Figures 1 and 2 are structural cross-sectional views of a conventional semiconductor integrated circuit device, and Figure 3 is a structure in which a vertical PNP transistor, a vertical NPN transistor, and a high resistance element are integrated using the method of an embodiment of the present invention. A structural sectional view of a semiconductor integrated circuit device, FIG. 4 is an impurity distribution diagram of the vertical PNP transistor shown in FIG. 3, and FIG. 5 is a structure showing another embodiment of the present invention in which the high resistance element in FIG. 3 is improved. FIG. 39,40...p - area, 41,42...n-area, 43,44,45...p-area, 46,47,
48, 49...n + area.

Claims (1)

【特許請求の範囲】[Claims] １ ｐ形半導体基板上に、ｎ形エピタキシヤル層
よりなりｎ形並びにｐ形埋込領域を有するPNP
トランジスタ形成領域、前記ｎ形エピタキシヤル
層よりなりｎ形埋込領域を有する縦型NPNトラ
ンジスタのコレクタ領域及び高抵抗素子の島領域
を形成し、前記PNPトランジスタ形成領域及び
前記高抵抗素子の島領域にそれぞれ前記ｐ形埋込
領域よりも低濃度の前記PNPトランジスタのｐ
形コレクタ領域及び前記高抵抗素子のｐ形低濃度
領域をイオン注入で形成し、前記PNPトランジ
スタのコレクタ領域及び前記高抵抗素子のｐ形低
濃度領域にそれぞれ前記PNPトランジスタのコ
レクタ領域よりも高濃度で表面から下方に向かつ
て濃度が下がる濃度勾配を有するｎ形ベース領域
及び前記高抵抗素子の高抵抗領域をイオン注入で
形成し、前記ｎ形ベース領域、前記NPNトラン
ジスタのコレクタ領域にそれぞれ前記ｎ形ベース
領域よりも高濃度の前記PNPトランジスタのｐ
形エミツタ領域及び前記NPNトランジスタのｐ
形ベース領域を形成し、前記ｎ形ベース領域、前
記NPNトランジスタのベース領域及び前記高抵
抗領域にそれぞれｎ形ベースコンタクト領域、前
記NPNトランジスタのｎ形エミツタ領域及び高
抵抗素子のコンタクト領域を形成することを特徴
とする半導体集積回路装置の製造方法。1 PNP consisting of an n-type epitaxial layer and having n-type and p-type buried regions on a p-type semiconductor substrate
a transistor forming region, a collector region of a vertical NPN transistor having an n-type buried region made of the n-type epitaxial layer, and an island region of a high resistance element; p of the PNP transistor, which has a lower concentration than the p-type buried region, respectively.
A collector region of the PNP transistor and a p-type low concentration region of the high resistance element are formed by ion implantation. An n-type base region having a concentration gradient that decreases downward from the surface and a high-resistance region of the high-resistance element are formed by ion implantation, and the n-type base region and the collector region of the NPN transistor are respectively formed with the n-type base region and the high-resistance region of the high-resistance element. p of the PNP transistor with a higher concentration than the shaped base region
type emitter region and p of the NPN transistor
forming a base region, and forming an n-type base contact region, an n-type emitter region of the NPN transistor, and a contact region of the high-resistance element in the n-type base region, the base region of the NPN transistor, and the high-resistance region, respectively. A method of manufacturing a semiconductor integrated circuit device, characterized in that:
JP57095334A 1982-04-19 1982-06-02 Semiconductor integrated circuit device Granted JPS58212158A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP57095334A JPS58212158A (en) 1982-06-02 1982-06-02 Semiconductor integrated circuit device
EP83103726A EP0093304B1 (en) 1982-04-19 1983-04-18 Semiconductor ic and method of making the same
DE8383103726T DE3361832D1 (en) 1982-04-19 1983-04-18 Semiconductor ic and method of making the same
US07/124,423 US4826780A (en) 1982-04-19 1987-11-23 Method of making bipolar transistors
US07/295,380 US5066602A (en) 1982-04-19 1989-01-10 Method of making semiconductor ic including polar transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57095334A JPS58212158A (en) 1982-06-02 1982-06-02 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS58212158A JPS58212158A (en) 1983-12-09
JPH033953B2 true JPH033953B2 (en) 1991-01-21

Family

ID=14134811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57095334A Granted JPS58212158A (en) 1982-04-19 1982-06-02 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS58212158A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61242065A (en) * 1985-04-19 1986-10-28 Sanyo Electric Co Ltd Manufacture of complementary type transistor
JPS63122161A (en) * 1986-11-12 1988-05-26 Hitachi Ltd Manufacture of semiconductor integrated circuit device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS515973A (en) * 1974-07-04 1976-01-19 Nippon Electric Co

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS515973A (en) * 1974-07-04 1976-01-19 Nippon Electric Co

Also Published As

Publication number Publication date
JPS58212158A (en) 1983-12-09

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