JPS61242065A - Manufacture of complementary type transistor - Google Patents
Manufacture of complementary type transistorInfo
- Publication number
- JPS61242065A JPS61242065A JP60084831A JP8483185A JPS61242065A JP S61242065 A JPS61242065 A JP S61242065A JP 60084831 A JP60084831 A JP 60084831A JP 8483185 A JP8483185 A JP 8483185A JP S61242065 A JPS61242065 A JP S61242065A
- Authority
- JP
- Japan
- Prior art keywords
- region
- collector
- base
- island
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 230000000295 complement effect Effects 0.000 title claims description 10
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 abstract description 2
- 239000006185 dispersion Substances 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- 238000000926 separation method Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000009795 derivation Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8228—Complementary devices, e.g. complementary transistors
- H01L21/82285—Complementary vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
Abstract
Description
【発明の詳細な説明】
（イ） 産業上の利用分野
本発明は相補型トランジスタの製造方法、特に特性の良
好な縦型ＰＮＰトランジスタを有する相補型トランジス
タの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing a complementary transistor, and particularly to a method for manufacturing a complementary transistor having a vertical PNP transistor with good characteristics.
（ロ）従来の技術
従来の相補型トランジスタの製造方法を第２図Ａ乃至第
２図Ｅを参照して詳述する。(B) Prior Art A conventional method for manufacturing complementary transistors will be described in detail with reference to FIGS. 2A to 2E.
先ず第２図Ａに示す如く、Ｐ型の半導体基板６９表面に
予定の第１および第２島領域と対応する部分に夫々Ｎ＋
型の埋め込み層６２（至）を拡散して形成し、埋め込み
層国（ト）を囲む様にＰ＋型の上下分離領域（財）の下
拡散を行う。更に第１島領域の埋め込み層Ｏ２上にはＰ
＋型のコレクタ埋め込み層（至）を重畳して拡散する。First, as shown in FIG. 2A, N+ is applied to the surface of the P-type semiconductor substrate 69 at portions corresponding to the planned first and second island regions.
A type buried layer 62 (to) is formed by diffusion, and diffusion is performed under a P+ type upper and lower separation region (goods) so as to surround the buried layer country (g). Furthermore, P is formed on the buried layer O2 of the first island region.
A + type collector buried layer (to) is superimposed and diffused.
次に第２図Ｂに示す如く、基板Ｃ３１）表面にＮ型のエ
ピタキシャル層０６）ヲ成長させる。このとき埋め込み
層Ｏ２（ト）、コレクタ埋め込み層（至）および上下分
離領域（財）の下拡散は上下方向に拡散され、所定の巾
を有する埋め込み層（３祁紳レクタ埋め込み層（至）を
形成している。Next, as shown in FIG. 2B, an N-type epitaxial layer 06) is grown on the surface of the substrate C31). At this time, the buried layer O2 (T), the collector buried layer (T), and the bottom diffusion of the upper and lower separation regions (T) are diffused in the vertical direction, and the buried layer (3) with a predetermined width is formed. is forming.
次に第２図Ｃに示す如く、エピタキシャル層（至）表面
より上下分離領域（ロ）の下拡散と第１の島領域０７）
にコレクタ導出領域Ｃ１ｌを同時に拡散し、上下分離領
域（２）を連結させてエピタキシャル層（ト）”ｋＰＮ
分離し第１および第２の島領域ＣＭａｗ形成する。Next, as shown in FIG. 2C, from the surface of the epitaxial layer (to), the upper and lower isolation regions (b) are diffused and the first island region 07) is formed.
The collector lead-out region C1l is simultaneously diffused into
The first and second island regions CMaw are separated.
またコレクタ導出領域ＯＩは第１の島領域０７）のＰＮ
Ｐトランジスタのコレクタ埋め込み層（ハ）まで達し両
者で共同してエピタキシャル層（至）を完全に取す囲ん
でＰＮＰ ）ランジスタのベース領域顛を形成する。In addition, the collector derivation area OI is the PN of the first island area 07).
The base region of the PNP transistor is formed by reaching the collector buried layer (c) of the P transistor and completely enclosing the epitaxial layer (c) together.
次に第２図りに示す如く、エピタキシャル層（至）表面
よりボロンを選択拡散し、第１の島領域Ｃ３７）のベー
ス領域（ト）表面にＰＮＰ）ランジスタのエミッタ領域
０υを形成し、第２の島領域（至）にはＮＰＮ）ランジ
スタのベース領域（４２を同時に形成する。Next, as shown in the second diagram, boron is selectively diffused from the surface of the epitaxial layer (to) to form an emitter region 0υ of the PNP transistor on the surface of the base region (T) of the first island region C37). At the same time, a base region (42) of an NPN transistor is formed in the island region (toward).
最後に第２図Ｅに示す如く、第１の島領域Ｇηのベース
領域（４０表面にＮ＋型のベースコンタクト領域（４３
ヲ形成し、同時に第２の島領域（至）のベース領域（４
２表面にＮＰＮ ）ランジスタのエミッタ領域（４滲と
エピタキシャル層間表面にコレクタコンタクト領域Ｇ！
りを形成する。Finally, as shown in FIG. 2E, an N+ type base contact region (43) is formed on the base region (40) of the first island region Gη.
At the same time, the base region (4) of the second island region (to) is formed.
2 NPN on the surface) Emitter region of the transistor (4) Collector contact region on the surface between the epitaxial layer G!
form a ridge.
以上に詳述した従来の方法では縦型ＰＮＰトランジスタ
とＮＰＮトランジスタとを同一チップ内に集積化で営る
。なお斯る縦型ＰＮＰ ）ランジスタの製造方法は例え
ば、特開昭５９−１７２７３８号公報等に示されている
。In the conventional method detailed above, a vertical PNP transistor and an NPN transistor are integrated in the same chip. A method for manufacturing such a vertical PNP transistor is disclosed, for example, in Japanese Patent Application Laid-Open No. 172738/1983.
（／→ 発明が解決しようとする問題点しかしながら従
来の相補型トランジスタの製造方法では、縦型ＰＮＰ
）ランジスタのベース領域（４０がエピタキシャル層（
至）で形成されるので、均一ベースで且つベース巾を狭
くできない欠点があった。このため縦型ＰＮＰ）ランジ
スタの利得帯域中種（ｆ？）が高くできず、またエピタ
キシャル層（至）の膜厚のばらつきによりｈ□がばらつ
く欠点となっていた。(/→ Problems to be solved by the invention However, in the conventional manufacturing method of complementary transistors, vertical PNP
) The base region of the transistor (40 is the epitaxial layer (
Since the base is formed with a uniform base and the width of the base cannot be narrowed. For this reason, the vertical type PNP) transistor cannot have a high gain band width (f?), and also has the disadvantage that h□ varies due to variations in the thickness of the epitaxial layer.
（ロ）問題点を解決するための手段
本発明は断点に鑑みてなされ、縦型ＰＮＰ）ランジスタ
をイオン注入によるコレクタ領域（９）およヒヘース領
域α９で形成することにより縦型ＰＮＰトランジスタの
特性を改善し且つＮＰＮ ）ランジスタの特性を改善す
る相補型トランジスタの製造方法を実現するものである
。(b) Means for Solving the Problems The present invention has been made in view of the above points, and the vertical PNP transistor is formed by ion implantation using the collector region (9) and the heath region α9. The present invention provides a method for manufacturing a complementary transistor that improves the characteristics and improves the characteristics of an NPN transistor.
（ホ）作用
本発明に依れば縦型ＰＮＰ ）ランジスタを二重拡散型
に形成できるので縦型ＰＮＰ ）ランジスタの特性を大
巾に改善できるととも′ＩＩｃＮＰＮ）ランジスタのＶ
Ｃ，（、□？）も低減できるのである。(e) Effects According to the present invention, the characteristics of the vertical PNP transistor can be greatly improved because the transistor can be formed into a double diffusion type.
C, (,□?) can also be reduced.
四 実施例
本発明に依る相補型トランジスタの製造方法を第１図人
乃至第１図Ｈな参照して詳述する。4. Embodiment A method of manufacturing a complementary transistor according to the present invention will be described in detail with reference to FIGS.
本発明の第１の工程は、Ｐ型のシリコン半導体基板（１
１表面の予定の第１およびｆｓ２の島領域＋２１（３１
の底面となる部分にＮ 型の埋め込み層（４１（５１を
形成し、第１の島領域（２）の埋め込み層（４）上にＰ
＋型のコレクタ領域
Ｎ型のエピタキシャル層（７）を積層することにある（
第１図人および第１図Ｂ参照）。The first step of the present invention is a P-type silicon semiconductor substrate (1
1 surface planned first and fs2 island area +21 (31
An N-type buried layer (41 (51) is formed on the bottom surface of the
The purpose is to stack an N-type epitaxial layer (7) in the +-type collector region (
(See Figure 1 Person and Figure 1B).
本工程では第１図人に示す如く基板（１）表面に選択的
にアンチモンを拡散してＮ 型の埋め込み層’ ＋４１
（５１を第１および第２の島領域＋２１（３１の底面と
なる部分に形成する。なお第１の島領域（２１の埋め込
み層（４）上にはボロンを拡散して縦型ＰＮＰトランジ
スタのコレクタ埋め込み層（６）を形成し、同時に各埋
め込み層（４１（５１ｙ囲む様に上下分離領域（８）の
下拡散も行う。In this process, as shown in Figure 1, antimony is selectively diffused onto the surface of the substrate (1) to form an N-type buried layer'+41.
(51 is formed on the bottom surface of the first and second island regions +21 (31). Boron is diffused on the buried layer (4) of the first island region (21) to form a vertical PNP transistor. A collector buried layer (6) is formed, and at the same time, diffusion is also performed under the upper and lower isolation regions (8) so as to surround each buried layer (41 (51y)).
次に第１図Ｂに示す如く、基板（１）上にエピタキシャ
ル層（７）を周知のエピタキシャル技術によって約７μ
ｍ厚に成長させ、この際に埋め込み層（４１（５）コレ
クタ埋め込み層（６）および上下分離領域（８）の下拡
散を上下方向に拡散させ所定の巾の埋め込み層＋４１（
５１およびＰＮＰトランジスタのコレクタ埋め込み層（
６）を形成している。Next, as shown in FIG. 1B, an epitaxial layer (7) of about 7 μm is formed on the substrate (1) by a well-known epitaxial technique.
m thickness, and at this time, the bottom diffusion of the buried layer (41(5)), the collector buried layer (6), and the vertical separation region (8) is diffused in the vertical direction to form a buried layer (41(5)) with a predetermined width.
51 and the collector buried layer of the PNP transistor (
6).
本発明の第２の工程は、第１の島領域（２１表面からＰ
型を与える不純物をイオン注入し、コレクタ埋め込み層
（６）まで達するＰｉのコレクタ領域（９）を形成する
ことにある（第１図Ｃ参照）。The second step of the present invention is to remove P from the first island region (21 surface).
The purpose is to form a Pi collector region (9) that reaches the collector buried layer (6) by ion-implanting impurities that provide a type (see FIG. 1C).
このイオン注入はボロンンドーズ量１０１３〜１０１′
ｃｒｒＬ−”で加速電圧８０〜２００Ｋｅ■で行い、第
１の島領域（２）のコレクタ埋め込み層（６）上のエピ
タキシャル層（７）表面に不純物を選択的に注入した後
約２〜３μの深さドライブインさせて、コレクタ埋め込
み層（６）まで到達させる。This ion implantation has a boron dose of 1013 to 101'
After selectively implanting impurities into the surface of the epitaxial layer (7) on the collector buried layer (6) of the first island region (2) by applying an accelerating voltage of 80 to 200 Ke, The depth is driven in to reach the collector buried layer (6).
なお本工程では第２の島領域（３）にはイオン注入を行
なわない。Note that in this step, ion implantation is not performed in the second island region (3).
本工程で第１の島領域（２）に縦型ＰＮＰ ）ランジス
タのコレクタ領域（９）を拡散することにより、縦ＷＰ
ＮＰ）ランジスタのコレクタ領域（９）の不純物濃度を
高く設定できる。In this step, by diffusing the collector region (9) of the vertical PNP transistor into the first island region (2), the vertical WP
The impurity concentration of the collector region (9) of the NP) transistor can be set high.
本発明の第３の工程は、第１の島領域（２）のコレクタ
領域（９）表面にＮ型のベース領域（ＩＯを形成し且つ
第２の島領域（３）にコレクタ導出領域任Ｊを同時に形
成することにある（第１図り参照）。The third step of the present invention is to form an N-type base region (IO) on the surface of the collector region (9) of the first island region (2), and to form a collector lead-out region J in the second island region (3). (See first diagram).
本工程では第１の島領域（２）のコレクタ領域（９）表
面と第２の島領域（３）表面の一部とに同時にリンケイ
オン注入する。このイオン注入はリンをドーズ量１０１
５〜１０１？ぼ−！で加速電圧６０〜１００ＫｅＶで行
い、深さ約１μにドライブインする。この結果第１の島
領域（２）のコレクタ領域（９）表面には縦型ＰＮＰ
）ランジスタを構成するＮ型ベース領域（１（ｌが形成
され、同時に第２の島領域（３）表面の一部にはＮＰＮ
）ランジスタのコレクタ領域にＮ型のコレクタ導出領
域（１１１が形成される。In this step, Rinkei ions are simultaneously implanted into the surface of the collector region (9) of the first island region (2) and a part of the surface of the second island region (3). This ion implantation uses phosphorus at a dose of 101
5-101? Bo-! It is performed at an accelerating voltage of 60 to 100 KeV, and the drive-in is performed to a depth of about 1 μ. As a result, vertical PNPs are formed on the surface of the collector region (9) of the first island region (2).
) is formed on the N-type base region (1 (l) constituting the transistor, and at the same time NPN is formed on a part of the surface of the second island region (3).
) An N-type collector lead-out region (111) is formed in the collector region of the transistor.
上述した第３の工程後、第１図Ｅに示す如く、エピタキ
シャル層（７）表面より上下分離領域（８）の１拡ｔｌ
ＰＮＰ）ランジスタのコレクタ導出領域（１２１を同時
に拡散し、上下分離領域（８）を連結させてエピタキシ
ャル層（７）をＰＮ分離して、第１の島領域（２）と第
２の島領域（３）とを電気的に分離する。またコレクタ
導出領域ａｚはＰＮＰ）ランジスタのコレクタ埋め込み
層（６）まで達し、コレクタ導出領域σ２はコレクタ領
域（９）全周を囲んでいろ。After the third step described above, as shown in FIG.
PNP) The collector lead-out region (121) of the transistor is simultaneously diffused, the upper and lower isolation regions (8) are connected, and the epitaxial layer (7) is separated into PN regions to form the first island region (2) and the second island region (2). 3).The collector lead-out region az should reach the collector buried layer (6) of the PNP transistor, and the collector lead-out region σ2 should surround the entire periphery of the collector region (9).
本発明の第４の工程は、第１の島領域（２）のベース領
域αα表面にＰＪのエミッタ領域αりを形成し且つ第２
の島領域（３）表面にＰ型のベース領域α４を形成する
ことにある（第１図Ｃ参照）。The fourth step of the present invention is to form an emitter region α of PJ on the surface of the base region αα of the first island region (2), and to form a second
The purpose is to form a P-type base region α4 on the surface of the island region (3) (see FIG. 1C).
本工程でＰＮＰ ）ランジスタは完成され、ベース領域
ＱＱＩとエミッタ領域０の二重拡散構造な採るので縦型
ＰＮＰ ）ランジスタのベース巾のばらつきが二重拡散
型のＮＰＮ）ランジスタとほぼ同等になる。なお本工程
でコレクタ導出領域α２表面に重畳してベース拡散して
コレクタコンタクト領域（１５１を形成しても良い。In this step, the PNP transistor is completed, and since it adopts a double-diffused structure of the base region QQI and the emitter region 0, the variation in base width of the vertical PNP transistor is almost the same as that of the double-diffused NPN transistor. Note that in this step, the collector contact region (151) may be formed by base diffusion overlapping the surface of the collector lead-out region α2.
本発明の第５の工程は、第２の島領域（３）のベース領
域０４表面にＮ＋型のエミッタ領域α６１を形成するこ
とにある（第１図Ｃ参照）。The fifth step of the present invention is to form an N+ type emitter region α61 on the surface of the base region 04 of the second island region (3) (see FIG. 1C).
本工程ではＮＰＮ）ランジスタを形成するとともに、第
１の島領域（２）のベース領域００表面にベースコンタ
クト領域αηを形成し、第２の島領域（３）のコレクタ
導出領域α９表面にコレクタコンタクト領域０秒を形成
している。In this step, an NPN) transistor is formed, and a base contact region αη is formed on the surface of the base region 00 of the first island region (2), and a collector contact region is formed on the surface of the collector lead-out region α9 of the second island region (3). A region of 0 seconds is formed.
本発明の最終工程は、周知の蒸着技術により蒸着アルミ
ニウムで各電極を形成することにある（第１図Ｃ参照）
。The final step of the invention is to form each electrode with vapor-deposited aluminum by well-known vapor deposition techniques (see Figure 1C).
.
本工程ではエピタキシャル層（７）表面を被覆するシリ
コン酸化膜住９にコンタクト孔を形成し、第１の島領域
（２）に形成した縦をＰＮＰ）ランジスタのコレクタコ
ンタクト領域（１５１のベースコンタクト領域αηおよ
びエミッタ領域αりに夫々オーミック接触するコレクタ
電極鶴、１ベース電極ｃ２Ｂおよびエミッタ電極のを形
成し、第２の島領域（３）に形成したＮＰＮ）ランジス
タのコレクタコンタクト領域αＳベース領域Ｌ４および
エミッタ領域α０に夫々オーミック接触するコレクタ電
極（ハ）、ベース電極０４）およびエミッタ電極（ハ）
を形成している。In this step, a contact hole is formed in the silicon oxide film layer 9 covering the surface of the epitaxial layer (7), and the collector contact region (base contact region of 151) of the vertical PNP transistor formed in the first island region (2) is formed. A collector electrode, a first base electrode c2B, and an emitter electrode are formed in ohmic contact with αη and emitter region α, respectively, and the collector contact region αS base region L4 and Collector electrode (c), base electrode 04) and emitter electrode (c), each in ohmic contact with emitter region α0
is formed.
斯上した本発明方法に依れば、二重拡散型の縦型ＰＮＰ
）ランジスタとＮＰＮ）ランジスタを同一チップ内に効
率良く集積化できるのである。According to the method of the present invention described above, double-diffused vertical PNPs
) transistors and NPN) transistors can be efficiently integrated on the same chip.
（ト１ 発明の効果
本発明に依れば縦型ＰＮＰ ）ランジスタを二重拡散型
の製造方法にできるので、従来の縦型ＰＮＰトランジス
タの均一ベース構造から拡散ベース構造にできる利点を
有する。この結果ベース巾はベース領域（１（ｌとエミ
ッタ領域旺３の拡散により制御され、大巾にベース巾を
狭くでき且つベース巾のばらつきを低減できる。これに
より高ｆＴ の縦型ＰＮＰ ）ランジスタを同一チッ
プ内に容易に集積化できる。(1) Effects of the Invention According to the present invention, a vertical PNP transistor can be manufactured using a double-diffusion type manufacturing method, so there is an advantage that the uniform base structure of the conventional vertical PNP transistor can be changed to a diffused base structure. As a result, the base width is controlled by the diffusion of the base region (l) and the emitter region (3), making it possible to significantly narrow the base width and reduce variations in the base width. Can be easily integrated into the same chip.
また本発明では二重拡散屋の縦型ＰＮＰ ）ランジスタ
とＮＰＮ ）ランジスタとをお互いの工程を効率良く活
用することにより、極めて少ない工程数で実現できるの
である。即ち単独の工程は縦型ＰＮＰ ）ランジスタの
コレクタ拡散のみである。In addition, in the present invention, the vertical type PNP transistor and the NPN transistor of the double diffuser can be realized with an extremely small number of steps by efficiently utilizing each other's processes. That is, the only single step is the collector diffusion of the vertical PNP transistor.
更に本発明では縦型ＰＮＰ ）ランジスタの特性な大巾
に改善するとともにＮＰＮ）ランジスタもコレクタ導出
領域（Ｌｌ）によりＶｃｗ Ｃｓ４１ ）を大巾に低減
できる利点を有する。Furthermore, the present invention has the advantage that the characteristics of the vertical PNP transistor are greatly improved, and the NPN transistor also has the advantage of being able to greatly reduce Vcw Cs41 ) by the collector lead-out region (Ll).
更に本発明ではＮＰＮ）ランジスタのベース拡散および
エミッタ拡散をコントロー／ｌ／″ｆることにより縦型
ＰＮＰ ）ランジスタとＮＰＮ）う／ジスタのベース巾
を独立して制御でき、両者のトランジスタのｈ□をコン
トロールできる。Furthermore, in the present invention, by controlling the base diffusion and emitter diffusion of the NPN) transistor, the base widths of the vertical PNP) transistor and the NPN) transistor can be independently controlled. can be controlled.
第１図人乃至第１図Ｈは本発明に依る相補型トランジス
タの製造方法を説明する断面図、第２図人乃至第２図Ｅ
は従来の相補型トランジスタの製造方法を説明する断面
図である。
主な図番の説明
（１１は半導体基板、＋２１＋３）は第１および第２の
島領域、１４）ｉ５１は埋め込み層、（６）はコレクタ
埋め込み層、（７）はエピタキシャル膚、（８）は上下
分離領域、（９）は゛コレクタ領域、α〔はベース領域
、 （１１１はコレクタ導出領域、αＪはエミッタ領域
、α４１＆ｔベース領域、αｅはエミッタ領域である。Figures 1 to 1H are cross-sectional views illustrating the method of manufacturing complementary transistors according to the present invention, and Figures 2 to 2E
FIG. 1 is a cross-sectional view illustrating a conventional method for manufacturing a complementary transistor. Explanation of main figure numbers (11 is semiconductor substrate, +21+3) is first and second island region, 14) i51 is buried layer, (6) is collector buried layer, (7) is epitaxial skin, (8) is The upper and lower separation regions, (9) are the collector region, α is the base region, (111 is the collector derivation region, αJ is the emitter region, α41&t base region, and αe is the emitter region.
Claims (1)
領域底面に対応する部分に逆導電型の埋め込み層を形成
し且つ前記第１の島領域の埋め込み層に重畳して一導電
型のコレクタ埋め込み層を形成した後前記基板表面に逆
導電型のエピタキシャルを積層する工程、 前記第１の島領域表面から一導電型の不純物をイオン注
入し前記コレクタ埋め込み層まで達する様に拡散して一
導電型のトランジスタのコレクタ領域を形成する工程、 前記第１の島領域のコレクタ領域表面および前記第２の
島領域表面に逆導電型の不純物をイオン注入して拡散し
、一導電型トランジスタのベース領域および逆導電型ト
ランジスタのコレクタ導出領域を同時に形成する工程、 前記第１の島領域のベース領域表面および前記第２の島
領域表面に一導電型の不純物を拡散し、一導電型トラン
ジスタのエミッタ領域および逆導電量トランジスタのベ
ース領域を同時に形成する工程、 前記第２の島領域の前記ベース領域表面に逆導電型のエ
ミッタ領域を形成する工程とを具備することを特徴とす
る相補型トランジスタの製造方法。(1) A buried layer of an opposite conductivity type is formed on the surface of a semiconductor substrate of one conductivity type in a portion corresponding to the bottom surfaces of the first and second island regions, and is superimposed on the buried layer of the first island region to form a buried layer of one conductivity type. After forming a type collector buried layer, stacking an epitaxial layer of the opposite conductivity type on the surface of the substrate, ion-implanting impurities of one conductivity type from the surface of the first island region and diffusing them so as to reach the collector buried layer. forming a collector region of a transistor of one conductivity type by ion-implanting and diffusing impurities of opposite conductivity type into the collector region surface of the first island region and the surface of the second island region; simultaneously forming a base region and a collector lead-out region of a transistor of opposite conductivity type; diffusing impurities of one conductivity type into the base region surface of the first island region and the surface of the second island region; A complementary type comprising the steps of: simultaneously forming an emitter region of the transistor and a base region of the opposite conductivity transistor; and forming an emitter region of opposite conductivity type on the surface of the base region of the second island region. Method of manufacturing transistors.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60084831A JPS61242065A (en) | 1985-04-19 | 1985-04-19 | Manufacture of complementary type transistor |
| KR1019860002819A KR900000818B1 (en) | 1985-04-19 | 1986-04-14 | Complemental transistor manufacturing method |
| CN86102691.8A CN1004456B (en) | 1985-04-19 | 1986-04-19 | Semiconductor device and method of producing same |
| US07/119,668 US4780425A (en) | 1985-04-19 | 1987-11-12 | Method of making a bipolar transistor with double diffused isolation regions |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60084831A JPS61242065A (en) | 1985-04-19 | 1985-04-19 | Manufacture of complementary type transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61242065A true JPS61242065A (en) | 1986-10-28 |
Family
ID=13841716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60084831A Expired - Lifetime JPS61242065A (en) | 1985-04-19 | 1985-04-19 | Manufacture of complementary type transistor |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS61242065A (en) |
| KR (1) | KR900000818B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190004183A (en) * | 2017-07-03 | 2019-01-11 | 주식회사 케이이씨 | Transient voltage suppressor and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58212158A (en) * | 1982-06-02 | 1983-12-09 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JPS60194558A (en) * | 1984-03-16 | 1985-10-03 | Hitachi Ltd | Manufacture of semiconductor device |
-
1985
- 1985-04-19 JP JP60084831A patent/JPS61242065A/en not_active Expired - Lifetime
-
1986
- 1986-04-14 KR KR1019860002819A patent/KR900000818B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58212158A (en) * | 1982-06-02 | 1983-12-09 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| JPS60194558A (en) * | 1984-03-16 | 1985-10-03 | Hitachi Ltd | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20190004183A (en) * | 2017-07-03 | 2019-01-11 | 주식회사 케이이씨 | Transient voltage suppressor and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR900000818B1 (en) | 1990-02-17 |
| KR860008619A (en) | 1986-11-17 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |