JPS6230372A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the occupying are of an upper diffused layer and to improve the integration by diffusing a lower diffused layer of an elevationally separating region and a deep element diffused region from the surface of an epitaxial layer in the epitaxial layer, and then diffusing the upper diffused layer of the separating region. CONSTITUTION:An N<+> type buried layer 3, a collector buried layer 5 and a lower diffused layer 4' are formed on a substrate 1, and an epitaxial layer 2 is grown on the substrate 1. The entire substrate 1 is heated to diffuse the layers 4', 3 and 5, and a collector region 6 is simultaneously deeply diffused. Phosphorus ions are then implanted to the region 6 to form a base region 7, the upper diffused layer 4'' of an elevationally separating region 4 is diffused together with a collector leading region 8 from the layer 2 to couple the region 4, thereby P-N separating the layer 2. Since the layer 4'' becomes shallow and the diffusing time of the layer 4'' is shortened, the lateral diffusion of the layer 4'' can be largely reduced. Thus, the occupying area of the layer 2 can be largely reduced to remarkably improve the integration.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor integrated circuit, and particularly to a method of manufacturing a semiconductor integrated circuit incorporating a vertical PNP transistor.

(B) Prior Art A conventional method for manufacturing a semiconductor integrated circuit will be described in detail with reference to FIGS. 3A to 3.

First, as shown in FIG. 3A, P is used as a semiconductor substrate (41).
An N" type buried layer (
43) and a substrate (43) surrounding this buried layer (43).
41) Boron is deposited on the surface to form an upper diffusion layer (44') of the upper and lower separation regions (44).

Next, as shown in FIG. 3B, an N-type epitaxial layer (42) is grown on the substrate (41). On the surface of the epitaxial layer (42), boron is deposited at a position corresponding to the lower diffusion M (44') to form an upper diffusion layer (44'') of the upper and lower isolation regions (44).

Next, as shown in FIG. 3C, the substrate (41) is heated to form an epitaxial layer (
42), and connects the upper diffusion layer (44'') with the upper diffusion layer (44') to form an upper and lower separation region (44). This diffusion process is performed at approximately 1100°C for 3~ When the epitaxial layer (42) is 13μ thick, the upper diffusion layer (44'') is diffused to a depth of approximately 10μ, and the upper diffusion layer (44') is raised to a depth of approximately 5μ. ing.

Further, as shown in the third diagram, an island region (4) formed of an epitaxial layer (42) surrounded by a top and bottom separation region (44) is formed.
5) A P-type base region (46) and an N-type emitter region (47) are diffused on the surface, and a collector contact region (48) is formed on the surface of the island region (45) by emitter diffusion.

By the above process, the NPN transistor is formed into an island region〈45
) can be formed. Note that the method for separating the upper and lower parts is
It is known from Japanese Patent Publication No. 14015, Japanese Patent Publication No. 49-45629, etc.

Next, as shown in FIG. 4, the conventional vertical PNP transistor consists of an N-type epitaxial layer (52) grown on a P-type silicon semiconductor substrate (51), and an N1-type epitaxial layer (52) grown on a P-type silicon semiconductor substrate (51). The embedding layer (53) and this embedding layer (
A P+ type upper and lower separation region (54) penetrating the epitaxial layer (52) so as to completely surround the substrate (53) and the substrate (51).
A P+ type collector region (55) provided overlappingly on the buried layer (53), a P type collector lead-out region (56) reaching the collector region (55) from the surface of the epitaxial layer (52), and the collector region (55) and the collector lead-out region 56), and is completely surrounded by the epitaxial layer (56).
2) and the base region (57) formed in
57) P+ type emitter region (58) formed on the surface;
Oxide film (59) covering the surface of the epitaxial layer (52)
), a collector electrode (61), a base electrode (62) and an emitter which are in ohmink contact with the collector lead-out region (56), the base contact region (60) and the emitter region (58) through the electrode hole of this oxide film (59), respectively. electrode(
63). Such a vertical PNP transistor is disclosed, for example, in Japanese Patent Laid-Open No. 59-172738.

In the above-mentioned vertical PNP transistor, the active base region (57) is formed of the epitaxial layer (52), so the impurity concentration is low (l Q "cm-" or less) and the base width is wide, so that the gain band mass ( rT) is low.Furthermore, variations in the resistivity or thickness of the epitaxial layer (52) directly result in variations in the impurity concentration or base width of the active base region (57), resulting in variations in hFt of the vertical PNP transistor. There is a drawback that appears as follows.

FIG. 5 shows a vertical PNP transistor that has improved this drawback. This vertical PNP transistor consists of a P-type silicon semiconductor substrate (71) and an N layered on the substrate (71).
type epitaxial layer (72), N4 type embedding/I (73) provided on the substrate (71), and this embedding J
The epitaxial layer (72) completely surrounds i (73).
) and a P+ type collector region (74) provided on the buried layer (73).
5) and a P+ type collector lead-out region (76) that reaches from the surface of the epitaxial layer (72) to the collector region (75).
), collector area (75) and collector derivation area (76
) and formed of an epitaxial layer (72), a P1 type emitter region (78) provided on the surface of the base region (77), and a base region (77) formed on the surface of the base region (77). The formed N4 type base contact region (80), the oxide film (79) covering the epitaxial! (72) surface, and the collector lead-out region (76) base contact region through the electrode hole of this oxide film (79). A collector electrode (81), a base electrode (82), and an emitter electrode (83) are in ohmic contact with the base region (80) and the emitter region (78), respectively.
7) Consisting of an N-type ion implantation region (84) with a higher impurity concentration than the base region (77) provided on the surface.

According to the above structure, as is clear from the impurity concentration distribution characteristics shown in FIG. 6, an N-type ion implantation region (84) is formed on the surface side of the epitaxial layer (72) of the conventional base region. This ion implantation region (84) can be set to an impurity concentration approximately 10 times higher than that of the epitaxial layer (72), and the base region (77) is composed of the ion implantation region (84) and the epitaxial layer (72). Completely formed. For this reason, the impurity distribution in the base region (77) becomes lower in impurity concentration from the emitter region (78) toward the collector region (75>), so a drift 1 field is generated inside and the holes are accelerated. The fT of the vertical PNP transistor can be improved from the conventional 50M to 100Ml (Z).

Furthermore, even if the thickness and resistivity of the epitaxial layer (72) vary, the hFt of the vertical PNP transistor is almost determined by the depth of the ion implantation region (84), so the variation in h□ can be greatly affected by the ion implantation. Can be reduced. Specifically, the variation is about half or less of the conventional variation.

(c) Problems to be Solved by the Invention However, in the above-mentioned conventional method for manufacturing semiconductor integrated circuits using the upper and lower separation method, the diffusion time can be shortened compared to the upper separation method. Since the diffusion of the upper diffusion layer (44') and the upper diffusion layer (44') is performed at the same time, the upper diffusion layer (44') is
4') It was necessary to diffuse much deeper. For this reason, the diffusion time is as long as 3 to 4 hours, and the lateral diffusion of the upper diffusion layer (44'') is also large, and the area occupied by the upper diffusion layer (44'') on the surface of the epitaxial layer (42) is large, and the degree of integration is not much improved. There was a drawback that it could not be done.

Furthermore, in the improved conventional vertical PNP (PNP) run lister mentioned above, the epitaxial layer (72) has a base region (
77), the width of the base region (77) is large, making it impossible to further improve ft, and hFx tends to fluctuate due to variations in the thickness of the epitaxial layer (72). Impurity concentration is IQ”c
Since Tn-' is low, the collector-emitter saturation voltage ■. ,(
sat) becomes large, making it difficult to manufacture.

(d) Means for Solving the Problems The present invention was made in view of the above-mentioned drawbacks, and the upper diffusion layer of the upper and lower isolation regions and the deep element diffusion region from the surface of the epitaxial layer are diffused into the epitaxial layer, and then the upper and lower regions are separated. The present invention provides a method for manufacturing a semiconductor integrated circuit which greatly improves the conventional drawbacks by diffusing the upper diffusion layer of the region.

In addition, the present invention has been made in view of the drawbacks of conventional vertical PNP transistors, and is a vertical PNP transistor in which the base region and emitter region are double-diffused on the surface of the collector region, which is formed by ion implantation from the surface of the epitaxial layer and reaches the collector buried layer. A method of manufacturing a semiconductor integrated circuit incorporating the present invention is provided.

(E) Function According to the present invention, the upper diffusion layer of the upper and lower isolation regions is diffused after the upper diffusion layer of the upper and lower isolation regions and the element diffusion region are diffused sufficiently deeply into the epitaxial layer, so that the upper diffusion layer of the upper and lower isolation regions is diffused. The layer can be formed sufficiently shallow and the element diffusion region can be formed sufficiently deep.

As a result, the area occupied by the diffusion layer can be reduced, and the degree of integration can be improved.

Further, according to the present invention, since a manufacturing method is adopted in which the base region and the emitter region are double-diffused on the surface of the collector region, the base width can be narrowed and variations can be reduced.

(F) Embodiment A first embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention will be described in detail with reference to FIGS. 1A to 1F.

First, as shown in FIG. 1A, a P-type silicon substrate is used as a semiconductor substrate (1), and antimony is selectively deposited on the surface of the substrate (1) to form an N+ type buried layer (3).
on the buried layer (3) and on the buried layer <3>
Boron is deposited on the surface of the substrate (1) surrounding the substrate (1) to form a collector buried layer (5) and an upper diffusion layer (4') of the upper and lower separation regions (4).

Next, as shown in FIG. 1B, an N-type epitaxial layer (2) is grown on the substrate (1) to a thickness of about 7 μm. At this time, the buried layer (3), the collector buried layer (5), and the lower diffusion ff1 (4') of the upper and lower separation regions (4) are slightly diffused in the vertical direction, specifically, the upper diffusion of the upper and lower separation regions (4). Layer (4') and collector buried layer (5) are approximately 1.5
It increases by about μm. In this step, boron ions are selectively implanted into a region corresponding to the collector buried layer (5) on the surface of the epitaxial layer (2) to form one of the element diffusion regions.
A collector region (6) is attached. This ion implantation uses boron at a dose of I Q I S ~ l Q
It is carried out at I ficrn-1 and an acceleration voltage of 80 to 200 KeV.

Next, as shown in Figure 1C, the entire board (1) is
″C and upper diffusion layer (4°) of upper and lower separation region (4)
, the buried layer (3) and the collector buried layer (5) are raised and diffused into the epitaxial layer (2), and at the same time, the collector region (6) is deeply diffused into the epitaxial layer <2>. Specifically, the upper diffusion layer (4') and collector buried layer (5) of the upper and lower isolation regions (4) are raised approximately 5 μm from the bottom surface of the epitaxial layer (2), and the collector region (6) is raised from the epitaxial layer (2) by approximately 5 μm from the bottom surface. 2) Drive-in to a depth of approximately 4 μm from the surface. Therefore, the collector region (6) completely reaches the collector buried layer (5).

Next, as shown in the first diagram, phosphorus ions are implanted into the surface of the collector region (6) to form a base region (7). This ion implantation has a phosphorus dose of 1016 w l Q ”
cm-'' at an accelerating voltage of 60 to 100 KeV, and the base region (7) is attached to the surface of the collector region (6).

Next, as shown in FIG. 1E, the upper diffusion layer (4'') and the collector lead-out region (8) of the upper and lower isolation regions (4) are simultaneously diffused from the surface of the epitaxial layer (2) to form the upper and lower isolation regions (4). The epitaxial!
5), and the collector derivation region (8) surrounds the entire periphery of the collector region (6). Furthermore, by this diffusion, the base region (7) formed in the previous step is driven in to a thickness of about 2.5 μm.
It forms a base region (7) with a depth of .

This step is a characteristic step of the present invention, in which the upper and lower separation regions (4
) Since the upper diffusion layer (4") is diffused after the upper diffusion layer (4') is sufficiently lifted up, the depth of the upper diffusion layer (4") can be made shallow to about 3 μm, and the upper diffusion layer (4") can be shortened to 1 hour at approximately 1200°C. Therefore, the lateral diffusion of the upper diffusion layer (4") can be greatly reduced, and the diffusion time can be reduced to within approximately 3 μm from the peripheral edge of the diffusion hole. As a result, the surface area occupied by the upper diffusion layer (4'') can be greatly reduced.

Furthermore, as shown in FIG.
) and the collector contact region (10).

This diffusion is performed in the base diffusion process of the NPN transistor. Thereafter, the base contact region (11) is formed on the surface of the base region (7) by the emitter diffusion process of the NPN transistor.
> is formed. The emitter region (9) is formed to a depth of approximately 2 μm, and the base contact region (11) is formed to a depth of approximately 1.5 μm.

Next, a second embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention will be described in detail with reference to FIGS. 2A to 2F.

First, as shown in FIG. 2A, P is used as a semiconductor substrate (21).
Using a type silicon substrate, antimony is selectively deposited on the substrate (21) to form an N+ type buried layer (23).
) on the buried layer (23) and on the buried layer (23).
Boron is deposited on the surface of the substrate (21) surrounding the collector buried layer (25) and the upper and lower separation regions (23).
4) Lower diffusion Jim (24') is also performed.

Next, as shown in FIG. 2B, an epitaxial layer (22) is grown on the substrate (21) to a thickness of about 7 μm. Thereafter, the substrate (21) is heat-treated to diffuse the buried layer (23), the collector buried layer (25), and the upper diffusion layer (24') of the upper and lower separation region (24) in the vertical direction. a buried layer (23), a collector buried layer (2
5) Form. Specifically, the upper diffusion layer (24°) of the upper and lower isolation regions (24) is about 5 μm thick and the epitaxial layer (2
2) Crawling up from the bottom.

Subsequently, as shown in FIG. 2C, a collector region (26) is formed by ion implantation, which is a feature of the present invention. This ion implantation is performed with boron at a dose of 1013 to IQ"cm-2 and an acceleration voltage of 80 to 200 KeV. After the impurity ions are implanted into the surface of the epitaxial layer (22) on the collector buried layer (25), the impurity is implanted to a depth of about 4 μm. It is driven in to reach the collector buried layer (25).This drive-in is conveniently performed at the same time as the diffusion of the lower diffusion layer (24') of the upper and lower separation regions (24>) described above.

Further, phosphorus ions are implanted into the surface of the collector region (26) to form a base region (28). In this ion implantation, the phosphorus dose is 10'6 to IQ "an-" and the acceleration voltage is 60.
The base region (8) is formed by driving in to a depth of about 2.5 μm.

Note that it is convenient to drive in the base region (28) at the same time as the subsequent diffusion of the upper diffusion layer (24'') of the upper and lower separation regions (24).

Furthermore, as shown in the second diagram, the upper diffusion H (24'') of the upper and lower isolation regions (24) and the collector lead-out region (27) are simultaneously diffused from the surface of the epitaxial layer (22) to connect the upper and lower isolation regions (24). The epitaxial layer (22> is PN
To separate. In addition, this collector lead-out region (27) reaches the collector buried layer (25), and the collector lead-out region <2
7) surrounds the entire periphery of the collector region (26). Specifically, the upper diffusion layer (24'') can be diffused to a depth of about 3 μm by diffusion at about 1200° C. for 1 hour.

Furthermore, as shown in FIG. 2E, a region 31) is diffused into the emitter region (30) and the collector contact 1 on the surface of the base region (28) and the surface of the collector lead-out region (27). This diffusion is performed in the base diffusion step of the NPN)-run lister. After that, NPN is applied to the surface of the base region (28).
A base contact region (29) is formed in the emitter diffusion process of the L-run lister. Specifically, the base region (28) has a thickness of approximately 2.5 μm, and the emitter region (30) has a thickness of approximately 2.5 μm.
The μm1 base contact region (29) has been formed to a depth of approximately 1.5 μm.

Furthermore, as shown in FIG. 2F, a collector ttM (s3), a base electrode (34), and an emitter electrode (35) are formed of vapor-deposited aluminum using a well-known vapor deposition technique.

The vertical PNP l-run lister according to the manufacturing method of the present invention described above includes a P-type silicon semiconductor substrate (21) and an N-type epitaxial layer (22) laminated on the substrate (21).
) and an N+ type buried layer (2) provided on the substrate (21).
3), a P+ type upper and lower separation region (24) penetrating the epitaxial layer (22) so as to completely surround this buried layer (23), and a P'''' provided on the buried layer (23).
Embedding type collector! (25) and a P-type collector region (26) formed by ion implantation from the surface of the epitaxial layer (22) to the collector buried layer (25).
and a P+ type collector lead-out region (2) reaching from the epitaxial layer 22) surface to the collector buried layer <25).
7), an N-type base region (28) formed by ion implantation on the surface of the collector region (26), and a base region (28).
) N” type base contact region (2) formed on the surface
9), a P-type emitter region (30) formed on the surface of the base region (28), a P+-type collector contact region (31) formed superimposed on the surface of the collector lead-out region (27), and an epitaxial An oxide film (32) covering the surface of the layer (22) and contact holes formed in this oxide film (32) are used to connect the collector contact region (31), the base contact region (29), and the emitter region (30), respectively. It is composed of a collector electrode (33), a base electrode (34), and an emitter electrode (35) that are in contact with each other.

Such a vertical PNP transistor has an epitaxial layer (22
) is used as the collector region (26), which is entirely formed by ion implantation.
First, by double-diffusing the base region (28) and emitter region (30), a diffused base region and a base width with little variation are realized.

(G) Effects of the Invention According to the present invention, after the lower diffusion layer (4') of the upper and lower isolation regions (4) and the collector region (6) are sufficiently deep diffused, the upper and lower regions of the upper and lower isolation regions (4) are Since the diffusion layer (4") is diffused, the upper diffusion layer (4') of the upper and lower isolation regions (4) can be formed shallowly, and the upper diffusion layer (4') of the upper and lower isolation regions (4) can be formed shallowly.
'') can be suppressed to about 3 μm or less, the area occupied by the upper diffusion layer (4'') on the surface of the epitaxial layer (2) can be greatly reduced, and the degree of integration can be greatly improved.

Further, according to the present invention, the upper diffusion layer (4) of the upper and lower separation region (4)
Since the diffusion layer (4'') is much shallower than the lower diffusion layer (4''), the diffusion time of the upper diffusion layer (4'') of the upper and lower separation region (4) is shorter than the conventional 3''.
It can be drastically shortened from ~4 hours to about 1 hour. As a result, thermal stress and damage to the surface of the epitaxial layer (2) can be greatly reduced, a decrease in hFK at the time of a small current in the transistor can be prevented, and noise can be greatly reduced.

Further, according to the present invention, the base region (28) changes from the conventional uniform base structure formed by an epitaxial layer to a diffused base structure, thereby making it possible to generate a drift electric field.

Also, the base width is the base area (28) and the emitter area (3
Since the double diffusion structure of 0) can be controlled, the base width can be made much narrower than the conventional one, and the manufacturing variations can be greatly reduced. As a result, f? of the vertical PNP transistor of the present invention? It has the advantage of being able to greatly improve the current to about 200MH2.

Furthermore, according to the present invention, since the base region (28) and the emitter region (30) can be formed by double diffusion, the variation in the base width is much wider than in the conventional method in which the base width is formed with an epitaxial layer. It is possible to greatly reduce manufacturing variations in hFK.

Furthermore, according to the present invention, since the collector burying layer (25) can be sufficiently raised and diffused, the collector region (26) can be buried in the collector! (25), and since the collector region 26) is surrounded by the collector buried layer (25) and the collector lead-out region (27), the saturation voltage Vex(sat) can be greatly reduced.

[Brief explanation of drawings]

1A to 1F are cross-sectional views for explaining a first embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention, and FIGS. 2A to 2F are sectional views for explaining a second embodiment of the present invention. Sectional diagram to explain, 3rd
Figures A to 3 are cross-sectional views explaining the conventional method for manufacturing semiconductor integrated circuits, and Figures 4 and 5 are conventional vertical PN
FIG. 6 is a cross-sectional view illustrating the P l-run lister, and FIG. 6 is a characteristic diagram illustrating the impurity profile of the conventional vertical PNP transistor shown in FIG. (1) is a semiconductor substrate, (2) is an epitaxial layer, (3
) is the buried layer, (4) is the upper and lower separation region, (4') is the lower diffusion layer, (4'') is the upper diffusion layer, (5) is the collector buried layer, (6) is the collector region, (7) is the base area, (
9) is the emitter region, (21) is the semiconductor substrate, (22)
is an epitaxial layer, (23) is a buried layer, (24)
(24') is the lower diffusion layer, (24'') is the upper diffusion layer, (25) is the collector buried layer, (26) is the collector region, (28) is the base region, (30) is the emitter Applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Shizuo Sano Go to Figure 1 Figure 1 B - Figure 1 C Figure 1 Diagram 1 AF 1 AF Figure 2 A ζ Figure 2 B Fig. 2 C Fig. 2 D Fig. 2 E Fig. 2 F Fig. 3 A 44" 42 44" Fig. 3 C Fig. 4 Fig. 5

Claims (2)

[Claims] (1) A step of attaching a buried layer of an opposite conductivity type to the surface of a semiconductor substrate of one conductivity type, and attaching a lower diffusion layer of one conductivity type in an upper and lower separation region to the substrate surface surrounding the buried layer; a step of laminating an epitaxial layer of opposite conductivity type on the surface of the epitaxial layer; causing the buried layer and the diffusion layer below the upper and lower isolation regions to crawl up and diffuse into the epitaxial layer; and at the same time, to diffuse above the upper and lower isolation regions from the surface of the epitaxial layer; A semiconductor integrated circuit comprising the steps of: diffusing an element diffusion region deeper than the epitaxial layer; and diffusing an upper diffusion layer of one conductivity type in the upper and lower separation regions from the surface of the epitaxial layer to reach the lower diffusion layer. manufacturing method. (2) After forming a buried layer of the opposite conductivity type on the surface of a semiconductor substrate of one conductivity type and forming a collector buried layer of one conductivity type by overlapping the buried layer, an epitaxial layer of the opposite conductivity type is formed on the surface of the substrate. a step of stacking layers; a step of ion-implanting impurities of one conductivity type from the surface of the epitaxial layer and diffusing them to reach the collector buried layer to form a collector region of the transistor; and a step of ion-implanting impurities of the opposite conductivity type to the surface of the collector region. 1. A method for manufacturing a semiconductor integrated circuit, comprising: forming a base region of a transistor by implanting the base region; and forming an emitter region of the transistor by diffusing an impurity of one conductivity type into the surface of the base region.