JPS62216355A - Manufacture of semiconductor injection integrated logic circuit device - Google Patents
Manufacture of semiconductor injection integrated logic circuit deviceInfo
- Publication number
- JPS62216355A JPS62216355A JP61060014A JP6001486A JPS62216355A JP S62216355 A JPS62216355 A JP S62216355A JP 61060014 A JP61060014 A JP 61060014A JP 6001486 A JP6001486 A JP 6001486A JP S62216355 A JPS62216355 A JP S62216355A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- diffusion layer
- region
- diffusion
- diffused
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000002347 injection Methods 0.000 title abstract 2
- 239000007924 injection Substances 0.000 title abstract 2
- 238000009792 diffusion process Methods 0.000 claims abstract description 80
- 239000000758 substrate Substances 0.000 claims description 15
- 238000000926 separation method Methods 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 238000003892 spreading Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000009193 crawling Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体集積回路に組み込まれる半導体注入集積
論理回路装置（以下、ＩＩＬと称す）の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor implanted integrated logic circuit device (hereinafter referred to as IIL) that is incorporated into a semiconductor integrated circuit.
（ロ）従来の技術
従来のＩＩＬの製造方法を第２図（り乃至（ホ）を用い
て説明する。(B) Prior Art A conventional IIL manufacturing method will be explained with reference to FIGS.
先ず第２図（りに示す如く、半導体基板（１）としてＰ
型のシリコン基板を用い、基板（１）上に選択的にアン
チモン（Ｓｂ）をデポジットしてＮ＋型の埋込層（２）
を形成し、埋込層（２）を囲む基板（１）表面にはボロ
ン（Ｂ）をデポジットして上下分離領域（３）の下拡散
層（４）を形成する。First, as shown in Figure 2, P is used as the semiconductor substrate (1).
Using a type silicon substrate, antimony (Sb) is selectively deposited on the substrate (1) to form an N+ type buried layer (2).
Boron (B) is deposited on the surface of the substrate (1) surrounding the buried layer (2) to form a lower diffusion layer (4) of the upper and lower separation regions (3).
次に第２図（ロ）に示す如く、基板（１）全面に周知の
気相成長法によりＮ−型のエピタキシャル層（５）を所
定厚きに形成する。この時埋込層（２〉および軍拡散層
（４）は上下方向に若干拡散きれる。Next, as shown in FIG. 2(B), an N-type epitaxial layer (5) is formed to a predetermined thickness over the entire surface of the substrate (1) by a well-known vapor phase growth method. At this time, the buried layer (2>) and the military diffusion layer (4) are slightly diffused in the vertical direction.
次に第２図（ハ）に示す如く、エピタキシャル層（５）
表面に選択的にボロン（Ｂ）をイオン注入し、ベース領
域（６）を付着する。このイオン注入はドーズ量１０″
〜ＩＱ″ｃｍ−”で加速電圧８０〜１００ＫｅＶで行う
。Next, as shown in FIG. 2(c), an epitaxial layer (5) is formed.
A base region (6) is deposited by selectively implanting boron (B) into the surface. This ion implantation has a dose of 10''
~IQ"cm-" and an accelerating voltage of 80 to 100 KeV.
次に第２図（ニ）に示す如く、エピタキシャル層（５）
表面から上下分離領域（３）の上拡散層（７）を約１２
００℃、３〜４時間で拡散し、同時に埋込層（２）、軍
拡散層（４）及びベース領域（６〉をドライブインする
。この工程で上拡散層（７）は軍拡散層（４）と連結し
てエピタキシャル層（５）を接合分離し、ベース領域（
６）は濃度差があるために上拡散層（７）より浅く形成
される。具体的には、エピタキシャル層（５）の厚みを
１３μｍとすると上拡散層（７）は約９μｍの深さに拡
散され、軍拡散層（４）は約７μｍの深さにはい上げら
れる。またベース領域（６）は約４μｍの深さに拡散さ
れ、埋込層（２）は約３μｍはい上げられる。Next, as shown in FIG. 2(d), an epitaxial layer (5) is formed.
The upper diffusion layer (7) of the upper and lower separation regions (3) from the surface is about 12
00°C for 3 to 4 hours, and at the same time drive in the buried layer (2), military diffusion layer (4), and base region (6). In this process, the upper diffusion layer (7) becomes the military diffusion layer ( 4), the epitaxial layer (5) is junction-separated, and the base region (
6) is formed shallower than the upper diffusion layer (7) due to the difference in concentration. Specifically, when the thickness of the epitaxial layer (5) is 13 μm, the upper diffusion layer (7) is diffused to a depth of about 9 μm, and the lower diffusion layer (4) is raised to a depth of about 7 μm. The base region (6) is also diffused to a depth of about 4 μm, and the buried layer (2) is raised by about 3 μm.
次に第２図（ホ〉に示す如く、拡散深さ約２μｍのＰ型
のインジェクタ領域（８）およびベースコンタクト領域
（９）を同時に拡散し、続いて拡散深き約１．５μｍの
Ｎ”型コレクタ領域（１０）を形成する。尚インジェク
タ領域（８）およびベースコンタクト領域（９）はＮＰ
Ｎトランジスタのベース拡散工程で形成し、コレクタ領
域り１０）はＮＰＮ トランジスタのエミッタ拡散工程
で形成する。Next, as shown in FIG. 2 (e), the P-type injector region (8) and base contact region (9) with a diffusion depth of approximately 2 μm are simultaneously diffused, and then the N” type with a diffusion depth of approximately 1.5 μm. A collector region (10) is formed.The injector region (8) and base contact region (9) are NP.
The collector region 10) is formed in the base diffusion process of the NPN transistor, and the collector region 10) is formed in the emitter diffusion process of the NPN transistor.
この様に形成したＩＩＬにおいては、活性ベースがイオ
ン注入により形成した低濃度のベース領域（６）で形成
されるので、高い逆方向電流増幅率逆βが得られ、且つ
コレクタ領域（１０）のばらつきによる逆βのばらつき
を抑えられる。In the IIL formed in this way, since the active base is formed by the low concentration base region (6) formed by ion implantation, a high reverse current amplification factor inverse β can be obtained, and the collector region (10) Variations in inverse β due to variations can be suppressed.
尚斯るＩＩＬは、例えば特願昭６０−２０９３８７号に
記載されている。Such IIL is described, for example, in Japanese Patent Application No. 60-209387.
（ハ）発明が解決しようとする問題点
しかしながら、衛士した従来の製造方法では上下分離領
域（３）の上拡散層＜７）と軍拡散層（４）及びベース
領域（６）を同時にドライブインしている。(c) Problems to be solved by the invention However, in the conventional manufacturing method, the upper diffusion layer (<7) of the upper and lower separation regions (3), the upper diffusion layer (4), and the base region (6) are simultaneously driven in. are doing.
するとこの拡散工程では、イオン注入による低濃３一
度のベース領域（６）を十分に深く拡散するために上拡
散層り７）をかなり深く形成しなければならない。さら
に上拡散Ｈ（７）と軍拡散層（４〉とでは上拡散層（７
）の方が拡散に供給される不純物が多い状態、具体的に
言えばボロン（Ｂ）を多量に含む拡散源膜を付着したま
まの状態で拡散するため、上拡散層（７）の方が軍拡散
層り４）よりかなり深く拡散されてしまう。In this diffusion step, the upper diffusion layer 7) must be formed quite deep in order to sufficiently diffuse the base region (6) with low concentration by ion implantation. Furthermore, the upper diffusion layer (7) is different from the upper diffusion layer (7) and the military diffusion layer (4>).
), more impurities are supplied for diffusion, specifically, the upper diffusion layer (7) is better because it diffuses with the diffusion source film containing a large amount of boron (B) still attached. It will be spread much deeper than the military diffusion layer 4).
従って上拡散層（７）の横方向拡散が大きく、エピタキ
シャル層（５）表面での占有面積が大で集積度を向上で
きない欠点があった。Therefore, the lateral diffusion of the upper diffusion layer (7) is large, and the area occupied on the surface of the epitaxial layer (5) is large, making it impossible to improve the degree of integration.
（ニ）問題点を解決するための手段
本発明は衛士した欠点に鑑みてなきれ、あらかじめ軍拡
散層り４）をエピタキシャルＮ（５）の厚みの半分以上
はい上げて拡散し、同時に低濃度のベース領域（６〉を
ドライブインした後に上拡散層（７）を形成することに
より、従来の欠点を大幅に改善したＩＩＬの製造方法を
提供するものである。(d) Means for solving the problem In view of the disadvantages of the present invention, the present invention has been developed by first increasing the diffusion layer 4) by more than half the thickness of the epitaxial N (5) and diffusing it, while at the same time having a low concentration. By forming the upper diffusion layer (7) after driving in the base region (6) of the IIL, the present invention provides a method of manufacturing an IIL that greatly improves the conventional drawbacks.
（ホ〉作用
本発明によれば、軍拡散層（４）をエビタキシャル層（
５）の厚みの半分以上はい上げて拡散しておくので、上
拡散Ｎ（７）を浅く形成し、その横方向拡散を抑えて集
積度を向上できる。さらにベース領域（６）は下拡散Ｍ
（４）と同時にドライブインするので、所定の特性が得
られるように十分に深く形成できる。(E) Effect According to the present invention, the military diffusion layer (4) is replaced by the epitaxial layer (
Since half or more of the thickness of 5) is raised and diffused, the upper diffusion N (7) can be formed shallowly, and its lateral diffusion can be suppressed to improve the degree of integration. Furthermore, the base region (6) has a lower diffusion M
(4) Since it is driven in at the same time, it can be formed sufficiently deep to obtain predetermined characteristics.
くべ）実施例
以下本発明によるＩＩＬの製造方法を第１図（イ）乃至
第１図（へ）を用いて詳細に説明する。EXAMPLE 1 The method for manufacturing IIL according to the present invention will be explained in detail with reference to FIGS. 1(A) to 1(F).
先ず第１図（イ）に示す如く、半導体基板（１）として
Ｐ型のシリコン基板を用い、基板（１）上に選択的にア
ンチモン（Ｓｂ）をデポジットしてＮ十型の埋込層（２
）を形成し、埋込層（２）を囲む基板（１）表面にはボ
ロン（Ｂ）をデポジットして上下分離領域（３）の軍拡
散層（４）を形成する。First, as shown in FIG. 1(A), a P-type silicon substrate is used as the semiconductor substrate (1), and antimony (Sb) is selectively deposited on the substrate (1) to form an N0-type buried layer ( 2
) is formed, and boron (B) is deposited on the surface of the substrate (1) surrounding the buried layer (2) to form a military diffusion layer (4) in the vertical separation region (3).
次に第１図（ロ）に示す如く、基板（１）全面に周知の
気相成長法によりＮ−型のエピタキシャル層（５）を７
μｍ厚に形成する。この時埋込層（２）および軍拡散層
り４）は上下方向に若干拡散される。Next, as shown in FIG. 1(b), an N-type epitaxial layer (5) is formed on the entire surface of the substrate (1) by a well-known vapor phase growth method.
Formed to a thickness of μm. At this time, the buried layer (2) and the diffusion layer 4) are slightly diffused in the vertical direction.
次に第１図（ハ）に示す如く、エピタキシャル層り５）
表面に選択的にポロン（Ｂ）をイオン注入し、ベース領
域（６）を付着する。このイオン注入はドーズ量１０１
１〜Ｉ Ｑ １４ｃＩＴ、 −１で加速電圧８０〜１０
０ＫｅＶで行う。Next, as shown in Figure 1 (c), an epitaxial layer is formed 5).
A base region (6) is deposited by selectively implanting poron (B) into the surface. This ion implantation has a dose of 101
1~IQ 14cIT, acceleration voltage 80~10 at -1
Performed at 0 KeV.
次に第１図（ニ）に示す如く、基板（１）全体に約１２
００°Ｃ１２時間の熱処理を加えて上下分離領域（３）
の不拡散層（４）と埋込層（２）とをエピタキシャルＭ
（５）内にはい上げて拡散し、同時にベース領域（６）
をドライブインする。具体的には、不拡散層（４）は基
板（１）表面から約５μｍ１埋込層（２〉は約２μｍは
い上げて拡散し、ベース領域（６）はエピタキシャル層
（５）表面から約３μｍ拡散する。Next, as shown in Figure 1 (d), about 12
Upper and lower separated regions (3) after heat treatment at 00°C for 12 hours
The non-diffusion layer (4) and the buried layer (2) are formed by epitaxial M.
(5) Crawling up and spreading into the base area (6)
drive-in. Specifically, the non-diffusion layer (4) extends approximately 5 μm from the surface of the substrate (1) and the buried layer (2) extends approximately 2 μm and is diffused, and the base region (6) extends approximately 3 μm from the surface of the epitaxial layer (5). Spread.
次に第１図（ホ）に示す如く、エピタキシャル層（５）
表面から上下分離領域（３）の上拡散層（７）を選択拡
散し、上下分離領域（３）をエピタキシャル層（５）の
厚みの半分より浅い位置で連結させてこれを接合分離す
る。Next, as shown in FIG. 1 (e), an epitaxial layer (5) is formed.
The upper diffusion layer (7) of the upper and lower isolation regions (3) is selectively diffused from the surface, and the upper and lower isolation regions (3) are connected at a position shallower than half of the thickness of the epitaxial layer (5) to achieve junction isolation.
本工程は本発明の特徴とする工程で、あらかじめ前の工
程で不拡散層（４）とベース領域（６）を十分に深く拡
散した後に上拡散層（７）を形成しているので、上拡散
層（７）を約３μｍと浅くでき、上拡散層（７）の拡散
時間を約１２００℃で１時間に短縮できる。このため上
拡散Ｍ（７）の横方向拡散を約３μｍに抑えることがで
き、上拡散層（７）の表面占有面積を大幅に縮小できる
。具体的には、拡散窓の大きさが４μｍであれば、不拡
散層（４）の幅が約１４μｍに形成されるのに対して上
拡散層（７）の幅は約１０μｍになる。This step is a characteristic step of the present invention, in which the upper diffusion layer (7) is formed after the non-diffusion layer (4) and the base region (6) have been sufficiently deeply diffused in the previous step. The diffusion layer (7) can be made shallow to about 3 μm, and the diffusion time of the upper diffusion layer (7) can be shortened to 1 hour at about 1200°C. Therefore, the lateral diffusion of the upper diffusion layer M (7) can be suppressed to about 3 μm, and the surface area occupied by the upper diffusion layer (7) can be significantly reduced. Specifically, if the size of the diffusion window is 4 μm, the width of the non-diffusion layer (4) is approximately 14 μm, whereas the width of the upper diffusion layer (7) is approximately 10 μm.
次に第１図（へ）に示す如く、拡散深さ約２μｍのＰ型
のインジェクタ領域（８）およびベースコンタクト領域
（９）を同時に拡散し、続いて拡散深さ約１．５μｍの
Ｎ＋型コレクタ領域（１０）を形成する。尚インジェク
タ領域（８）およびベースコンタクト領域（９）はＮＰ
Ｎ）ランジスタのベース拡散工程で形成し、コレクタ領
域り１０）はＮＰＮ）ランジスタのエミッタ拡散工程で
形成する。Next, as shown in FIG. 1(f), the P-type injector region (8) and the base contact region (9) with a diffusion depth of about 2 μm are simultaneously diffused, and then the N+ type with a diffusion depth of about 1.5 μm. A collector region (10) is formed. Note that the injector area (8) and base contact area (9) are NP.
N) is formed in the base diffusion process of the transistor, and the collector region 10) is formed in the emitter diffusion process of the NPN) transistor.
この様に形成したＩＩＬは、上下分離領域（３）がエピ
タキシャル層（５）の厚みの半分より浅い位置で連結さ
れ且つ不拡散層（４）は上拡散層（７）より幅広に形成
される。またベース領域（６）はベースコ７一
ンタクト領域（９）より深く拡散される。In the IIL formed in this way, the upper and lower isolation regions (3) are connected at a position shallower than half the thickness of the epitaxial layer (5), and the non-diffusion layer (4) is formed wider than the upper diffusion layer (7). . Also, the base area (6) is diffused deeper than the base area 71 and the contact area (9).
従って本実施例によれば、ベース領域（６）を十分に深
く拡散する一方で、上下分離領域（３）の上拡散Ｍ（７
）を浅くでき、横方向拡散を抑えて表面占有面積を大幅
に縮小できる。しかも上下分離領域（３）の不拡散層（
４）は幅広に形成するものの、不拡散層（４）とベース
領域（６）とはそれらの周端部が横方向拡散により湾曲
しており、エピタキシャル層（５）深部においである程
度の離間距離が保たれているので、不拡散層（４）はエ
ピタキシャル層（５）表面での集積度の向上をあまり防
げず、上拡散層（７）とベース領域（６）又は上拡散層
（７）とベースコンタクト領域（９）との離間距離を狭
めることができる。よってＩＩＬのパターンサイズを大
幅に縮小できる。Therefore, according to this embodiment, while the base region (6) is diffused sufficiently deeply, the upper diffusion M (7) of the upper and lower separation regions (3) is
) can be made shallower, suppressing lateral diffusion and greatly reducing the surface area occupied. Moreover, the non-diffusion layer (
4) is formed wide, but the peripheral edges of the non-diffusion layer (4) and the base region (6) are curved due to lateral diffusion, and there is a certain separation distance in the deep part of the epitaxial layer (5). is maintained, the non-diffusion layer (4) cannot significantly prevent the increase in the degree of integration on the surface of the epitaxial layer (5), and the upper diffusion layer (7) and the base region (6) or the upper diffusion layer (7) The distance between the base contact region (9) and the base contact region (9) can be reduced. Therefore, the IIL pattern size can be significantly reduced.
また、ベース領域（６）は不拡散層（４）と同時に拡散
するので十分に深く且つ低濃度に設定できる。Further, since the base region (6) is diffused at the same time as the non-diffusion layer (4), it can be set sufficiently deep and at a low concentration.
このベース領域（６）は、島領域（５）をエミッタとす
る逆方向縦型ＮＰＮトランジスタの活性ベースであり、
ベース幅が広くても、ベース領域（６）底部から埋込層
（２）までの距離が短いこととベース領域（６）が十分
に低濃度であることから高い逆方向電流増幅率逆βが得
られる。さらに十分に深く形成されるので、コレクタ領
域（１０）の拡散深さのばらつきによる逆βの変動が少
い。This base region (6) is the active base of a reverse vertical NPN transistor whose emitter is the island region (5),
Even if the base width is wide, the short distance from the bottom of the base region (6) to the buried layer (2) and the sufficiently low concentration of the base region (6) result in a high reverse current amplification factor inverse β. can get. Furthermore, since it is formed sufficiently deep, there is little variation in the inverse β due to variations in the diffusion depth of the collector region (10).
（ト）発明の詳細
な説明した如く、本発明によれば不拡散層（４）をエピ
タキシャル層（５）の厚みの半分以上はい上げてから上
拡散層（７）を形成するので、上拡散層（７）を浅くし
、その横方向拡散を抑えて集積度を大幅に向上できると
いう利点を有する。(G) As described in detail, according to the present invention, the upper diffusion layer (7) is formed after the non-diffusion layer (4) is increased by more than half the thickness of the epitaxial layer (5). It has the advantage that the layer (7) can be made shallow, its lateral diffusion can be suppressed, and the degree of integration can be greatly improved.
しかも本発明によれば、不拡散層（４）と同時にベース
領域（６）をドライブインするので、ベース領域（６）
を十分に深く且つ低濃度に形成でき、特性良好なＩＩＬ
が得られるという利点を有する。Moreover, according to the present invention, since the base region (6) is driven in at the same time as the non-diffusion layer (4), the base region (6)
IIL can be formed sufficiently deep and at low concentration, and has good characteristics.
It has the advantage that it can be obtained.
そして本発明によれば、上拡散層（７）の拡散時間を短
くできるので、熱拡散によるエピタキシャル層（５）表
面の結晶欠陥が少いという利点を有し、きらに不拡散層
（４）を上拡散Ｎ（７）より幅広に形成するので多少の
マスクずれがあっても完全な接合分離が得られるという
利点を有する。According to the present invention, since the diffusion time of the upper diffusion layer (7) can be shortened, there is an advantage that there are fewer crystal defects on the surface of the epitaxial layer (5) due to thermal diffusion. Since it is formed wider than the upper diffusion N(7), it has the advantage that complete junction isolation can be obtained even if there is some mask shift.
第１図は（イ）乃至第１図（へ）は本発明を説明するた
めの断面図、第２図（り乃至（ホ）は従来のＩＩＬの製
造方法を説明するための断面図である。
（１）は半導体基板、 （４）は上下分離領域（３）
の下拡散Ｊｅ？、（５）はエピタキシャル層、（６）は
ベース領域、 （７）は上下分離領域（３）の上拡散層
である。
出願人 三洋電機株式会社外１名
代理人 弁理士 西野卓嗣 外１多
筒 １ 図 （イ〕
第１図ｔｏ＞
第１図（ホ）
第１図（へ）
第２図（イ）
第２図（ロフ1A to 1F are cross-sectional views for explaining the present invention, and FIGS. 2A to 2E are cross-sectional views for explaining the conventional IIL manufacturing method. (1) is the semiconductor substrate, (4) is the upper and lower separation region (3)
Lower diffusion Je? , (5) is an epitaxial layer, (6) is a base region, and (7) is an upper diffusion layer of the upper and lower separation regions (3). Applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Takuji Nishino 1 Figure (A) Figure 1 to > Figure 1 (E) Figure 1 (F) Figure 2 (A) Figure 2 (Roff
Claims (1)
導電型の不純物を付着し、該埋込層を囲んで上下分離領
域の下拡散層を形成する一導電型の不純物を付着する工
程、 前記基板全面に逆導電型のエピタキシャル層を積層する
工程、 前記エピタキシャル層表面にベース領域を形成する一導
電型の不純物を付着する工程、 前記基板全体を加熱処理して前記下拡散層を前記エピタ
キシャル層の厚みの半分以上はい上らせて拡散し、同時
に前記ベース領域をドライブインする工程、 前記エピタキシャル層表面より前記上下分離領域の上拡
散層を形成し、前記下拡散層へ到達させる工程、 前記エピタキシャル層表面より一導電型のインジェクタ
領域とベースコンタクト領域を形成し、続いて前記ベー
ス領域表面に逆導電型のコレクタ領域を形成する工程と
を具備することを特徴とする半導体注入集積論理回路装
置の製造方法。(1) Impurities of the opposite conductivity type are attached to the surface of a semiconductor substrate of one conductivity type to form a buried layer, and impurities of one conductivity type are attached to surround the buried layer and form a diffusion layer below the upper and lower separation regions. a step of laminating an epitaxial layer of opposite conductivity type on the entire surface of the substrate; a step of attaching an impurity of one conductivity type to form a base region on the surface of the epitaxial layer; and a step of heat-treating the entire substrate to form the lower diffusion layer. spreading the epitaxial layer by more than half the thickness of the epitaxial layer and simultaneously driving in the base region, forming an upper diffusion layer of the upper and lower isolation regions from the surface of the epitaxial layer and reaching the lower diffusion layer. forming an injector region and a base contact region of one conductivity type from the surface of the epitaxial layer, and then forming a collector region of the opposite conductivity type on the surface of the base region. A method of manufacturing an integrated logic circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61060014A JPS62216355A (en) | 1986-03-18 | 1986-03-18 | Manufacture of semiconductor injection integrated logic circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61060014A JPS62216355A (en) | 1986-03-18 | 1986-03-18 | Manufacture of semiconductor injection integrated logic circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62216355A true JPS62216355A (en) | 1987-09-22 |
| JPH0577297B2 JPH0577297B2 (en) | 1993-10-26 |
Family
ID=13129787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61060014A Granted JPS62216355A (en) | 1986-03-18 | 1986-03-18 | Manufacture of semiconductor injection integrated logic circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62216355A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5350686A (en) * | 1976-10-19 | 1978-05-09 | Mitsubishi Electric Corp | Production of semiconductor integrated circuit |
| JPS5384578A (en) * | 1976-12-29 | 1978-07-26 | Fujitsu Ltd | Semiconductor integrated circuit |
-
1986
- 1986-03-18 JP JP61060014A patent/JPS62216355A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5350686A (en) * | 1976-10-19 | 1978-05-09 | Mitsubishi Electric Corp | Production of semiconductor integrated circuit |
| JPS5384578A (en) * | 1976-12-29 | 1978-07-26 | Fujitsu Ltd | Semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0577297B2 (en) | 1993-10-26 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |