JPS62219557A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable upper diffused layers to be made shallow and to significantly enhance the integration degree of the titled integrated circuit inhibiting the lateral diffusion of the upper diffused layers by a method wherein, after the lower diffused layers are made to creep up in advance over half of the thickness of an epitaxial layer, the upper diffused layers are formed. CONSTITUTION:The lower diffused layers 4 of vertical isolation regions 3 and the collector buried layer 5 of the vertical type PNP transistor are diffused being made to creep up over half of the thickness of an epitaxial layer 6 by applying a 2hr heat treatment to a whole substrate 1 at about 1,200 deg.C, and at the same time, the base region 7 of the vertical type PNP transistor and the base region 8 of the IIL are driven in. Then, the upper diffused layers 9 of the vertical isolation regions 3 and the collector lead-out regions 10 of the vertical type PNP transistor are simultaneously diffused selectively from the surface of the epitaxial layer 6, the vertical isolation regions 3 are coupled with the epitaxial layer 6 at the positions shallower than half of the thickness of the epitaxial layer 6 and first, second and third island regions 11, 12 and 13 are formed. The collector buried layer 5 and the base region 7 of the vertical type PNP transistor and the base region 8 of the IIL are driven in with the lower diffused layers 4 driven in.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to vertical PNP transistors and IIL (Inte
This invention relates to improvements in the manufacturing method of semiconductor integrated circuits incorporating rated injection logic and ordinary NPN transistors.

(B) Prior Art A conventional method for manufacturing a semiconductor integrated circuit will be explained with reference to FIGS. 2(A) to 2(E).

First, as shown in FIG. 2(A), a P-type silicon substrate is used as the semiconductor substrate (1), antimony (SB) is selectively deposited on the substrate (1), and a plurality of buried layers (2) are formed.
a) Form (2b) (2c) and embed MA (2a)
(2b) Boron (B) is deposited on the surface of the substrate (1) surrounding (2c) and on a predetermined buried layer (2a) to form the lower diffusion layer (4) of the upper and lower separation regions (3) and the vertical PNP. A collector buried layer (5) of the transistor is formed.

Next, as shown in FIG. 2(B), an N-type epitaxial layer (6) is formed to a predetermined thickness over the entire surface of the substrate (1) by a well-known vapor phase growth method.

Next, as shown in FIG. 2(c), an epitaxial layer (6) is formed.
Phosphorus (P) is ion-implanted onto a predetermined buried layer (2a) on the surface, and a base region (7) of a vertical PNP transistor is attached. This ion implantation has a dose of 1012~l Q
"cyn-" and an acceleration voltage of 80 to 100 KeV. Then, boron (B) ions are implanted onto the other buried layer (2b), and the base region (8) of the IIL is attached. This ion implantation was carried out at a dose of 1013 to 10'4 and an acceleration voltage of 8
It is carried out at 0 to 100 KeV.

Next, as shown in FIG. 2(d), an epitaxial layer (6) is formed.
The upper diffusion layer (9) of the upper and lower separation regions (3) from the surface and the vertical P
The collector lead-out region (10) of the NP transistor is diffused, and at the same time, the lower diffusion layer (4), the collector buried layer (5) and base region (7) of the vertical PNP I-transistor, and the I
Drive in the IL base area (8). In this step, the upper diffusion layer (9) and the lower diffusion layer (4) are connected to form two lower isolation regions (3), and the epitaxial layer (6) is junction-separated to form the first, second, and third regions. Island area (11) (12) (
13). Further, the collector lead-out region (10) reaches as far as the collector buried layer (5) and surrounds the base region (7).

Specifically, if the thickness of the epitaxial layer (6) is 13 μm, the upper diffusion layer (9) is diffused to a depth of approximately 9 μm, the lower diffusion layer (4) and the collector buried layer (5) are diffused to a depth of approximately 7 μm, The base region (7) of the vertical PNP transistor and the base region (8) of the IIL are both driven in to a depth of about 4 μm.

Next, as shown in Figure 2 (E), an epitaxial layer (6) is formed.
Boron (B) is selectively diffused from the surface to form the first island region (1
1) has an emitter region (14) of a vertical PNP transistor.
), the second island region (12) has an injector region (15) and a base contact region (16) of the IIL,
The base regions (17) of NPN transistors are formed in the third island regions (13), and then phosphorus (P) is selectively diffused, and the base regions of vertical PNP transistors are formed in the first island regions (11). A contact region (18) is provided in the second island region (12), a collector region (19) of the IIL is provided in the second island region (12), an emitter region (20) and a collector contact region (21) of the NPN transistor are provided in the third island region (13). ) respectively.

Vertical PN formed in the first island region (11) in this way
In the P transistor, most of the active base is formed in the base region (7) formed by ion implantation, so the impurity concentration generates an internal drift electric field to increase the traveling speed of carriers, resulting in a high gain bandwidth product. fT has been obtained. Also a vertical PNP transistor stone. is almost determined by the base region (7), so the epitaxial layer (6)
hFII does not vary much even if the specific resistance and thickness of the material vary. A vertical PNP transistor having such a structure is described in, for example, Japanese Patent Laid-Open No. 59-211270.

In addition, the IIL formed in the second island region (12) is a base contact region (1
6) Since it is formed with a deeper base region (8), a high inverse β can be obtained even if the base width is wide. Furthermore, IIL of such a structure
is described, for example, in Japanese Patent Application No. 60-206971.

In the third island region (13), a normal bipolar NPN I transistor whose collector is the island region (13) can coexist integrally with these vertical PNP transistors and IIL.

(c) Problems to be solved by the invention However, in order to take advantage of the high speed of IIL, the distance from the bottom of the base region (8) of IIL to the buried layer (2b) must be shortened by making the epitaxial layer (6) thinner. It is more advantageous to However, in the conventional manufacturing method, at the same time the upper diffusion layer (9) of the upper and lower separation regions (3) is diffused, the collector buried layer (5) and base region (7) of the vertical PNPl-transistor and the base region (8) of the IIL are diffused. ) is a drive-in. Therefore, the diffusion process of the upper diffusion layer (9) requires a processing time long enough to diffuse these regions sufficiently deeply and obtain predetermined characteristics. Moreover, between the upper diffusion layer (9) and the lower diffusion layer (4), the upper diffusion layer (9) is in a state where more impurities are supplied, that is, the diffusion source film containing a large amount of boron (B) remains attached. Therefore, the upper diffusion layer (9) is inevitably formed deeper than the lower diffusion layer (4).

Therefore, even if the epitaxial layer (6) is made thinner, the upper diffusion layer (
9) had to be formed quite deep and had the disadvantage that lateral diffusion was large and the degree of integration could not be improved.

(d) Means for solving the problems The present invention has been made in view of the above-mentioned drawbacks, and the present invention has been made in view of the above drawbacks.
3) The lower diffusion layer <4> and the collector buried layer (5) of the vertical PNP transistor are raised and diffused by more than half the thickness of the epitaxial layer (6), and at the same time the base region (7) of the vertical PNP transistor is After driving in the base region (8) of the IIL and IIL sufficiently deeply, a diffusion layer (9) above the upper and lower isolation regions (3) is formed to form a vertical PNP transistor and an IIL with greatly improved integration density. The present invention provides a method for manufacturing a semiconductor integrated circuit in which a semiconductor integrated circuit and an NPN transistor coexist.

(*) Effect According to the present invention, the upper diffusion layer (9) is formed after the lower diffusion layer (4) has been raised by half the thickness of the epitaxial layer (6) and then diffused. ) can be made shallower, suppressing its lateral diffusion and reducing the surface area occupied. Moreover, the collector buried layer (5) and base region (7) of the vertical PNP transistor and the base region of the IIL (
8) is driven in at the same time as the lower diffusion it(4), so each region can be formed sufficiently deep.

Therefore, a vertical PNP transistor with good characteristics, an IIL, and an NPN transistor can be integrated and coexist, and the degree of integration can be greatly improved.

(f) Example The method for manufacturing a semiconductor integrated circuit of the present invention is shown in Fig. 1 (a) below.
This will be explained in detail using .

First, as shown in FIG. 1(A), a P-type silicon substrate is used as a semiconductor substrate (1), antimony (SB) is selectively deposited on the substrate (1), and a plurality of buried layers (2) are formed.
a) (2b) (2c) are formed, and the buried layer (2g) (
Boron (B) is deposited on the surface of the substrate (1) surrounding zb> (2c) and on a predetermined buried layer (2a) to form the lower diffusion layer (4) of the upper and lower isolation region (3) and the vertical PNP transistor. A collector buried layer (5) is formed.

Next, as shown in FIG. 1(b), an N-type epitaxial layer (6) is deposited on the entire surface of the substrate (1) by a well-known vapor phase epitaxy method for about 70 cm.
Formed to a thickness of μm.

Next, as shown in Figure 1 (C), an epitaxial layer (6) is formed.
Phosphorus (P) is ion-implanted onto a predetermined buried layer (2a) on the surface, and a base region (7) of a vertical PNP transistor is attached. This ion implantation has a dose of 10'2 w l
Q "cm-" and an acceleration voltage of 80 to 100 KeV.

Then, boron (B) ions are implanted onto the other buried layer (2b), and the base region (8) of the IIL is attached. This ion implantation is carried out at a dose of 10'3 to 10'' and an acceleration voltage of 80
Perform at ~100 KeV. In this process, boron (B)
Needless to say, it is also possible to ion-implant phosphorus (P) and then ion-implant phosphorus (P).

Next, as shown in Figure 1 (d), about 12
By applying heat treatment at 00°C for 2 hours, the lower diffusion layer (4) of the upper and lower isolation regions (3) and the collector buried layer (5) of the vertical PNP transistor are transformed into an epitaxial layer (6).
It spreads by crawling up more than half of its thickness, and at the same time l1ffi
PNP transistor base region (7) and IIL (7)
Drive in base area (8). Specifically, the lower diffusion layer (4) and collector buried layer (5) are raised and diffused by about 5 μm, and the base region of the vertical PNP transistor (
7) and the base region (8) of the IIL are diffused to a depth of approximately 3 μm. The base region (7) of the vertical PNP transistor therefore completely reaches the collector buried layer (5). It should be noted that there is no problem even if the impurity concentration in the base region (7) is made slightly lower than in this embodiment so that it does not completely reach the collector buried layer (5). And buried layers (2a) (2b) (2
c) is crawled to a depth of approximately 2 μm.

Next, as shown in FIG. 1 (e), an epitaxial layer (6) is formed.
The upper diffusion layer (9) of the upper and lower separation regions (3) from the surface and the vertical P
The collector lead-out region (10) of the NP transistor is selectively diffused at the same time, and the upper and lower isolation regions (3) are covered with an epitaxial layer (
6) Connect at a position shallower than half the thickness of the first, second,
Third island regions (11), (12), and (13) are formed.

This step is a characteristic step of the present invention, in which the upper diffusion layer (4) is raised and diffused in advance by more than half the thickness of the epitaxial layer (6), and at the same time, the collector buried layer (5) of the vertical PNP transistor is After driving in the base region (7) and the base region (8) of IIL sufficiently deeply, the upper diffusion B (9) is formed, so the upper diffusion layer (9) is not restricted by these regions and has a thickness of approximately 3 μm. The diffusion time can be shortened to about 1 hour. Therefore, by suppressing the lateral diffusion of the upper diffusion layer (9) to about 3 μm, the surface area occupied by the upper diffusion layer (9) can be significantly reduced. If the width of the diffusion window is 4 μm, the upper diffusion layer (9) and the collector lead-out region (
10) is formed to have a width of about 10 μm. Also, the upper diffusion layer (
4> is wider because it is formed deeper than the upper diffusion layer (9>), and has a width of approximately 14 μm.

Next, as shown in Fig. 1 (f), an epitaxial layer (6) is formed.
Selectively diffuse boron (B) from the surface to form the first island region 1
1) has a vertical PNP emitter region (1)
4), the injector region (15) and base contact region (16) of the IIL are placed in the second island region (12), and the base region (17) of the NPN transistor is placed in the third island region (13), respectively. Diffusion to a target depth of 2 μm, followed by selective diffusion of phosphorus (P) from the surface of the epitaxial layer (6),
The first island region (11) has a base contact region (18) of a vertical PNP transistor, and the second island region (12) has a base contact region (18) of a vertical PNP transistor.
is the collector region (19) of IIL, and the third island region (
13) is the emitter region of the NPN transistor (20
) and the collector contact area (21) are each 1.5 μm.
Form to a depth of m.

In the semiconductor integrated circuit formed in this way, the upper diffusion layer (9)
Since it can be made shallower, its lateral diffusion can be suppressed and the surface area occupied can be significantly reduced. At this time, although the lower diffusion layer (4) is formed to be wider than the upper diffusion layer (9), its peripheral edge is curved due to lateral diffusion and gradually becomes narrower upward from the surface of the substrate (1). Therefore, about 14μ on the surface of the substrate (1)
Even if there is a width of m, the line width at the top of the upper diffusion layer (4) is about 4 μm, which is the line width of the diffusion window. Therefore, the upper diffusion layer (4) formed wide cannot prevent an increase in the degree of integration on the surface of the epitaxial layer (6), and the surface occupation area of the upper and lower separation regions (3) can be determined only by the upper diffusion layer (9). can significantly improve the degree of

Furthermore, in the vertical PNP transistor formed in the first island region (11), the collector buried layer (5) and the base region (7)
) is formed at the same time as the upper diffusion layer (4), so it can be formed sufficiently deep. Therefore, since all or substantially all of the region serving as the active base is formed by the base region (7) formed by ion implantation, a high fT equal to or higher than that of the conventional method can be obtained, and there is less variation among the crystals. The collector buried layer (5) formed by the difference in the diffusion coefficients of boron (B) and antimony (sb) also rises larger than the buried layer (2a), which is necessary and sufficient. .

(sat) is obtained.

In addition, in the IIL formed in the second island region (12), the active base of the inverted vertical NPN transistor whose emitter is the island region (12) is formed in the low concentration base region (8) formed by ion implantation. formed and base region (8)
The buried layer (2b) is diffused deeply and the epitaxial layer (6) is made thinner.
) are close to each other, so even if the base width is wide, a high inverse β can be obtained. Since the active base is deep, there is little variation in the inverse β due to variations in the collector region (19).

Then, the third island area (13) has this island area (13).
A bipolar NPN transistor (with collector IIL) is integrated with a vertical PNP transistor, IIL.

(g) As described in detail, according to the present invention, the upper diffusion layer (
4) is increased by more than half the thickness of the epitaxial layer (6), and then the upper diffusion layer (9) is formed.
) can be made shallow, its lateral diffusion can be suppressed, and the degree of integration can be greatly improved.

Furthermore, according to the present invention, the vertical P
Since the collector buried layer (5) and base region (7) of the NP transistor and the base region (8) of the IIL are driven in, sufficient diffusion depth is obtained for each, thereby providing the necessary and sufficient Vct (sat). It has the advantage that a vertical PNP l-transistor having variations in , fl, h, and a, an IIL with improved inverse β and further increased speed, and a normal bipolar NPN transistor can coexist in an integrated manner.

Further, according to the present invention, since the diffusion time of the upper diffusion layer (9) is short, there are fewer crystal defects on the surface of the epitaxial layer (6) due to thermal diffusion, and the upper diffusion layer (4) is made wider than the upper diffusion layer (9). Since it is formed in the same direction, it has the advantage that complete junction separation can be obtained even if there is some mask displacement.

[Brief explanation of drawings]

Figures 1 (A) to 1 (F) are cross-sectional views for explaining the manufacturing method according to the present invention, and Figures 2 (A) to 2 (E) are cross-sectional views for explaining the conventional manufacturing method. FIG. (1) is a semiconductor substrate, (2a), (2b), and (2c) are buried layers, (4) is an upper diffusion layer of the upper and lower separation regions (3), (5)
is the collector buried layer of the vertical PNP transistor, (6> is the epitaxial layer, (7) is the base region of the vertical PNP transistor, (8) is the base region of the IIL, and (9) is the upper and lower isolation region (3). This is the upper diffusion layer.

Claims (1)

[Claims] (1) Impurities of the opposite conductivity type forming a plurality of buried layers are attached to the surface of a semiconductor substrate of one conductivity type, and a diffusion layer below the upper and lower separation regions is placed on the surface of the substrate surrounding the buried layers in a predetermined manner. A step of depositing an impurity of one conductivity type on the buried layer to form a collector buried layer of a vertical PNP transistor, a step of laminating an epitaxial layer of the opposite conductivity type on the entire surface of the substrate, and a step of depositing an epitaxial layer of the opposite conductivity type on the entire surface of the epitaxial layer. On the predetermined buried layer, an impurity of an opposite conductivity type is formed to form the base region of the vertical PNP transistor, and on the other buried layer, an impurity of one conductivity type is formed to form the base region of the IIL. a step of attaching, heating the entire substrate to increase and diffuse the lower diffusion layer and the collector buried layer by more than half the thickness of the epitaxial layer, and at the same time attaching the base region of the vertical PNP transistor and the IIL; a step of driving in the base region, selectively diffusing the upper diffusion layer of the upper and lower separation regions from the surface of the epitaxial layer until reaching the lower diffusion layer;
forming second and third island regions and simultaneously forming a collector lead-out region of the vertical PNP transistor in the first island region; selectively diffusing impurities of one conductivity type from the surface of the epitaxial layer; The emitter region of the vertical PNP transistor is provided in the first island region, the injector region and base contact region of the IIL are provided in the second island region, and the base region of the NPN transistor is provided in the third island region. Then, by selectively diffusing impurities of opposite conductivity type, a base contact region of the vertical PNP transistor is formed in the first island region, a collector region of the IIL is formed in the second island region, and A method of manufacturing a semiconductor integrated circuit, comprising the step of forming an emitter region and a collector contact region of the NPN transistor in the third island region, respectively.