JPH0727969B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor integrated circuit in which a high breakdown voltage linear element and a high-speed IIL coexist.

(B) Conventional technology IIL (Integrated Injection Logic) is a bipolar logic element with high integration density and low power consumption, and it can be manufactured by the conventional bipolar integrated circuit manufacturing method. It is possible to coexist with a linear circuit such as an NPN transistor. IIL
When co-existing with the linear transistor, the IIL operating speed and the withstand voltage BV _CEO (collector-emitter withstand voltage) of the linear transistor can be raised as one indicator of the performance of the integrated circuit. In order to increase the operation speed of IIL, it is necessary to reduce the thickness of the epitaxial layer portion.
However, in order to increase the breakdown voltage BV _{CEO of the} linear element, the contradictory condition of increasing the thickness of the epitaxial layer portion is necessary.

Therefore, as described in, for example, Japanese Patent Application Laid-Open No. 57-164558, a two-stage epitaxial structure as shown in FIG. 2 has been proposed. The manufacturing method will be briefly described below.

A high-concentration N-type impurity diffusion is selectively performed on the P-type substrate (1) to form a first buried layer (2). After that, a first epitaxial layer (3) is formed by a vapor phase epitaxy method, and N type high impurity concentration diffusion is selectively performed in a region for forming an IIL to form a second buried layer (4). Subsequently, an N-type second epitaxial layer (5) is formed on the entire surface by a vapor phase epitaxy method, and a P ⁺ type is reached from the surface of the second epitaxial layer (5) to the substrate (1) for element isolation. To form the isolation region (6). After that, the P-type base region (8) of the NPN transistor ( 7 ), the N ⁺ -type emitter region (9) and the N ⁺ -type collector lead-out region (10) are formed in the region where only the first buried layer (2) is formed. In the region where the second buried layer (4) is formed, the IIL ( 11 ) P-type injector region (12), P-type base region (13), N ⁺ -type collector region (14) and N ⁺ -type region are formed. Forming a contact region (15). This result IIL ( 11 )
The thickness of the epitaxial layer of the portion is effectively thin, and the thickness of the epitaxial layer of the NPN transistor ( 7 ) portion is thick, which satisfy the contradictory conditions. However, since the sum of the thicknesses of the first and second epitaxial layers (3) and (5) is considerably large and the diffusion time of the isolation region (6) is considerably long, impurities in the first buried layer (2) are It exudes to the side of the first epitaxial layer (3) and causes the breakdown voltage of the NPN transistor ( 7 ) to deteriorate. Further, since the diffusion is performed for a long time, the lateral diffusion of the isolation region (6) also becomes large, resulting in an increase in occupied area.

In order to improve such a defect, a structure as shown in FIG. 3 can be considered. In this structure, the separation region ( 6 ) is connected to the upper separation region (1
6) and the lower isolation region (17), which are connected to each other for element isolation, and which forms the lower isolation region (17) on the surface of the first epitaxial layer (3). (B) is deposited and the upper isolation region (16) is diffused from the surface of the second epitaxial layer (15),
Using this heat process, the deposited lower isolation region (17) is driven in in both up and down directions. The driven-in lower diffusion layer (17) penetrates the first epitaxial layer (3) to reach the surface of the substrate (1), and is diffused from the surface to the second epitaxial layer (5) side. The element isolation is completed by connecting with the upper isolation region (16). With this structure,
Since the diffusion time required for element isolation can be shortened,
The seepage of the second embedded layer (2) is a little, and the degree of breakdown voltage deterioration is small. In addition, since the lateral diffusion of the upper isolation region (16) is small, the occupied area required for element isolation can be small.

(C) Problems to be Solved by the Invention However, even in the above-described manufacturing method, since the lower isolation region (17) is driven in using the thermal process of the upper isolation region (16), the upper isolation region ( 16) must be formed at least half as deep as the thickness of the second epitaxial layer (5). Therefore, there is a drawback that the occupied area required for element isolation cannot be further reduced. Moreover, since the first epitaxial layer (3) cannot be extremely thick, NP
The second epitaxial layer (5) cannot be extremely thin in order to secure the breakdown voltage BV _CEO of the N transistor ( 7 ). Moreover, 2
The first epitaxial layer (5) is the emitter, the base region (13) is the base, and the collector region (14) is the collector.
IIL reverse direction inverter NPN transistor has a defect that the impurity concentration gradient of the base is inclined in the opposite direction from the collector to the emitter, so that a faster IIL cannot be obtained.

(D) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and an antimony (Sb) forming a second embedded layer (24) is formed on the surface of the first epitaxial layer (23). A step of depositing and further ion-implanting boron (B) forming a lower isolation region (25), a step of laminating a second epitaxial layer (27) on the entire surface, and a surface of the second epitaxial layer (27) To IIL ( 38 )
The step of implanting boron (B) forming the base region (28) of the above, and the heat treatment is applied to the entire substrate (21) to drive the lower isolation region (25) up and down.
A step of driving in the base region (28) of L ( 38 ) to a predetermined depth, and a step of forming an upper isolation region (30) from the surface of the second epitaxial layer (27) to complete element isolation. The NPN transistor (32) is embedded in the second layer in the region where only the first embedded layer (22) is provided by sequentially diffusing P-type impurities and N-type impurities from the surface of the second epitaxial layer (27). And a step of forming an IIL ( 38 ) in the region where the layer (24) is provided.

(E) Function According to the present invention, since the lower isolation region (25) is re-diffused in the vertical direction by applying heat treatment to the entire substrate (21) in advance, two layers are left to complete the element isolation. Very small on the surface of the epitaxial layer (27). Therefore, the upper isolation region (30) can be made shallow to suppress lateral diffusion and the occupied area required for element isolation can be reduced. Also, IIL ( 3
Since the base region (28) of 8 ) is set to a low impurity concentration and is deeply formed so as to be close to the second buried layer (24) by utilizing the above-mentioned thermal process, a faster IIL can be obtained.

(F) Embodiment Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

First, as shown in FIG. 1A, the impurity concentration is 10 ¹⁴ to 10 ¹⁵ cm ^-3.
After forming a thermal oxide film on the surface of the P-type silicon substrate (21) to a degree, the thermal oxide film is patterned to form the first buried layer (2
By opening the planned region of 2) and selectively doping N-type impurities such as antimony (Sb) or arsenic (As) using this thermal oxide film pattern as a mask, the N ⁺ -type first buried layer ( 22) Deposit.

Next, as shown in FIG. 1B, the first embedding layer (2
2) The surface of the substrate (21) is exposed by removing all of the thermal oxide film and the like used to form it, and a thickness of 7 to 9 μm and a specific resistance ρ = 1 to 5 Ω are formed on the surface of the substrate (21) by a known vapor phase growth method. -The first epitaxial layer (23) of N type of about cm is laminated and formed. After that, a thermal oxide film pattern is formed again on the surface of the first epitaxial layer (23), and only the planned IIL formation region is doped with N-type impurities such as antimony (Sb) or arsenic (As) to form the second layer of N ^+. The buried layer (24) is deposited, and boron (B) that forms the lower isolation region (25) in the region that is to be the element isolation is further accelerated with an acceleration voltage of 80 to 100 KeV and a dose amount of 10
Ion implantation is performed at about ¹² to 10 ¹³ cm ^-2 . Second embedded layer (24)
The order of the N-type impurities forming the and the P-type impurities forming the lower isolation region (25) may be reversed. In addition, (2
6) is a collector low resistance buried region provided for the purpose of reducing the collector series resistance of the NPN transistor.

Subsequently, as shown in FIG. 1C, a thickness of 7 to 9 is formed on the entire surface of the first epitaxial layer (23) by a known vapor phase growth method.
It is formed by laminating an N-type second epitaxial layer (27) having a μm and a specific resistance ρ = 1 to 5 Ω · cm. After that, boron (B) that forms the IIL base region (28) is accelerated to a voltage of 40 to 60 in the IIL formation planned region on the surface of the second epitaxial layer (27).
Ion implantation is performed with KeV and a dose amount of 10 ¹² to 10 ¹³ cm ^-2 .
Further, phosphorus (P) that forms an N ⁺ -type collector low resistance region (29) is ion-implanted into a region facing the collector low resistance buried region (26) in the NPN transistor formation planned region. The order of these may be reversed.

Then, as shown in FIG. 1D, the entire substrate (21) has about 1200
A heat treatment is performed at 2 ° C. for 2 to 3 hours, and the deposited lower isolation region (25) is driven in from the surface of the first epitaxial layer (23) in both up and down directions. The drive-in lower isolation region (25) is the first epitaxial layer (23)
To reach the surface of the substrate (21), and 4 to 6 μm upward from the surface of the first epitaxial layer (23) and half or more of the thickness of the second epitaxial layer (27) deeper. If formed in this way, only a very small portion of the surface of the second epitaxial layer (27) remains to complete the element isolation. By the heat treatment of this step, the base region (28) of the IIL and the collector low resistance region (29) of the NPN transistor are formed from the surface of the second epitaxial layer (27) to a depth of 3 to 4 μm and 4 to 5 μm, respectively.
The first and second buried layers (22, 24) are re-diffused upward from the deposited surface by about 5 to 7 μm and 3 to 5 μm, respectively.

Next, as shown in FIG. 1E, a P ⁺ -type upper isolation region (30) is formed in a region corresponding to the lower isolation region (25) of the surface of the second epitaxial layer (27), and the lower isolation region is formed. The element isolation is completed by connecting with (25). Since the lower isolation region (25) occupies most of the isolation between elements, the diffusion depth of the upper isolation region (30) can be made shallower than the conventional one by 3 to 4 μm from the surface of the second epitaxial layer (27). Therefore, since the lateral diffusion of the upper isolation region (30) is small, the area occupied by the surface of the second epitaxial layer (27) required for element isolation can be reduced.

Subsequently, as shown in FIG. 1F, a thermal oxide film pattern serving as a mask is formed on the surface of the second epitaxial layer (27),
By selectively diffusing boron (B), the I-L P-type injector region (31) and the NPN transistor P-type base region (3
2) to form. Further, a thermal oxide film pattern is formed again and N type impurities such as phosphorus (P) are selectively diffused, and the N ⁺ type collector region (33), the N ⁺ type contact region (34) and the NPN of the IIL are formed.
Form the N ⁺ -type emitter region (35) of the transistor. After that, a surface oxide film is opened to form a contact hole, and a metal wiring layer is formed and patterned by a known vapor deposition or sputtering method to form an electrode wiring (36) on each region. In this way, the NPN transistor ( 37 ) as a linear element is provided in the region where only the first buried layer (22) is provided, and the II as the logic element is provided as the logic element in the region where the second buried layer (24) is provided.
Form L ( 38 ). (39) is an oxide film.

Since the semiconductor integrated circuit of the present invention formed as described above adopts the two-stage epitaxial structure, the high withstand voltage NPN transistor ( 37 ) and the high speed IIL ( 38 ) can be mounted on the same chip, and the IIL ( 38 ) is formed. Vertical NPN that composes
Since the base region (28) of the transistor has a low impurity concentration and is formed considerably deep so as to be extremely close to the second buried layer (24), a faster IIL ( 38 ) can be obtained. Moreover,
Since heat treatment is applied to the entire substrate (21) in advance to drive in the lower isolation region (25), the upper isolation region (3
The diffusion depth of (0) can be formed to be half or less than the thickness of the second epitaxial layer (27), so that the area occupied by element isolation on the surface of the second epitaxial layer (27) can be reduced. Further, since the base region (28) is driven in by utilizing the thermal process of the lower diffusion region (25) instead of the upper isolation region (30), it is possible to set it to a low impurity concentration but to form it deeply. It can drive in a difficult base area (28) deep enough. Furthermore, since the heat treatment time of the lower diffusion region (25) is not limited by the occupied area for element isolation on the surface of the second epitaxial layer (30), the thickness of the first epitaxial layer (23) can be increased and the thickness of the second epitaxial layer (23) can be increased. Epitaxial layer (27) can be thinly formed, with higher breakdown voltage NPN transistor ( 37 ) and faster I
Can be combined with IL ( 38 ).

The lateral diffusion of the lower isolation region (25) is maximum at the surface of the first epitaxial layer (23) and is smallest at the tip of the top of the lower isolation region (25), and at the same time the second epitaxial layer is formed. The bottom of the diffusion region formed from the surface of the layer (27) also has the smallest lateral diffusion, so the two are sufficiently separated, and the lower isolation region (25) occupies the element isolation on the surface of the second epitaxial layer (27). The area will not be larger than the opening area of the upper isolation region (30).

(G) Effect of the Invention As described above, according to the present invention, the NP having a higher breakdown voltage than the conventional
It has the advantage that the N-transistor ( 37 ) and the faster IIL ( 38 ) can be combined on the same chip. Further, since the occupied area required for element isolation can be reduced, there is an advantage that the chip size can be reduced.

[Brief description of drawings]

1A to 1F are sectional views for explaining the present invention, and FIGS. 2 and 3 are sectional views for explaining a conventional example. (21) is a substrate, (22) is a first buried layer, (23) is a first epitaxial layer, (24) is a second buried layer, (25) is a lower isolation region, (27) Is the second epitaxial layer, (30)
Is the upper separation region.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/082

Claims (1)

[Claims] 1. A step of depositing an impurity of opposite conductivity type to form a first buried layer on the surface of a semiconductor substrate of one conductivity type, and a first epitaxial layer of opposite conductivity type is formed on the entire surface of the substrate. Step and 2 on the IIL formation planned part on the surface of the first epitaxial layer
A step of depositing an impurity of opposite conductivity type forming a buried layer of a first layer, and doping a impurity of one conductivity type forming a lower isolation region in a portion where element isolation is performed, and the first epitaxial layer Forming a second conductivity type second epitaxial layer on the entire surface; ion-implanting a conductivity type impurity forming a base region of the IIL on the surface of the second conductivity type epitaxial layer; Heating to drive in the lower isolation region vertically from the surface of the first epitaxial layer until reaching the substrate, and driving in the base region of the IIL to a predetermined depth; and the second epitaxial layer. Forming an upper isolation region of one conductivity type in a region of the layer corresponding to the lower isolation region, and connecting the lower isolation region to form an element isolation; Selectively diffusing one conductivity type impurity on the surface of the Charl layer to form an injector region of the IIL and a base region of a linear transistor; and selectively diffusing the opposite conductivity type impurity on the surface of the second epitaxial layer. And a step of forming a collector region of the IIL and an emitter region of the linear transistor.