JPH0727970B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor integrated circuit in which a high breakdown voltage linear transistor, a miniaturized low breakdown voltage linear transistor, and a faster IIL coexist.

(B) Conventional technology IIL (Integrated Injection Logic) is a bipolar logic element with high integration density and low power consumption, and it can be manufactured by the conventional bipolar integrated circuit manufacturing method. It is possible to coexist with a linear circuit such as an NPN transistor. IIL
When co-existing with the linear transistor, the IIL operating speed and the withstand voltage BV _CEO (collector-emitter withstand voltage) of the linear transistor can be raised as one indicator of the performance of the integrated circuit. In order to increase the operation speed of IIL, it is necessary to reduce the thickness of the epitaxial layer portion.
However, in order to increase the breakdown voltage BV _{CEO of the} linear element, the contradictory condition of increasing the thickness of the epitaxial layer portion is necessary.

Therefore, as described in, for example, Japanese Patent Application Laid-Open No. 57-164558, a two-stage epitaxial structure as shown in FIG. 2 has been proposed. The manufacturing method will be briefly described below.

A high-concentration N-type impurity diffusion is selectively performed on the P-type substrate (1) to form a first buried layer (2). After that, a first epitaxial layer (3) is formed by a vapor phase epitaxy method, and N type high impurity concentration diffusion is selectively performed in a region for forming an IIL to form a second buried layer (4). Subsequently, an N-type second epitaxial layer (5) is formed on the entire surface by a vapor phase epitaxy method, and a P ⁺ type is reached from the surface of the second epitaxial layer (5) to the substrate (1) for element isolation. To form the isolation region (6). After that, the P-type base region (8) of the NPN transistor ( 7 ), the N ⁺ -type emitter region (9) and the N ⁺ -type collector lead-out region (10) are formed in the region where only the first buried layer (2) is formed. In the region where the second buried layer (4) is formed, the IIL ( 11 ) P-type injector region (12), P-type base region (13), N ⁺ -type collector region (14) and N ⁺ -type region are formed. Forming a contact region (15). This result IIL ( 11 )
The thickness of the epitaxial layer of the portion is effectively thin, and the thickness of the epitaxial layer of the NPN transistor ( 7 ) portion is thick, which satisfy the contradictory conditions. However, since the sum of the thicknesses of the first and second epitaxial layers (3) and (5) is considerably large and the diffusion time of the isolation region (6) is considerably long, impurities in the first buried layer (2) are It exudes to the side of the first epitaxial layer (3) and causes the breakdown voltage of the NPN transistor ( 7 ) to deteriorate. Further, since the diffusion is performed for a long time, the lateral diffusion of the isolation region (6) also becomes large, resulting in an increase in occupied area.

In order to improve such a defect, a structure as shown in FIG. 3 can be considered. In this structure, the separation region ( 6 ) is connected to the upper separation region (1
6) and the lower isolation region (17), which are connected to each other for element isolation, and which forms the lower isolation region (17) on the surface of the first epitaxial layer (3). (B) is deposited and the upper isolation region (16) is diffused from the surface of the second epitaxial layer (5), and
Using this heat process, the deposited lower isolation region (17) is driven in in both up and down directions. The driven-in lower diffusion layer (17) penetrates the first epitaxial layer (3) to reach the surface of the substrate (1), and is diffused from the surface to the second epitaxial layer (5) side. The element isolation is completed by connecting with the upper isolation region (16). According to this structure,
Since the diffusion time required for element isolation can be shortened,
The seepage of the second embedded layer (2) is a little, and the degree of breakdown voltage deterioration is small. In addition, since the lateral diffusion of the upper isolation region (16) is small, the occupied area required for element isolation can be small.

(C) Problems to be Solved by the Invention However, even in the above-described manufacturing method, since the lower isolation region (17) is driven in using the thermal process of the upper isolation region (16), the upper isolation region ( 16) must be formed at least half as deep as the thickness of the second epitaxial layer (5). Therefore, there is a drawback that the occupied area required for element isolation cannot be further reduced. Moreover, since the first epitaxial layer (3) cannot be extremely thick, the second epitaxial layer (5) cannot be extremely thin in order to secure the breakdown voltage BV _CEO of the NPN transistor ( 7 ). Moreover, the second epitaxial layer (5) is the emitter,
IIL reverse inverter NPN transistor with the base region (13) as the base and the collector region (14) as the collector The impurity concentration gradient of the base is inclined in the opposite direction from the collector to the emitter, resulting in faster IIL. There was a drawback that I could not. Furthermore, since the small signal circuit elements other than the output stage are not required to have such a high breakdown voltage, the circuit elements shown in FIGS.
The use of the NPN transistor ( 7 ) in the figure resulted in excessive quality, which was a drawback of unnecessarily increasing the chip size.

(D) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and the second layer is buried in the IIL formation scheduled region and the low breakdown voltage linear transistor formation scheduled region on the surface of the first epitaxial layer (23). Boron (B) that deposits antimony (Sb) that forms the embedded layer (24) and that forms the lower isolation region (25) in the region where element isolation is performed.
Ion implantation, a step of laminating a second epitaxial layer (27) on the entire surface, and a boron (B) forming a base region (28) of IIL ( 41 ) on the surface of the second epitaxial layer (27). And the heat treatment is applied to the entire substrate (21) to drive the lower isolation region (25) up and down, and the base region (28) of the IIL ( 41 ) to a predetermined depth. And a step of forming an upper isolation region (30) from the surface of the second epitaxial layer (27) to complete isolation between elements, and a P-type impurity and an N-type impurity from the surface of the second epitaxial layer (27). Are sequentially diffused, and a high breakdown voltage linear transistor ( 40 ) is provided in a region where only the first buried layer (22) is provided, and a low breakdown voltage linear transistor ( 40 ) is provided in a region where the second buried layer (24) is provided. 42) and by including the step of forming the IIL (41) And butterflies.

(E) Function According to the present invention, since the lower isolation region (25) is re-diffused in the vertical direction by applying heat treatment to the entire substrate (21) in advance, two layers are left to complete the element isolation. Very small on the surface of the epitaxial layer (27). Therefore, the upper isolation region (30) can be made shallow to suppress lateral diffusion and the occupied area required for element isolation can be reduced. In addition, IIL ( 4
Since the base region (28) of 1 ) is set to a low impurity concentration and is deeply formed so as to be close to the second embedded layer (24) by utilizing the above-mentioned thermal process, a faster IIL can be obtained. Further, since the collector lead-out region (29) can be omitted by providing the second buried layer (24), a high breakdown voltage NPN transistor ( 40 ) and a miniaturized low breakdown voltage linear transistor ( 42 ) can coexist. You can

(F) Embodiment Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

First, as shown in FIG. 1A, the impurity concentration is 10 ¹⁴ to 10 ¹⁵ cm ^-3.
After forming a thermal oxide film on the surface of the P-type silicon substrate (21) to a degree, the thermal oxide film is patterned to form the first buried layer (2
By opening the planned region of 2) and selectively doping N-type impurities such as antimony (Sb) or arsenic (As) using this thermal oxide film pattern as a mask, the N ⁺ -type first buried layer ( 22) Deposit.

Next, as shown in FIG. 1B, the first embedding layer (2
2) The surface of the substrate (21) is exposed by removing all of the thermal oxide film and the like used to form it, and a thickness of 7 to 9 μm and a specific resistance ρ = 1 to 5 Ω are formed on the surface of the substrate (21) by a known vapor phase growth method. -The first epitaxial layer (23) of N type of about cm is laminated and formed. After that, a thermal oxide film pattern is formed again on the surface of the first epitaxial layer (23), and antimony (Sb) or arsenic (As) is formed in the low breakdown voltage linear transistor and the IIL formation planned region.
⁺ N-type second buried layer by doping N-type impurities such as
Is further deposited, and boron (B) that forms the lower isolation region (25) in the region that is to be used as the element isolation is ion-implanted at an acceleration voltage of 80 to 100 KeV and a dose amount of 10 ¹³ to 10 ¹⁴ cm ^-2. To do. The N-type impurities forming the second buried layer (24) and the P-type impurities forming the lower isolation region (25) may be formed in reverse order. Reference numeral (26) is a collector low resistance buried region provided for the purpose of reducing the collector series resistance of the high breakdown voltage linear transistor.

Subsequently, as shown in FIG. 1C, a thickness of 7 to 9 is formed on the entire surface of the first epitaxial layer (23) by a known vapor phase growth method.
It is formed by laminating an N-type second epitaxial layer (27) having a μm and a specific resistance ρ = 1 to 5 Ω · cm. After that, boron (B) that forms the IIL base region (28) is accelerated to a voltage of 40 to 60 in the IIL formation planned region on the surface of the second epitaxial layer (27).
Ion implantation is performed with KeV and a dose amount of 10 ¹² to 10 ¹³ cm ^-2 .
Further, phosphorus (P) forming an N ⁺ -type collector low resistance region (29) is ion-implanted into a region corresponding to the collector low resistance buried region (26) in the high breakdown voltage linear transistor formation planned region. The order of these may be reversed.

Then, as shown in FIG. 1D, the entire substrate (21) has about 1200
A heat treatment is performed at 2 ° C. for 2 to 3 hours, and the deposited lower isolation region (25) is driven in from the surface of the first epitaxial layer (23) in both up and down directions. The drive-in lower isolation region (25) is the first epitaxial layer (23)
To reach the surface of the substrate (21), and 4 to 6 μm upward from the surface of the first epitaxial layer (23) and half or more of the thickness of the second epitaxial layer (27) deeper. If formed in this way, only a very small portion of the surface of the second epitaxial layer (27) remains to complete the element isolation. By the heat treatment of this step, the base region (28) of the IIL and the collector low resistance region (29) of the high breakdown voltage linear transistor are formed at a depth of 3 to 4 μm and 4 to 5 μm respectively from the surface of the second epitaxial layer (27). The first and second burying layers (22) and (24) are 5 to 7 μm and 3 to 5 μm from the deposited surface, respectively.
It is re-diffused upward. As a result, the buried layer in the low breakdown voltage linear transistor formation planned region is connected to the first and second layers to form one large buried layer.

Next, as shown in FIG. 1E, the second epitaxial layer (2
7) A P ⁺ upper isolation region (30) is formed in a region corresponding to the lower isolation region (25) on the surface and is connected to the lower isolation region (25) to complete element isolation. Since the lower isolation region (25) occupies most of the element isolation, the diffusion depth of the upper isolation region (30) is the second epitaxial layer (27).
It can be made shallower than before by 3 to 4 μm from the surface. For that reason,
Since the lateral diffusion of the upper isolation region (30) is small, the area occupied by the surface of the second epitaxial layer (27) required for element isolation can be reduced.

Subsequently, as shown in FIG. 1F, a thermal oxide film pattern serving as a mask is formed on the surface of the second epitaxial layer (27),
Boron (B) is selectively diffused to a depth of 2 to 3 μm
An IIL P-type injector region (31) and low-voltage and high-voltage linear transistor P-type base regions (32) (33) are formed. Further, a thermal oxide film pattern is formed again, and N type impurities such as phosphorus (P) are selectively diffused to a depth of 1 to 2 μm, and the N ⁺ type collector region (34) and the N ⁺ type contact region (35) of IIL are formed. , N ⁺ type emitter regions (36) (37) and N ⁺ collector contact regions (38) of low and high breakdown voltage linear transistors are formed. Thereafter, the surface oxide film is opened to form a contact hole, and a metal wiring layer is formed and patterned by a well-known vapor deposition or sputtering method to form an electrode wiring (39) on each region. Thus, the first buried layer (2
In the area where only 2) is provided, the NPN type high breakdown voltage linear transistor ( 40 ) is used as a linear element, and in the area where the second embedded layer (24) is provided, the IIL ( 41 ) as a logic element and a linear element are used. NPN type low breakdown voltage linear transistor ( 42 ) is formed.

Since the semiconductor integrated circuit of the present invention formed as described above adopts the two-stage epitaxial structure, the high breakdown voltage linear transistor ( 40 ) and the high speed IIL ( 31 ) can be incorporated on the same chip, and the second layer is formed. Low breakdown voltage linear transistor ( 42 ) miniaturized by providing a buried layer (24)
Can coexist. Since the low withstand voltage linear transistor ( 42 ) can obtain a small saturation voltage V _{CE (sat)} by the second buried layer (24), it is not always necessary to provide the collector low resistance region (29), and the shallow collector contact region ( 38) is enough, so it can be miniaturized more than the high breakdown voltage linear transistor ( 40 ). In addition, the base region (32) of the low breakdown voltage linear transistor ( 42 ) is the base region (2) of the IIL.
8) Since it is shallower, sufficient withstand voltage BV _CEO can be obtained for small signals.

Furthermore, according to the manufacturing method of the present invention, the substrate (2
1) Since heat treatment is applied to the whole to drive-in the lower isolation region (25), the diffusion depth of the upper isolation region (30) is set to 2
The second epitaxial layer (27) can be formed to have a thickness half or less than the thickness of the second epitaxial layer (27).
The area occupied by element isolation on the surface can be reduced. Also, not the upper separation area (30) but the lower separation area (25).
The drive-in of the base region (28) is performed by using the heat process of 1. Therefore, the base region (28), which is difficult to form deeply because of the low impurity concentration, can be driven in sufficiently deeply. Further, since the heat treatment time of the lower diffusion region (25) is not limited by the occupied area for element isolation on the surface of the second epitaxial layer (27), the thickness of the first epitaxial layer (23) and the thickness of the second epitaxial layer (23) are larger than those of the prior art. The thickness of the epitaxial layer (27) can be made thinner, and the linear transistor ( 40 ) with a higher breakdown voltage than before and the IIL ( 4
It can be combined with 1 ).

The lateral diffusion of the lower isolation region (25) is maximum at the surface of the first epitaxial layer (23) and is smallest at the tip of the top of the lower isolation region (25), and at the same time the second epitaxial layer is formed. The bottom of the diffusion region formed from the surface of the layer (27) also has the smallest lateral diffusion, so the two are sufficiently separated, and the lower isolation region (25) occupies the element isolation on the surface of the second epitaxial layer (27). The area will not be larger than the opening area of the upper isolation region (30).

(G) Effects of the Invention As described above, according to the present invention, a linear transistor ( 40 ) having a higher withstand voltage than before and an IIL ( 41 ) with a higher speed than before can be combined, and a miniaturized low withstand voltage linear transistor ( 42 ) Can also coexist. Further, since the occupied area required for element isolation can be reduced, there is an advantage that the chip size can be reduced.

[Brief description of drawings]

1A to 1F are sectional views for explaining the present invention, and FIGS. 2 and 3 are sectional views for explaining a conventional example. (21) is a semiconductor substrate, (22) is a first buried layer, (24) is a second buried layer, (25) is a lower isolation region, (28) IIL base region, (30) is The upper isolation region, ( 40 ) is a high breakdown voltage linear transistor, ( 41 ) is an IIL, and ( 42 ) is a low breakdown voltage linear transistor.

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/8222 27/082 9169-4M H01L 21/76 J

Claims (1)

[Claims] 1. A step of depositing an impurity of opposite conductivity type to form a first buried layer on the surface of a semiconductor substrate of one conductivity type, and a first epitaxial layer of opposite conductivity type is formed on the entire surface of the substrate. And a step of depositing an impurity of opposite conductivity type to form a second buried layer on the IIL formation scheduled portion and the low breakdown voltage linear transistor formation scheduled portion on the surface of the first epitaxial layer and separating the elements. Is a step of doping an impurity of one conductivity type to form a lower isolation region, a step of forming a second epitaxial layer of the opposite conductivity type on the entire surface of the first epitaxial layer, and a surface of the second epitaxial layer A step of implanting an impurity of one conductivity type to form the base region of the IIL, and heating the entire substrate to move the lower isolation region vertically from the surface of the first epitaxial layer to the substrate. Driving in until reaching a predetermined depth, and driving in the base region of the IIL to a predetermined depth, and forming an upper isolation region of one conductivity type in a region corresponding to the lower isolation region of the second epitaxial layer, Forming a device isolation by connecting to the lower isolation region, and selectively diffusing one conductivity type impurity on the surface of the second epitaxial layer to form an injector region of the IIL and a low breakdown voltage and high breakdown voltage linear transistor. A step of forming a base region; and a step of selectively diffusing an impurity of opposite conductivity type on the surface of the second epitaxial layer to form a collector region of IIL and an emitter region of a low breakdown voltage and high breakdown voltage linear transistor. A method of manufacturing a semiconductor integrated circuit, comprising: