JP2613073B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Collector-emitter breakdown voltage (BV
_CED ) and a method of manufacturing the same. A semiconductor device capable of improving the collector-emitter breakdown voltage (BV _CED ) of a desired transistor without changing the depth of the transistor, and a method of manufacturing the same. A first buried diffusion layer formed including at least immediately below an emitter region of the transistor, A semiconductor device including a portion penetrating the second buried diffusion layer shallower than the first buried diffusion layer, and a step of selectively forming the first buried diffusion layer on the substrate; A step of selectively forming a second buried diffusion layer shallower than the first buried diffusion layer in a region other than the first buried diffusion layer; forming an epitaxial layer over the entire surface; Selectively forming a film, penetrating the second buried diffusion layer from the insulating film. And a step of forming a transistor including at least an emitter region on the first buried diffusion layer.

[Industrial applications]

The present invention Collector-emitter breakdown voltage (BV
_{The present} invention relates to a method for manufacturing a semiconductor device with improved _CED .

[Conventional technology]

Semiconductor devices separated by, for example, Conventionally, most bipolar transistors have a collector-emitter breakdown voltage (BV _CED ) of 6 to 8 V, and are often used in gate arrays and static RAMs.

However, when a bipolar transistor having a collector-emitter breakdown voltage of 10 V or more is used for a programmable ROM or the like, the following problem occurs.

In order to improve the withstand voltage between the collector and the emitter, the thickness of the epitaxial layer may be simply formed to be thicker than the conventional one. However, when the thickness of the epitaxial layer is increased, element isolation is performed. Accordingly, it is necessary to deeply form it.

This is shown in the center of FIG. Referring to the high-speed bipolar transistor formed on the left side, the conventional Of the epitaxial layer 16 and the second buried diffusion layer 13
A depth of about 5 μm should have been obtained from the sum of the thicknesses of the layers. However, in order to obtain a high withstand voltage bipolar transistor having a collector-emitter breakdown voltage of 10 V or more by making the epitaxial layer 16 thick, a depth of 8 μm or more is required. Becomes this Is formed by first etching away to a depth of 8 μm and then A technology for embedding is required. But now The limit is about 5 μm, and if it is deeper than this, it becomes very difficult to secure the stability of the process.

Therefore, it is desired to improve the collector-emitter breakdown voltage by means other than the above.

[Problems to be solved by the invention]

Thus, the conventional In a semiconductor device and a method for manufacturing the same separated by Has to be formed deeply, and there is a problem in securing the stability of the process.

Therefore, the present invention It is an object of the present invention to provide a semiconductor device capable of improving the collector-emitter breakdown voltage (BV _CED ) of a desired transistor without changing the depth of the transistor, and a method of manufacturing the same.

[Means for Solving the Problems] The problem is that in a semiconductor device separated by a U-groove, a first buried diffusion layer formed including at least immediately below an emitter region of a transistor, A portion penetrating the second buried diffusion layer, which is shallower than the first buried diffusion layer, wherein the first buried diffusion layer has a lower concentration than the second buried diffusion layer; A semiconductor device, wherein a high breakdown voltage element is formed in a region having a diffusion layer, and a low breakdown voltage element is formed in a region only of the second buried diffusion layer; The step of selectively forming the first buried diffusion layer, wherein the region other than the first buried diffusion layer is shallower than the first buried diffusion layer and has a concentration higher than that of the first buried diffusion layer. High second embedding A step of selectively forming a diffusion layer, a step of forming an epitaxial layer on the entire surface, and a step of selectively forming an insulating film for element isolation thereon, and a step of forming a U through the second buried diffusion layer from the insulating film. Forming a groove, wherein at least an emitter region for a high withstand voltage element is formed on the first buried diffusion layer;
Forming a transistor including an emitter region for a low-breakdown-voltage element on the buried diffusion layer described above.

[Action]

According to the means of the present invention, by forming the deep first buried diffusion layer so as to include at least immediately below the emitter region of the transistor, the withstand voltage between the collector and the emitter can be improved and the shallow second buried diffusion layer can be formed. To Through the element to perform element isolation, so that the Therefore, the device with high breakdown voltage can be separated from the transistor, so that the stability of the process can be secured.

〔Example〕

Hereinafter, the present invention will be specifically described with reference to the illustrated embodiments.

FIG. 1 is a sectional view showing the structure of an embodiment of the present invention, and FIGS. 2 (a) to 2 (e) are sectional views showing the steps of the embodiment of the present invention. In the figure, 11 is 12 is a first buried diffusion layer, 13 is a second buried diffusion layer, 14 is an emitter region, 15 is a substrate, 16 is an epitaxial layer, 17 is an insulating film, 18 is a collector region, and 19 is a collector-emitter region. .

In this embodiment, both a low-breakdown-voltage and high-speed bipolar transistor and a bipolar transistor requiring a high-breakdown voltage are formed simultaneously in the same process.

As shown in FIG. 1, the semiconductor device of the present embodiment
A deep first buried diffusion layer 12 is formed so as to include at least immediately below an emitter 14 region of the transistor;
Perform element isolation Are configured to penetrate the shallow second buried diffusion layer 13.

The first buried diffusion layer formed immediately below the emitter region is an n-type buried diffusion layer having a low concentration (10 ¹⁶ to 10 ¹⁸ cm ⁻³ ) and a depth of about 3 to 5 μm deeper than the conventional one. It is a diffusion layer. Conventionally, by forming this diffusion layer, 6
~ 8V collector-emitter withstand voltage of 10 ~ 13
V could be improved. Also Is used as the diffusion layer in the portion to be used, the n-type shallow second buried diffusion layer having the same concentration (10 ¹⁹ cm ⁻³ ) and depth (1.5 μm) as the conventional one is used. Can be used to perform element isolation. Can be sufficient.

Next, a method for manufacturing the semiconductor device of this embodiment will be specifically described below.

As shown in FIG. 2A, a P-type silicon substrate 15 is formed.
Is selectively diffused at predetermined positions to form an n-well layer serving as the first buried diffusion layer 12. The location where this selective diffusion is performed is a region where a high-breakdown-voltage transistor is formed, and is a position including at least the emitter region of the transistor. The diffusion concentration is about 10 ¹⁶ to 10 ¹⁸ cm ^-3 ,
The depth is 3 μm.

Next, as shown in FIG. 2 (b), a shallow second buried diffusion layer
Form 13. This diffusion layer is formed by diffusing arsenic (As) in a place other than the position where phosphorus is diffused first. Diffusion concentration is 10
¹⁹ cm ^-3 and a depth of 1.5 μm. The second buried diffusion layer 13 is the same as a conventionally used diffusion layer.

As shown in FIG. 2C, an n-type silicon epitaxial layer 16 is grown on the two diffusion layers to a thickness of 2 μm.

Next, as shown in FIG. 2D, an insulating film (SiO ₂ ) 17 is formed on the epitaxial layer 16 by performing selective diffusion by a selective oxidation (LOCOS) method to perform element isolation to a thickness of about 6000 °. In order to further separate the elements, a depth of about 5 μm passes through the insulating film 17 and penetrates the second buried diffusion layer 13. Are formed respectively.

Then, as shown in FIG. 2 (e), Embedded in polysilicon Is completed, and a collector region 18, an emitter region 14, and a collector-emitter region 19 are formed in each element formation region by the same process as in the related art. In forming this element, the compensating diffusion of the collector is performed by implanting phosphorus (P ⁺ ) at a dose of about 3 × 10 ¹⁵ cm ⁻² at 80 KeV. Diffusion between the collector and the emitter is performed by implanting boron (B ⁺ ) at a dose of about 5 × 10 ¹³ cm ⁻² at 35 KeV, and arsenic (As ⁺ ) is implanted at a dose of 4 × 10 ¹⁵ at 60 KeV.
This is performed by ion implantation of about cm ⁻² .

 Finally, each electrode is formed.

In the transistors thus formed in FIG. 2E, the right side is a high breakdown voltage transistor, and the left side is a low breakdown voltage and high speed transistor. By using the method for manufacturing a semiconductor device of this embodiment, a high breakdown voltage transistor and a low breakdown voltage transistor can be simultaneously formed in the same step. This was made possible only by partially adding the first buried diffusion layer to the structure of the conventional semiconductor device. Since the same transistor as in the related art can be used in common, only a desired transistor can be selectively increased in breakdown voltage.

〔The invention's effect〕

As described above, according to the present invention, It has become possible to improve the collector-emitter breakdown voltage of a desired transistor without changing the depth of the transistor.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the structure of an embodiment of the present invention, and FIGS. 2 (a) to 2 (e) are sectional views showing the steps of the embodiment of the present invention. In the figure, 12 denotes a first buried diffusion layer, 13 denotes a second buried diffusion layer, 14 denotes an emitter region, 15 denotes a substrate, 16 denotes an epitaxial layer, 17 denotes an insulating film, 18 denotes a collector region, and 19 denotes a collector-emitter region. .

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H01L 27/082 29/73

Claims (2)

(57) [Claims] 1. A semiconductor device separated by a U-groove (11), comprising: a first buried diffusion layer (12) formed at least immediately below an emitter (14) region of a transistor; ) Includes a portion penetrating the second buried diffusion layer (13) shallower than the first buried diffusion layer (12), and the first buried diffusion layer (12) is 13), a high breakdown voltage element is formed in a region having the first buried diffusion layer (12), and a low breakdown voltage element is formed in a region having only the second buried diffusion layer (13). A semiconductor device comprising an element formed. 2. A step of selectively forming a first buried diffusion layer (12) having a predetermined concentration on a substrate (15), wherein a first buried diffusion layer is formed in a region other than the first buried diffusion layer (12). A step of selectively forming a second buried diffusion layer (13) shallower than (12) and having a concentration higher than that of the first buried diffusion layer (12); And selectively forming an insulating film (17) for element isolation on the U-groove (11) penetrating the second buried diffusion layer (13) from the insulating film (17). Forming at least an emitter (14) region for a high breakdown voltage element on the first buried diffusion layer (12), and an emitter region for a low breakdown voltage element on the second buried diffusion layer (13). Forming a transistor included in the semiconductor device.