JP2595799B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mixed-type semiconductor device having an NPN transistor and a PNP transistor and a method of manufacturing the same.

[Conventional technology]

FIG. 2 is a cross-sectional view of a conventional semiconductor device in which an NPN transistor and a PNP transistor are mixed, and is a part of the device shown in FIG. 1 on page 87 of IEICE technical report SDM89-62.

As shown in the figure, the PNP region on the surface of the P-type substrate 1 and N
N ⁺ buried layer 2 and 3 are respectively formed in the PN region, together with the P ⁺ -type buried layer 4 is formed on the surface of the N ⁺ -type buried layer 2, between the PNP region and NPN region in the same step After a P ⁺ type buried layer 5 for element isolation is formed, an N type epitaxial layer 6 is formed by lamination.

In the PNP region, a low-concentration P-well layer 7 as a collector is formed in the N-type epitaxial layer 6 and an N-type base layer 8 is formed in the P-well layer 7.
A field oxide film 9 is formed, a P ⁺ emitter layer 10 is formed on the N-type base layer 8, a P ⁺ collector lead-out layer 11 is formed on the P-well layer 7, and an N ⁺ -type external base layer is formed on the N-type base layer 8. 12 is formed.

On the other hand, in the NPN region, the N-type epitaxial layer 6
Then, an N ⁺ -type collector extraction layer 13 and a P-type base layer 14 are formed, an N ⁺ -type emitter layer 16 is diffused from the polycrystalline silicon 15 into the P-type base layer 14, and P ⁺ The mold external base layer 17 is formed.

In FIG. 2, reference numeral 18 denotes a metal wiring, and 19 denotes a passivation film.

The breakdown voltage of the PNP transistor is determined by the distance that a depletion layer formed by the PN junction between the N-type base layer 8 and the P-well layer 7 extends in the low-concentration P-well layer 7 toward the P ⁺ -type buried layer 4. Therefore, during the growth of the N-type epitaxial layer 6, P-type impurities such as boron of the P ⁺ -type buried layer 4 float in the epitaxial layer 6 by auto-doping, and heat treatment during the formation of the P-well layer 7. In consideration of the fact that the P ⁺ -type buried layer 4 rises, the thickness of the N-type epitaxial layer 6 must be determined in consideration of the margin.
In order to obtain a breakdown voltage of V, about 4
A film thickness of μm is required.

On the other hand, arsenic or antimony, which is an N-type impurity used for the N ⁺ type buried layer 3, has a smaller diffusion coefficient than boron which is a P-type impurity. That is, the thickness of the N-type epitaxial layer 6 from the upper end of the N ⁺ -type buried layer 3 to the lower end of the P-type base layer 14 is larger than a desired value.

[Problems to be solved by the invention]

In the conventional case, as described above, in order to secure the withstand voltage of the PNP transistor, it is necessary to form the N-type epitaxial layer 6 thicker with an allowance for the floating of the P ⁺ -type buried layer 4. However, if the N-type epitaxial layer 6 is made thicker with a margin, as described above, the remaining epitaxial thickness of the N-type epitaxial layer 6 in the NPN transistor becomes too large than a desired value, and there is a problem in the breakdown voltage of the NPN transistor. On the other hand, there is a problem that the collector resistance is increased and the speed performance is reduced.

The present invention has been made in order to solve the above problems, and can secure a sufficient element withstand voltage without making the second conductivity type epitaxial layer unnecessarily thick unlike the related art. It is an object of the present invention to prevent a reduction in speed performance due to an increase in collector resistance or the like.

[Means for solving the problem]

A semiconductor device according to the present invention includes a low-concentration buried layer of a second conductivity type formed on a part of a surface of a substrate of a first conductivity type; A first conductivity type high-concentration buried layer located below a surface, a second conductivity type epitaxial layer formed on the entire surface of the substrate, and the high-concentration buried layer from the surface of the epitaxial layer; And a low-concentration layer of the first conductivity type formed on the high-concentration buried layer so as to reach the surface.

Further, as a method of manufacturing the same, a step of forming a low-concentration buried layer of the second conductivity type on a part of the surface of the substrate of the first conductivity type;
Impurities of the first conductivity type are ion-implanted into the low-concentration buried layer at a high energy of about 500 KeV or more and heat-treated, and the low-concentration buried layer is positioned so that the surface is located below the surface of the substrate. Forming a first conductivity type high concentration buried layer in the embedded layer, growing a second conductivity type epitaxial layer over the entire surface of the substrate, and forming the high concentration buried layer from the surface of the epitaxial layer. Forming a low concentration layer of the first conductivity type on the high concentration buried layer so as to reach the surface of the buried layer.

[Action]

In the present invention, since the high-concentration buried layer whose surface is located below the substrate is provided in the low-concentration buried layer, it is necessary to increase the thickness of the epitaxial layer involved in the withstand voltage of the element as in the conventional case. In addition, even if an epitaxial layer having a necessary minimum thickness is formed, a sufficient device withstand voltage is secured, and an increase in the collector resistance as in the related art is prevented.

In addition, a high-concentration buried layer is formed at a position sufficiently deep from the substrate surface because a high-concentration buried layer is formed by ion-implanting a first-conductivity-type impurity at a high concentration by high-energy implantation of about 500 KeV or more and performing heat treatment. Even if a layer is formed and the high-concentration buried layer rises due to a heat treatment in a subsequent step, the surface of the high-concentration buried layer can be positioned below the substrate surface.

〔Example〕

1A to 1I show an embodiment of a semiconductor device and a method of manufacturing the same according to the present invention, and the manufacturing steps will be described below.

First, as shown in FIG. 1A, by implantation or diffusion,
P ^- a PNP region of the surface of the mold substrate 21, concentration of about 1 × 10 ¹⁶ cm ^-3 of N ^- formed in 22 depth 2 to 5 [mu] m ^- low doped buried layer of type (called buried layer below N) After that, 1 × 10 ²⁰ cm
High concentration N ⁺ -type buried layer 23 ^-3 is formed to a depth 2-4 [mu] m, by heat treatment during the formation of this time N ⁺ -type buried layer 23,
The depth of the N ⁻ buried layer 22 becomes 5 to 8 μm, and then a thin oxide film 24 is formed on the entire upper surface of the substrate 21.

Then, as shown in FIG. 1B, a photoresist film 25 is applied and formed on the oxide film 24, the photoresist film 25 is patterned by photolithography, and an opening 26 is formed above the N ⁻ buried layer 22. , after the oxide film 24 is exposed in the opening 26, the photoresist film 25 as a mask, about 24MeV high energy boron dose of about 3 × 10 ¹⁴ cm ^-2 of (B)
There are ion-implanted, N ^- high density region 27 having a projected range r _p from the surface of the buried layer 22 to a depth of approximately 3.5μm is formed.

Next, as shown in Figure 1C, also as a mask the photoresist film 25, B dose of about 2 × 10 ¹² cm ^-2 are implanted at a low energy of about 200 KeV, N ^- the buried layer 22 low concentration region 28 is formed with r _p from the surface projected range to a depth of about 0.5 [mu] m, and subsequently the photoresist film 25 is removed, heat treatment at 950-1,100 ° C. is performed, as shown in 1D view , N ⁻ buried layer 22 includes a P ⁺ type high concentration buried layer (hereinafter referred to as P ⁺ buried layer) 29 and a P ⁻ type low concentration buried layer (hereinafter referred to as P ⁻ buried layer) 30. It is formed by lamination.

Further, after the oxide film 24 is removed, an N ⁻ -type epitaxial layer 31 is formed on the entire upper surface of the substrate 21 as shown in FIG. 1E, and a P-type channel cut region 32 is formed as shown in FIG. 1F. Then, after the trench insulating film 33 is formed and the device isolation is performed, the epitaxial layer 31 in the PNP region has a thickness of about 10 ¹⁶ cm ^−3.
The extent of P ^- low concentration diffusion layer of the type (hereinafter P ^- called diffusion layer) 34 is formed, the P ^- diffusion layer 34 is P ^- lead to buried layer 30, P ⁺ buried layer from the surface of the epitaxial layer 31 2 reaching the surface of 29
Layer structure P ^- constitute the low concentration layer.

Here, in FIG. 1F, reference numeral 35 denotes an insulating film formed on the entire upper surface of the epitaxial layer 31 and having an open PNP region and NPN region, and reference numeral 36 denotes a thin insulating film formed by thermal oxidation at the opening of the insulating film 34. It is.

Thereafter, as shown in FIG. 1G, P ⁻
Each of the diffusion layer 34 and the P ⁻ buried layer 30 is connected to the P ⁺ buried layer 29.
P ⁺ -type collector lead layer 37 is formed, N ⁺ -type collector lead layer 38 connected to the N ⁺ -type buried layer 23 is formed on a portion of the epitaxial layer 31 of the NPN region, the PNP region P ^- diffusion layers 34 An N-type base layer 39 is formed on the surface layer, and a P-type base 40 is formed on the surface layer of the epitaxial layer 31 in the NPN region.

Next, as shown in FIG. 1H, an insulating film 41 is formed on the entire upper surface, and openings are formed at the base position of the PNP region, the collector position and the emitter position of the NPN region of the insulating film 41,
A polycrystalline silicon film 42 is formed in each of these openings to diffuse an N-type impurity, an N ⁺ -type external base layer 43 is diffused and formed in an N-type base layer 39, and an N-type After the formation of the ⁺⁺ type emitter layer 44, the PNP of the insulating film 41 is formed.
Openings are formed at the collector position, the emitter position of the region, and the base position of the NPN region. P-type impurities are introduced from these openings, and a P ⁺⁺ type emitter layer 45 is formed in the N-type base layer 39. P ^{+ type} external base layer in P type base layer 40
46 is formed.

Then, as shown in FIG. 1I, the passivation film 47
Is formed on the entire upper surface, a contact hole is formed at an electrode position, a metal wiring layer 48 is formed, and a semiconductor device in which a PNP transistor and an NPN transistor are mixed is manufactured.

By the way, as described above, by implanting B ions into the N ⁻ buried layer 22 by high energy implantation, the first B
As shown in the figure, since the high-concentration region 27 can be formed at a position sufficiently deep from the surface of the N ⁻ buried layer 22, that is, the surface of the substrate 21, as shown in FIGS. 1E and 1F, P ^- Diffusion layer 34
Even when the P ⁺ and P ^- buried layers 29 and 30 are lifted during the formation of the substrate, the surface of the P ⁺ buried layer 29, that is, the interface between the P ⁺ and P ^- buried layers 29 and 30 is higher than the surface of the substrate 21. Can also be prevented from rising upward.

Therefore, even if the N ⁻ type epitaxial layer 31 has the minimum necessary thickness that satisfies the breakdown voltage of the NPN transistor, as shown in FIG. 1I, the PN junction between the P ⁻ diffusion layer 34 and the N type base layer 39 is reduced. Can be obtained as the distance L from the surface of the P ⁺ buried layer 29 to the desired breakdown voltage of the PNP transistor, and without increasing the collector resistance of the conventional NPN transistor. In addition, it is possible to prevent a reduction in speed performance.

In the above embodiment, the P ⁺ buried layer 29 and the P ⁻ buried layer 30 are formed in the N ⁻ buried layer 22, and then the
The case where the P ⁻ diffusion layer 34 is formed and the P ⁻ type low concentration layer has a two-layer structure has been described, but only the P ⁺ buried layer 29 is replaced with the N ⁻ buried layer 22.
Formed in a deep position inside, and then the epitaxial layer
By diffusion of P-type impurities from 31 surface, P ⁺ buried layer 29
Of course, a P ^- type low concentration layer reaching the surface of the substrate may be formed.

Further, in the above-described embodiment, the first conductivity type is described as P-type and the second conductivity type is described as N-type. However, the present invention can be similarly implemented in the opposite case.

〔The invention's effect〕

As described above, according to the semiconductor device of the present invention, since the high-concentration buried layer whose surface is located below the substrate is provided in the low-concentration buried layer, the thickness of the epitaxial layer is increased as in the related art. It is possible to secure sufficient device withstand voltage even if an epitaxial layer with a minimum thickness is formed without the need to perform the process, and to prevent a decrease in speed performance by preventing an increase in collector resistance as in the past. This is extremely effective as a mixed-type semiconductor device having PNP and NPN transistors.

According to the method of manufacturing a semiconductor device of the present invention,
A high-concentration buried layer is formed at a position sufficiently deep from the substrate surface by forming a high-concentration buried layer by ion-implanting a first-conductivity-type impurity at a high concentration by high-energy implantation of 500 KeV or more and performing heat treatment. Can be formed,
Even if the high-concentration buried layer rises due to the heat treatment in the subsequent process, the surface of the high-concentration buried layer can be located below the substrate surface, and it is necessary to make the epitaxial layer thick as in the past. Absent.

[Brief description of the drawings]

1A to 1I are cross-sectional views showing manufacturing steps of an embodiment of a semiconductor device and a method of manufacturing the same according to the present invention, and FIG. 2 is a cross-sectional view of a conventional semiconductor device. In the figure, 21 is a substrate, 22 is an N ^- buried layer, 29 is a P ⁺ buried layer,
Reference numeral 30 denotes a P ^- buried layer, 31 denotes an epitaxial layer, and 34 denotes a P ^- type diffusion layer. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A low-concentration buried layer of a second conductivity type formed on a part of a surface of a substrate of a first conductivity type, and a surface formed in the low-concentration buried layer has a surface higher than a surface of the substrate. A first conductive type high-concentration buried layer located below; a second conductive type epitaxial layer formed on the entire surface of the substrate; and a surface from the epitaxial layer to the surface of the high-concentration buried layer. A low-concentration layer of the first conductivity type formed on the high-concentration buried layer so as to reach the high-concentration buried layer. 2. A step of forming a second conductivity type low-concentration buried layer on a part of the surface of a first conductivity type substrate; High-concentration buried layer of the first conductivity type is formed in the low-concentration buried layer so that the surface is located lower than the surface of the substrate by ion-implanting a conductive-type impurity at a high concentration. A step of growing an epitaxial layer of a second conductivity type over the entire surface of the substrate; and forming a layer on the high concentration buried layer so as to reach the surface of the high concentration buried layer from the surface of the epitaxial layer. Forming a first-conductivity-type low-concentration layer.