JPS6422055A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS6422055A JPS6422055A JP62179293A JP17929387A JPS6422055A JP S6422055 A JPS6422055 A JP S6422055A JP 62179293 A JP62179293 A JP 62179293A JP 17929387 A JP17929387 A JP 17929387A JP S6422055 A JPS6422055 A JP S6422055A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- iil
- epitaxial layer
- isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
PURPOSE:To make the chip size small by selectively diffusing impurities of the opposite conductivity types into the surface of the second-layer epitaxial layer to form the collector region of an IIL and the emitter region of a linear transistor, thereby reducing the dedicated area required for element isolation. CONSTITUTION:In the surface of a first-layer epitaxial layer 23, antimony forming a second-layer buried layer 24 is deposited and boron ions forming an underside isolation region 25 are implanted. On the whole surface a second- layer epitaxial layer 27 is stacked, into the surface of which boron ions forming a base region 28 of an IIL 38 are implanted. A heat treatment is applied to the whole substrate 21 to upwardly and downwardly drive in the underside isolation region 25 and drive in the base region 28 of the IIL 38 to a predetermined depth. From the second-layer epitaxial layer 27 surface an upper side isolation region 30 is formed thereby to complete the element isolation, and from the second-layer epitaxial layer 27 surface a P-type impurity and an N-type impurity are sequentially diffused to form an NPN transistor 32 in the region where only a first-layer buried layer 22 is provided, and the IIL 38 in the region where the second-layer buried layer 24 is provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62179293A JPH0727969B2 (en) | 1987-07-17 | 1987-07-17 | Method for manufacturing semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62179293A JPH0727969B2 (en) | 1987-07-17 | 1987-07-17 | Method for manufacturing semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6422055A true JPS6422055A (en) | 1989-01-25 |
| JPH0727969B2 JPH0727969B2 (en) | 1995-03-29 |
Family
ID=16063292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62179293A Expired - Lifetime JPH0727969B2 (en) | 1987-07-17 | 1987-07-17 | Method for manufacturing semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0727969B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03165048A (en) * | 1989-11-22 | 1991-07-17 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
-
1987
- 1987-07-17 JP JP62179293A patent/JPH0727969B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03165048A (en) * | 1989-11-22 | 1991-07-17 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0727969B2 (en) | 1995-03-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080329 Year of fee payment: 13 |