JPH03165048A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the occurrence of deterioration in characteristics of an element by continuously changing the forming depth of an embedded layer. CONSTITUTION:An n-type epitaxial layer 18 is formed on a p-type semiconductor substrate 17. An insulating film 19 having a specified thickness is formed in a transistor forming region on the epitaxial layer 18. Thereafter, impurity ions 20 are implanted into the entire surface of the epitaxial layer 18 through the insulating film 19. Then, the insulating film 19 is removed. An activated n<+>-type embedded layer 22 whose depth is continuously changed is formed. Element isolating grooves are formed from the epitaxial layer 18 and the embedded layer 22 to the substrate 17. Insulating films and the like are deposited in the grooves, and element isolating regions 23 are formed. A deep peripheral circuit part of the embedded layer 22 and the shallow memory cell part of the embedded layer 22 are formed in the isolated pattern. At the peripheral circuit part and the memory cell part, n-p-n type transistors T1 and T2 are formed, respectively. Thus the formation of a step in the semiconductor layer is prevented, and the occurrence of the deterioration of the characteristics of the element can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a buried layer is formed in a semiconductor layer, and a method for manufacturing the same.

[Conventional technology]

Conventionally, as a semiconductor device in which a buried layer is formed in a semiconductor layer, there is, for example, a bipolar transistor type semiconductor memory device (hereinafter referred to as bipolar memory).This type of bipolar memory consists of a memory cell part and a peripheral circuit part, and α Charged particles (electrons and holes) are generated in the memory cell by radiation such as radiation, and the parasitic current caused by these charged particles causes the transistor in the memory cell to operate and the information stored in the memory cell to change. Error phenomena may occur.

In addition, in this type of bipolar memory, as the degree of integration progresses, the area of the memory cell part decreases, resulting in
The amount of charge accumulated in the memory cell portion decreases, the critical amount of charge at which soft errors occur decreases, and soft error resistance tends to deteriorate.

Therefore, in order to improve the soft error resistance performance, the distance between the base and collector of the transistor in the peripheral circuit section is reduced by thinning the epitaxial layer between the base layer and collector layer of the transistor in the memory cell section. The amount of charge that can be stored is increased by increasing the capacitance between the base and collector of the transistor in the memory cell portion, which is narrower than the distance between the base and collector.

At this time, by keeping the distance between the base and collector of the transistor in the peripheral circuit part wide, the soft error resistance can be improved without reducing the operating speed of the bipolar memory.

As a specific example of a bipolar memory with improved soft error resistance in this way, Japanese Patent Laid-Open No. 61-150
There is one described in Japanese Patent No. 266, which is manufactured by the steps shown in FIG.

First, as shown in FIG. 5(a), a p-type silicon substrate 1
An n-type collector layer 2 constituting a transistor in the peripheral circuit section and an n-type collector layer 3 constituting a transistor in the memory cell section are formed as buried layers at separate positions on the substrate 1 and both collector layers 2. , 3, and then a thin silicon oxide layer 5 and a silicon nitride layer 6 are sequentially formed on this epitaxial layer 4 to form a transistor in the memory sale section above the silicon nitride layer 6. A photoresist film 7 is formed outside the area.

Next, as shown in FIG. 5(b), using the photoresist film 7 as a mask, the silicon nitride film 6 in the transistor formation region of the memory cell portion is etched. After the silicon oxide film 5 and the surface layer of the epitaxial layer 4 are removed, the epitaxial layer 4 in the memory cell part is processed to be thinner than the epitaxial layer 4 in the peripheral circuit part, and the photoresist film 7 is removed, the peripheral circuit part and the epitaxial layer 4 are removed. The same figure (
C).

As shown in (d), npn type transistors are formed.

By the way, in FIGS. 5(c) and 5(d), 8 is a base electrode, 9 is a p- type intrinsic base region, 10.11 is a p+ type extrinsic base region, 12 is an emitter electrode, 13 is an n+ type emitter region, 14 is a collector voltage h, 15 is an n-type collector region, and 16 is a silicon oxide film.

In this way, by thinning the epitaxial layer 4 corresponding to the transistor formation region in the memory cell section by etching, the depth from the surface of the epitaxial layer 4 to both collector layers 2 and 3 is changed, and the base of the transistor in the memory cell section is changed. By narrowing the distance between the collectors and increasing their capacitance, it is possible to increase the critical charge amount at which a knot error occurs, and to improve soft error resistance.

[Problem to be solved by the invention]

In conventional semiconductor devices and their manufacturing methods, selective etching of the epitaxial layer 4 is performed in order to selectively change the thickness of the epitaxial layer 4 on the collector layer 2.3, which is a buried layer. , a step is formed on the surface of the epitaxial layer 4, and this step may cause a decrease in pattern accuracy during subsequent steps such as isolation region formation, transistor formation, wiring formation, etc., or during the deposition of an insulating film. There was a problem in that it caused deterioration of the film coverage, leading to deterioration of the characteristics of the ultimately formed element.

In addition, in the conventional method, the collector layer 2.
3 and selectively etching the epitaxial layer 4, the depth from the surface of the epitaxial layer 4 to both collector layers 2 and 3 is changed, so that buried layers with effectively different depths are formed. Another problem was that the number of steps required to form the .

By the way, as another example in which the depth of the buried layer is changed, there is a semiconductor integrated circuit consisting of a high speed transistor and a high voltage transistor as described in Japanese Patent Publication No. 1-31305. Since the step of forming the buried layer and the step of forming the second buried layer having a different depth are separate steps, the number of steps increases as in the example described above.

Furthermore, in these conventional examples, buried layers with different depths are formed in different transistor regions, and the depth of the buried layer does not change continuously, so the scope of application is limited to the above-mentioned. This method is limited to bipolar memories, semiconductor integrated circuits made of high-speed and high-voltage transistors, and cannot be applied when the depth of a buried layer changes continuously in one transistor region.

This invention was made in order to solve the above-mentioned problems, and it is possible to form a buried layer with a continuously changing depth in one process without creating a large step difference as in the conventional method. The purpose is to

[Means to solve the problem]

A semiconductor device according to the present invention is characterized in that a buried layer is formed in a semiconductor layer, and the depth of the buried layer changes continuously.

Further, as a manufacturing method, a film is formed on at least a part of the semiconductor layer, and impurity ions are implanted into the semiconductor layer from above the semiconductor layer on which the film is formed, depending on the presence or absence of the film and the thickness. It is effective to form a buried layer whose depth changes continuously.

[Effect]

In this invention, since the depth of the buried layer formed in the semiconductor layer changes continuously, unlike the conventional case where the thickness of the semiconductor layer on the buried layer is changed by selective etching etc. No steps are formed on the surface of the semiconductor layer, and deterioration of characteristics of the formed element is prevented.

In addition, since the buried layer is formed by ion implantation through the film, the buried layer with varying depth can be formed in one process, reducing the number of processes. Even if the depth needs to be changed, the desired buried layer can be easily obtained with fewer steps.

〔Example〕

FIG. 1 shows a first embodiment in which a semiconductor device and a method for manufacturing the same according to the present invention are applied to a bipolar memory, and each step will be explained below.

First, as shown in FIG. 1(a), an n-type epitaxial layer 18 that forms a semiconductor layer together with the substrate 17 is formed on a p-type semiconductor substrate 17 made of silicon or the like, and a memory cell portion on this epitaxial layer 18 is formed. After an insulating film 19 of a predetermined thickness is formed in the transistor formation region, impurity ions 20 are implanted into the entire surface of the epitaxial layer 18 through the insulating film 19 by an ion implantation method. Here, 21 is an implanted impurity.

At this time, when ions are implanted through the insulating film 19, the implantation depth becomes shallower than when ions are implanted without passing through the insulating film 19, and the implantation depth also changes depending on the film thickness of the insulating film 19. The thicker the film thickness, the shallower it becomes.
As shown in FIG. 1(a), the implantation depth of the impurity 21 in the memory cell portion where ions are implanted through the insulating film 19 is shallower than that in the peripheral circuit portion where ions are implanted without passing through the insulating film 19.

Next, the insulating film 19 is removed, and the implanted impurities are activated by annealing, etc., to form an n-type buried layer 22 with a continuously varying depth, as shown in FIG. 1(b). be done.

Then, as shown in FIG. 1C, an element isolation groove is formed from the epitaxial layer 18 and buried layer 22 to the substrate 17, and an insulating film or the like is deposited in this groove to form an element isolation region 23. , the deep peripheral circuit part of the buried layer 22 and the shallow memory cell part of the buried layer 22 are formed separately, and then, as shown in FIG.
Pn-type transistors TI and T2 are formed, respectively.

By the way, in FIG. 1(d), 24 is a base electrode,
25 is a p-type base region, 26 is an emitter electrode, and 27 is an n-type base region.
28 is a collector electrode, 29 is an n-type collector region, and 30 is a silicon oxide film.

In this way, since the implantation depth of the impurity is changed by ion implantation through the insulating film 19, the buried layer 22 whose formation depth continuously changes can be formed in one process, and the memory cell Of course, by increasing the capacitance between the base and collector of the transistor T2 in the section, it is possible to improve the soft error resistance performance, and it is also possible to prevent the occurrence of the step difference that occurs in conventional bipolar memory, and improve the characteristics of the element. Deterioration can be prevented.

Next, FIG. 2 is a sectional view of the second embodiment, and the difference in FIG. 2 from FIG.
The reason is that the buried layer 22 is made shallower in the portion where it is to be formed.

This makes it possible to easily separate the buried layer 22 even if the depth of the element isolation region 23 is shallow, for example in a semiconductor device in which element isolation is performed by a selective oxidation method (LOCO5 method) in which it is difficult to form a deep element isolation region 23. Since the element isolation region 23 can be made shallow in this way, it is possible to reduce the level difference in unevenness occurring on the surface of the element isolation region 23 itself than before.

Further, FIG. 3 is a cross-sectional view of the third embodiment, which is applied to one transistor 1'1 (or T2) in FIG. 1(d), for example, and is different from this. This is because, in one transistor region, the buried layer 22 in the portion where the n+ type collector region 29 should be formed is made shallower.

By the way, this n+ type collector region 29 is provided to reduce the collector resistance of the transistor and enable high-speed operation, and is usually formed by thermal diffusion of impurities. This shortens the heat treatment time required to bond the n+ type buried layer 22 and the n+ type collector region 29, making it possible to suppress lateral diffusion of impurities. It is no longer necessary to increase the area of the transistor formation region in anticipation of diffusion, and it becomes possible to reduce the transistor dimensions and achieve high integration.

Furthermore, FIG. 4 is a cross-sectional view of the fourth embodiment, and after the buried layer 22 and element isolation region 23 are formed by the same steps as in FIGS. 1(a) to (C), FIG. A high voltage transistor T3 is formed to correspond to the transistor T1 in the peripheral circuit section in (d), and a high frequency transistor T4 is formed to correspond to the transistor T2 in the memory cell section.

However, in FIG. 4, 31 is a p-type external base region.

At this time, in the high-voltage transistor T3, the buried layer 22 is deepened to effectively thicken the epitaxial layer 18 in order to increase the base-collector breakdown voltage, and in the high-frequency transistor T4, high-speed operation is ensured. Therefore, the buried layer 22 is made shallow to effectively make the epitaxial layer 18 thinner.

In this way, a high voltage transistor T is placed on the same substrate 17.
Even when forming the high-frequency transistor T4 and 3, by continuously changing the depth of the buried layer 22 in one step by ion implantation, it can be easily performed with fewer steps than in the past. .

In the above embodiment, the case where ions are implanted through the insulating film 19 has been described, but it goes without saying that the implantation is not limited to the insulating film.

Furthermore, it goes without saying that the insulating film 19 may have a different thickness.

Further, although only one transistor is illustrated in FIG. 3, the depth of the buried layer may be changed for each of a plurality of transistors.

Further, in each of the embodiments described above, the case where an n p n-type transistor is formed has been described, but it goes without saying that a pnp type transistor can also be implemented in the same manner.

〔Effect of the invention〕

As described above, according to the present invention, since the depth of the buried layer formed in the semiconductor layer changes continuously, the thickness of the semiconductor layer on the buried layer is changed by selective etching or the like as in the conventional method. It is possible to prevent the formation of a step in the semiconductor layer as in the case where the semiconductor layer is changed, and it is possible to prevent the characteristics of the formed element from deteriorating.

In addition, as a method for forming such a semiconductor device, one method is to form a buried layer by ion implantation through the film.
A buried layer with varying depth can be formed in the process, reducing the number of steps. For example, even if it is necessary to change the depth of the buried layer within one element formation region, the desired The buried layer can be easily formed in a small number of steps, and is extremely effective in producing semiconductor devices such as various integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of each step of an embodiment of a semiconductor device and a method for manufacturing the same according to the present invention, FIGS. 2, 3, and 4 are sectional views of other embodiments, and FIG. 5 is a conventional method. FIG. 3 is a cross-sectional view of each step of the method for manufacturing a semiconductor device of FIG. In the figure, 17 is a semiconductor substrate, 18 is an epitaxial layer, 19 is an insulating film, 20 is an impurity ion, and 22 is a buried layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (2)

[Claims] (1) A semiconductor device in which a buried layer is formed in a semiconductor layer, characterized in that the depth of the buried layer changes continuously. (2) A film is formed on at least a portion of the semiconductor layer, and impurity ions are implanted into the semiconductor layer from above the semiconductor layer on which the film is formed, and the depth is continuous depending on the presence or absence of the film and its thickness. 1. A method for manufacturing a semiconductor device, comprising forming a buried layer having a different shape.