JPS63127567A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve information write characteristics while enhancing the degree of integration by making the quantity of flow-up of the region of a buried collector of a bipolar transistor for writing and reading information larger than a buried collector region of a bipolar transistor for a peripheral circuit. CONSTITUTION:A buried collector region 3 of a bipolar transistor Trn for writing and reading information for a p-n-p load type memory cell is constituted of a semiconductor region 3A and a semiconductor region 3B formed by an n-type impurity having a diffusion rate faster than the semiconductor region 3A. Consequently, the buried collector region 3 can be flowed up positively by the semiconductor region 3B. Accordingly, the volume of an epitaxial layer 2 can be reduced, storage carriers are decreased, and the information write characteristics of the memory cell are improved while the area of the memory cell can be minimized, thus enhancing the degree of integration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device, particularly a semiconductor integrated circuit device having a pievora transistor type memory.

[Conventional technology]

A pnp load type memory cell is known as a memory cell of a semiconductor integrated circuit device having a bipolar transistor type memory. This memory cell is composed of a flip-flop circuit consisting of two npn type bipolar transistors for reading and writing information and a pnp type bipolar transistor for loading.

has been done. The collector region is mainly composed of an n-type epitaxial layer laminated on top of a p-type semiconductor substrate and an n-type buried collector region. The base region is composed of a p-type semiconductor region formed on the main surface of the epitaxial layer. The emitter region is composed of an n-type semiconductor region formed on the main surface of the base region.

The load bipolar transistor uses the base region of the information writing/reading bipolar transistor as a collector region, and the collector region serves as a base region. The emitter region of the load bipolar transistor is composed of a p-type semiconductor region formed in the same process as the base region of the information write/read bipolar transistor.

In the memory cell configured in this manner, the information writing/reading bipolar transistor and the load bipolar transistor are surrounded by an element isolation region.

Electrically isolated from other areas.

A semiconductor integrated circuit device having a bipolar transistor type memory is described, for example, in Nikkei Electronics, published by Nikkei McGraw-Hill, March 10, 1986, pp. 199-217.

[Problem that the invention seeks to solve]

The inventor found that the following problem occurred.

In the memory cell, holes flowing into the base region (n-type epitaxial layer) from the emitter region (p-type semiconductor region) of the load bipolar transistor are held as accumulated carriers. This accumulated carrier hinders the information inversion operation of the flip-flop circuit of the memory cell and deteriorates the information writing characteristics (reduces the information writing operation speed). The accumulated carriers can be reduced by reducing the volume of the epitaxial layer (load bipolar transistor base region). Specifically, this is done by extending the collector region and emitter region (p-type semiconductor region) of the load bipolar transistor to a depth that is sufficient to contact the n-type buried collector region.

・'While applying the above-mentioned bipolar transition for load)'
) - Elongation of the collector region and emitter region of the star increases the planar area of the memory cell, resulting in an interlayer that reduces the degree of integration.

Furthermore, the stretching of the collector region and emitter region also stretches the base region of an npn bipolar transistor constituting one peripheral circuit, such as a decoder circuit or an input/output circuit. This stretching of the base area is
Reduce the spacing between the base area and the embedded collector area, or
Ebisu brings the two into contact. For this reason, in the bipolar transistor for peripheral circuits, the collector-base capacitance increases, resulting in a problem that the operating speed decreases.

A first object of the present invention is to provide a semiconductor integrated circuit device having a bipolar transistor type memory.

It is an object of the present invention to provide a technology capable of improving information writing characteristics and increasing the degree of integration.

A second object of the present invention is to achieve the first object and to
An object of the present invention is to provide a technology that can increase the operating speed of bipolar transistors for peripheral circuits.

The above and other objects and novel features of the present invention will become apparent from the description of the present invention and the accompanying drawings.

[Means for solving problems]

An overview of one typical invention disclosed in this application is as follows.

In a semiconductor integrated circuit device having a bipolar transistor type memory, the amount of rise of the buried collector region of a bipolar transistor for reading and writing information in a pnp or npn load type memory cell is compared with the buried collector region of a bipolar transistor for two peripheral circuits. Large structure.

[For production]

According to the above-mentioned means, the volume of the epitaxial layer can be reduced by the rise of the buried collector region, thereby reducing accumulated carriers and improving the information writing characteristics of the memory cell. Since the memory cell area can be reduced by reducing each of the collector region and emitter region, the degree of integration can be improved.

Furthermore, since the amount of rise in the buried collector region of the bipolar transistor for the peripheral circuit can be reduced and the collector-base capacitance can be reduced, the operating speed of the peripheral circuit can be increased.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A configuration of the present invention will be described below along with an embodiment in which the present invention is applied to a semiconductor integrated circuit device having a bipolar transistor type memory configured with a pnp load type memory cell.

In addition, in all the episodes, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

〔Example〕

A memory cell of a bipolar transistor type memory mounted on a semiconductor integrated circuit device which is an embodiment of the present invention is
Figure (equivalent circuit diagram) shows.

As shown in FIG. 1, the pnp load type memory cell is provided at the intersection of complementary digits IDC extending in the direction of two rows, word aWL and data holding line it1 extending in the direction of one column. The pnp load type memory cell includes two load pnp bipolar transistors T r p and four information writing/reading npn bipolar transistors T.
It is composed of a flip-flop circuit consisting of r and n.

Next, the specific structure of this embodiment will be explained with reference to FIG. 2 (a sectional view of main parts of a memory cell and peripheral circuit elements).

As shown in FIG. 2, on the top of the p-type semiconductor substrate 1,
The n'' type epitaxial layer 2 is gIM-formed.

An inter-element isolation region 4 is provided on the main surface of the epitaxial layer 2 between the bipolar transistor formation regions forming each of the memory cell and the peripheral circuit element. The element isolation region 4 is composed of a trench 4A, an insulating film 4B, and a buried member 4C.

The groove 4A is a bipolar transistor T for reading and writing information.
r n and a load bipolar transistor Trp, surrounding the memory cell and defining its area. Further, the trench 4A surrounds the peripheral circuit npn bipolar transistor Tr of the peripheral circuit and defines its area. The groove 4A has a U-shape, and its bottom reaches the semiconductor substrate l.

The absolute R film 4B is formed along the silicon surface of the semiconductor substrate 1 etc. exposed in the trench 4A. This insulating film 4B is formed of, for example, a silicon oxide film, a silicon nitride film, or a composite film thereof.

The embedded member 4C is embedded in the 1f14A via the ala4B. The embedded member 4A is made of, for example, polycrystalline silicon having the same coefficient of thermal expansion as that of the semiconductor substrate 1 and Evitacal M2. Further, the embedded member 4C may be formed of an insulating film.

p II For information writing/reading of p-load type memory cells (np
n type) bipolar transistor T r n has a collector region Cn, a base region [3
n and an emitter region En.

The collector region Cn includes a buried collector region 3 consisting of an n-type semiconductor region 3A and an n-type semiconductor region 3B, an n'-type semiconductor region 5 for pulling up which is connected to the buried collector region 3 and raises its potential, and an epitaxial layer. It consists of 2. The n゛゛ semiconductor region 3A of the buried collector region 3 is the fourth
As shown in the figure (impurity concentration distribution diagram of memory cell), it is formed of an n-type impurity such as antimony (Sb). n
The type semiconductor region 3B is formed of an n-type impurity such as arsenic (As), phosphorus (P), etc., which has a faster diffusion rate than the n-type impurity, or a combination of these and antimony (Sb). The buried collector region 3 configured as described above can be formed by introducing n-type impurities that form the semiconductor regions 3A and 3B into the surface of the semiconductor substrate 1 in advance, and then stacking the epitaxial layer 2.

In particular, the semiconductor region 3B has n
Since the diffusion rate of the type impurity is fast, the distance from the base region Bn (or Cp + h p , 6) can be significantly reduced, or it is possible to contact it.

The base region Bn is composed of a p-type semiconductor region 6 provided on the main surface of the epitaxial layer 2. The emitter region En is composed of an n-type semiconductor region 7 provided on the main surface of the base region Bn.

The load (pnp type) bipolar transistor TrP is
Collector region cp, base region BP and emitter region E
It is composed of P. The collector region Cp is the base region B of the bipolar transistor T r n for reading and writing information.
It is composed of n. The base region Bp is composed of a collector region (buried collector region 3 and epitaxial layer 2).

The emitter region Ep is formed in the same process as the base region Bn, and a p-type semiconductor region 6 provided opposite thereto.
It consists of

An electrode lO is connected to each of the semiconductor regions 5.6 and 7. The electrode 10 is formed of, for example, an aluminum film, and is connected to each semiconductor region 5, 6, 7 through a connection hole 9 formed in an interlayer insulating film 8.

In this way, the buried collector region 3 of the information writing/reading bipolar transistor T r n of a pnp load type memory cell is divided into a semiconductor region 3A and a semiconductor region 3B formed of an n-type impurity having a faster diffusion rate than the semiconductor region 3A. With this structure, the buried collector region 3 can be actively raised in the semiconductor region 3B, so that the volume of the epitaxial layer 2 can be reduced. epitaxial layer 2
The reduction in the volume of the load bipolar transistor TrP
Since the amount of holes flowing from the emitter region Ep to the base region Bp can be reduced and accumulated carriers can be reduced, the information inversion operation of the flip-flop circuit can be facilitated.
Information writing characteristics (information writing operation speed) can be improved.

Moreover, in the buried collector region 3, since n-type impurities are present in the region defined by the element isolation region vi4, the collector region Cp (base region Bn) and emitter region EP are reduced in plan. be able to. This reduction is
The area of the pnp load type memory cell can be reduced and the degree of integration can be improved.

On the other hand, peripheral circuits such as bipolar transistors Tr used as decoder circuits and input/output circuits
is composed of a collector region kJiC, a base region B, and an emitter region E, as shown on the left side of FIG. The collector region C is composed of a buried collector region 3 formed of an ri' type semiconductor region 3A. The base region B is composed of a P-type semiconductor region 6. Emitter area E
is composed of a + type semiconductor region 7.

As shown in FIG. 3 (impurity concentration distribution diagram of peripheral circuit elements), the buried collector region 3 is composed only of a semiconductor region 3A formed of rl type impurities such as Sb.

In this way, by configuring the buried collector region 3 of the bipolar transistor Tr for the peripheral circuit with the semiconductor region 3A formed of the n-type impurity with a slow diffusion rate, the protrusion of the buried collector region 3 can be reduced, Since the collector region (embedded collector region 3) C and the base region B can be sufficiently spaced apart, the space between the collector bases can be reduced. This reduction in collector-base capacitance can increase the operating speed of the bipolar transistor Tr for one peripheral circuit.

In other words, one aspect of the present invention is the buried collector region 3 (3A and 3B) of the bipolar transistor T r n for reading and writing information.
The rise amount of the bipolar transistor T for peripheral circuits is
It is thicker than the buried collector region 3 (3A) of R. By doing so, it is possible to improve the information writing characteristics, improve the degree of integration, and further increase the operating speed.

Although the invention made by the present inventor has been specifically explained above based on the above embodiments, 5 the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in one embodiment of the present invention, an npn load type memory cell may be configured with a pnp type bipolar transistor for information writing/reading and an npn type bipolar transistor for load.

Further, the present invention can be applied not only to a semiconductor integrated circuit device on which only a bipolar transistor is mounted, but also to a semiconductor integrated circuit device on which a bipolar transistor and a complementary MISFET are mounted.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects that can be obtained by typical ones are as follows.

In a semiconductor integrated circuit device having a bipolar transistor type memory, improving the information writing characteristics of the memory cell,
In addition to reducing the area of memory cells and increasing the degree of integration,
The operating speed of peripheral circuits can be increased.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram showing a memory cell of a bipolar transistor type memory mounted on a semiconductor integrated circuit device which is an embodiment of the present invention, and FIG. 2 shows specific details of the memory cell and peripheral circuit elements. 3 and 4 are impurity concentration distribution diagrams of one peripheral circuit element and one memory cell, respectively. In the figure, 1... semiconductor substrate, 2... epitaxial layer, 3.3A, 3B, 5, 6.7-... semiconductor region, Tr
Mouth: Bipolar transistor for reading and writing information, Tr
p: bipolar transistor for load, Tr: bipolar transistor for peripheral circuit.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device having a memory cell composed of an information writing/reading bipolar transistor and a load bipolar transistor, and a peripheral circuit bipolar transistor, wherein the information writing/reading bipolar transistor and a bipolar transistor for the peripheral circuit is constructed of an npn type or a pnp type having a buried collector region, and the amount of rise of the buried collector region of the information writing/reading bipolar transistor is determined by the amount of rise of the buried collector region of the bipolar transistor for the peripheral circuit. 1. A semiconductor integrated circuit device characterized by having a larger collector region than the integrated collector region. 2. The memory cell is separated from other regions by an element isolation region formed by a groove surrounding the bipolar transistor for reading and writing information and the bipolar transistor for load, and the bipolar transistor for peripheral circuit is also separated from other regions. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is separated from other regions by the element isolation region. 3. The buried collector region of the information writing/reading bipolar transistor is formed of n-type impurities such as As, P, or a combination of these and Sb, and the buried collector region of the peripheral circuit bipolar transistor is formed of Sb or the like. The semiconductor integrated circuit device according to claim 1 or 2, characterized in that the semiconductor integrated circuit device is formed of n-type impurities. 4. Claims 1 to 4, characterized in that the collector region of the information writing/reading bipolar transistor is configured to contact each of the collector region and emitter region of the load bipolar transistor. Each semiconductor integrated circuit device according to item 3.