JPH0536700A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce a collector series resistance of a high output P-N-P transistor and to reduce its occupying area. CONSTITUTION:An emitter region 27 is surrounded by an outer part 26a and an extended part 26b of a collector leading region to form a unit transistor 31, and a plurality of the transistors 31 are disposed adjacently to form a unit transistor. One base contact region 28 is formed at the center of a pattern, and a base bias is applied to all the plurality of the transistors 31.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reduction of V _{CE (sat)} of a vertical PNP transistor incorporated in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A vertical PNP transistor conventionally incorporated in a semiconductor integrated circuit (IC) is disclosed in, for example, Japanese Patent Laid-Open No. 59-59.
-212170. 5 and 6
Is a plan view and a sectional view taken along the line CC of the vertical PNP transistor, where (1) is a P-type semiconductor substrate, (2) is an N-type epitaxial layer formed by stacking on the substrate (1),
(3) is an N ⁺ -type buried layer formed by being buried in the surface of the substrate (1), and (4) is a P ⁺ -type top and bottom that penetrates the epitaxial layer (2) so as to surround the buried layer (3). An isolation region, (5) is an island region formed in an island shape by the upper and lower isolation regions (4), and (6) is formed by being diffused upward from the surface of the substrate (1) so as to overlap the buried layer (3). ⁺ Type collector buried layer, (7) is a P type emitter region formed on the surface of the island region (5) corresponding to the collector buried layer (6), (8)
Is a P-type collector lead-out region reaching the collector buried layer (6) from the surface of the island region (5) so as to surround the emitter region (7), and (9) is the collector buried layer (6) and the collector lead-out region ( 8) a base region formed of an epitaxial layer (2) completely partitioned by and (10)
Is an N ⁺ base contact region, (11) is an oxide film,
Reference numerals (12), (13) and (14) denote an emitter electrode, a collector electrode and a base electrode which make ohmic contact with each region through a contact hole (15) formed by opening the oxide film (11).

In the above vertical PNP transistor, when this transistor is used as an output transistor, conventionally, the emitter region (7) is arranged in a ring shape, and a base contact is formed in the center of the ring-shaped emitter region (7). A pattern with areas (10) is used.

[0004]

However, in the ring-shaped emitter, when the emitter region (7) is divided into cells per unit area and considered, the collector lead-out region (8) is equal to one cell. Instead of being surrounded by a distance, it is surrounded by a shape in which an approaching portion and a distant portion are mixed. Then, the collector current mainly flows through the collector lead-out region (8) in the close portion, and the far portion can hardly contribute, so that the collector series resistance becomes large. Since the ring-shaped emitter transistor can be considered as the one cell connected in parallel, the ring-shaped emitter transistor has a drawback that the collector series resistance is large. Further, there is a drawback that the occupied area is large.

[0005]

The present invention has been made in view of the above-mentioned conventional problems, and one emitter region (2
7) is a pattern in which the collector lead-out region (26) surrounds as one unit, a plurality of patterns are arranged adjacent to each other, and a part of the portion of the collector lead-out region (26) shared by the plurality of emitter regions (27) is arranged. The base contact region (28) is arranged in the removed portion so as to be equidistant from all of the emitter regions (27).

[0006]

According to the invention, one emitter region (27)
Since most of its periphery is surrounded by the collector lead-out region (26), the collector series resistance can be reduced more than that of the ring-shaped emitter. Further, since the base contact region (28) is arranged in the portion surrounded by the emitter regions (7) and the collector lead-out region (26) is removed, the occupied area can be reduced.

[0007]

An embodiment of the present invention will be described in detail below with reference to the drawings. 1 is a plan view showing a vertical PNP transistor of the present invention, FIG. 2 is a sectional view taken along line AA of FIG. 1, and FIG. 3 is a sectional view taken along line BB of FIG. 2 or 3,
(21) is a P-type silicon semiconductor substrate, (22) is an island region obtained by separating the epitaxial layer formed on the substrate (21) by a P ⁺ isolation region (23), and (24) is embedded in the surface of the substrate (21). N ⁺ type buried layer formed by (2
5) is a P ⁺ -type buried layer formed to overlap the N ⁺ -type buried layer (24), (26) is a P ⁺ -type collector lead-out region reaching the collector buried layer (25) from the surface of the island region (22), (27) is P ⁺ formed on the surface of the island region (22)
Type emitter region, (28) is a collector buried layer (2
5) is an N ⁺ type base contact region for giving a base bias to the base region surrounded by the collector lead-out region (26), (29) is an oxide film, and (30) is an electrode. If the N-type impurity is diffused into the region serving as the base to make the concentration higher than the impurity concentration of the epitaxial layer, the vertical PNP transistor has a high f _T.

In FIG. 1, each emitter region (27) is formed to have a minimum size, and a total of four emitter regions (27) are equidistant from each other at positions corresponding to the corners of the square. It is arranged. A ring-shaped collector lead-out region (2
An outer portion (26a) of 6) is formed and a collector lead-out region (26) surrounds each of the emitter regions (27).
To form an extended portion (26b) of the. The extended portion (26b) of the collector lead-out region (26) is connected to approximately the center of one side of the square formed by the outer portion (26a) of the collector lead-out region (26), and is centered from each of the four sides of the square. It is growing toward you.

Each of the emitter regions (27) is surrounded on two sides by the outer portion (26a) of the collector lead-out region (26), and the remaining two sides are extended by the collector lead-out region (26) (26b). One unit transistor ( 31 ) is formed in an arrangement surrounded by four, and four unit transistors ( 3 ) are formed.
1 ) are adjacent to each other to form one unit. At the intersection of two diagonal lines connecting the four emitter regions (27), that is, at the center of the square formed by the four emitter regions (27), a base contact region that applies a base bias to the four unit transistors ( 31 ). (28) is arranged. The base contact region (28) is equidistant from all emitter regions (27) to equalize its base bias.

The extended portion (2) of the collector lead-out region (26)
6b) is an extended portion (26) of the collector lead-out region (26).
b) and the extended portion (26b), and up to the position where the collector lead-out region (26) and the base contact region (28) are not connected by lateral diffusion.
Close to 8). When configuring an output PNP transistor, a large number of the above unit units are arranged adjacent to each other in one island region (22) and are connected in parallel with an Al electrode (30) through each contact hole (32). To do.

In the PNP transistor of the present invention, unit transistors ( 31 ) each having the smallest emitter size are connected in parallel to form one unit, and the periphery of each emitter region (27) is located outside the collector lead-out region (26) (26a). )
And the extended portion (26b) are substantially completely equidistant,
The collector series resistance can be made small. More specifically, the unit transistor ( 31 ) of the present application has the same collector series resistance as that of the pattern in which the collector derivation region surrounds the minimum size emitter, which can minimize the collector series resistance, and the unit transistor ( 31 ) of the present application has the same collector series resistance. Since the unit transistors ( 31 ) are connected in parallel, the current capacity can be increased and at the same time the collector series resistance can be kept low.

Further, according to the present application, the base contact region (28) is not arranged outside the collector lead-out region (26), but is arranged in a portion surrounded by a plurality of emitter regions (27) with a minimum size, and four base contact regions (28) are arranged. Since only one base contact is required for the unit transistor ( 31 ), the pattern size can be reduced. FIG. 4 shows a second embodiment of the present invention. In this embodiment, the emitter region (27) has a vertically long shape, and two unit transistors ( 31 ) are combined into one unit transistor. The overall dimensions are the same as in the previous embodiment.

In this embodiment, since the emitter region (27) is extended, the linearity of the collector current can be extended as compared with the previous embodiment.

[0014]

As described above, according to the present invention,
Since the unit transistors ( 31 ) of small size and emitter size are connected in parallel, the collector series resistance is small, and there is an advantage that a high output PNP transistor with a small saturation voltage V _{CE (sat)} can be provided. Further, since it is sufficient to provide one base contact region (28) for four unit transistors ( 31 ), there is an advantage that the occupied area can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view for explaining the present invention.

FIG. 2 is a sectional view taken along the line AA of FIG.

3 is a sectional view taken along line BB of FIG.

FIG. 4 is a plan view showing a second embodiment.

FIG. 5 is a plan view for explaining a conventional example.

FIG. 6 is a sectional view taken along line CC of FIG.

Claims (3)

[Claims] 1. A semiconductor substrate of one conductivity type, a reverse conductivity type epitaxial layer formed on the substrate, island regions in which the epitaxial layer is separated into islands, and one conductivity buried in the bottom of the island region. -Type collector buried layer, one-conductive-type emitter region arranged on the surface of the island region so as to be spaced apart from each other, and equidistant from each of the emitter regions on the surface of the island region. A reverse-conductivity-type base contact region arranged at a position such that: an outer part of a one-conductivity-type collector lead-out region that extends from the surface of the island region to the collector buried layer and surrounds the periphery of each emitter region; Continuously extending from the outer portion of the collector lead-out region toward the base contact region so that each of the emitter regions is surrounded by the collector lead-out region. The semiconductor integrated circuit characterized by comprising a extending portion of the collector lead region. 2. A semiconductor substrate of one conductivity type, a reverse conductivity type epitaxial layer formed on the substrate, an island region in which the epitaxial layer is separated into islands, and one conductivity buried in the bottom of the island region. -Type collector buried layer, an emitter region of one conductivity type disposed on the surface of the island region so as to be spaced apart from each other and located at each corner of the square, and on the surface of the island region surrounded by the emitter regions. A base contact region of reverse conductivity type arranged at a position equidistant from all the emitter regions, and a collector of one conductivity type extending from the surface of the island region to the collector buried layer and surrounding the periphery of each emitter region. The outer side portion of the lead-out region and the emitter region are surrounded by the collector lead-out region. The semiconductor integrated circuit characterized by comprising a extending portion of the collector lead region extending toward the tact region. 3. The semiconductor integrated circuit according to claim 1, wherein a region surrounded by the outer portion of the collector lead-out region is one transistor unit, and a large number of the units are connected in parallel.