JPS55146964A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55146964A
JPS55146964A JP4547780A JP4547780A JPS55146964A JP S55146964 A JPS55146964 A JP S55146964A JP 4547780 A JP4547780 A JP 4547780A JP 4547780 A JP4547780 A JP 4547780A JP S55146964 A JPS55146964 A JP S55146964A
Authority
JP
Japan
Prior art keywords
type
layer
region
embedded
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4547780A
Other languages
Japanese (ja)
Other versions
JPS5643615B2 (en
Inventor
Osamu Ozawa
Koichi Kanzaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4547780A priority Critical patent/JPS55146964A/en
Publication of JPS55146964A publication Critical patent/JPS55146964A/en
Publication of JPS5643615B2 publication Critical patent/JPS5643615B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H01L27/0244—I2L structures integrated in combination with analog structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To facilitate the manufacture and to enhance the scale of integration of a semiconductor device of the type having I<2>L as a high-speed element and a bipolar transistor as a high dielectric element on the same chip, by providing two embedded layers on the I<2>L-type region. CONSTITUTION:An n<+>-type embedded layer 121 for I<2>L and an n<+>-type embedded layer 122 for bipolar transistor are formed by diffusion in a p-type Si substrate 11. Then, an n-type layer 13 is formed over the entire area by an epitaxial growth. Subsequently, the second n<+>-type embedded layer 14 is formed only in the portion of the layer 13 opposing to the layer 121 by diffusion, thereby to form the second epitaxial growth layer 15 over the entire surface. Thereafter, the laminated epitaxial layers 15 and 13 formed between the I<2>L forming region and the transistor region are separated from each other to form islands, by a p<+>-type region 16 reaching the substrate 11. Then, n-type impurities are diffused to form in the I<2>L an n<+>-type region 171 taking ground potential GND and enveloping both sides of the embedded layer 14 and, simultaneously, an n<+>-type region 172 for deriving collector in the transistor. Thereafter, active regions are formed in ordinary way.
JP4547780A 1980-04-07 1980-04-07 Manufacture of semiconductor device Granted JPS55146964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4547780A JPS55146964A (en) 1980-04-07 1980-04-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4547780A JPS55146964A (en) 1980-04-07 1980-04-07 Manufacture of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP11921776A Division JPS5344186A (en) 1976-10-04 1976-10-04 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS55146964A true JPS55146964A (en) 1980-11-15
JPS5643615B2 JPS5643615B2 (en) 1981-10-14

Family

ID=12720468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4547780A Granted JPS55146964A (en) 1980-04-07 1980-04-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55146964A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6228616U (en) * 1985-08-07 1987-02-21
JPH0516008Y2 (en) * 1986-08-05 1993-04-27
JPS641038U (en) * 1987-06-16 1989-01-06

Also Published As

Publication number Publication date
JPS5643615B2 (en) 1981-10-14

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