JPS6437861A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6437861A
JPS6437861A JP62194873A JP19487387A JPS6437861A JP S6437861 A JPS6437861 A JP S6437861A JP 62194873 A JP62194873 A JP 62194873A JP 19487387 A JP19487387 A JP 19487387A JP S6437861 A JPS6437861 A JP S6437861A
Authority
JP
Japan
Prior art keywords
layer
shaped
section
iil
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62194873A
Other languages
Japanese (ja)
Inventor
Toshiyuki Okoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP62194873A priority Critical patent/JPS6437861A/en
Publication of JPS6437861A publication Critical patent/JPS6437861A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize the increase of working speed and the elevation of breakdown strength simultaneously by substantially thinning the thickness of an epitaxial layer section through rediffusion in an IIL section and using approximately the whole thickness of the epitaxial layer in a linear transistor section. CONSTITUTION:A P-type epitaxial layer 22 is formed onto a substrate 21, and an N-type epitaxial layer 23 is shaped onto the layer 22. An N<+> type buried layer 24 is formed to the surface of the substrate 21 so as to share the borders with the layer 23, penetrating the layer 22, an N<+> type buried layer 26 is shaped to the surface of the layer 22, and a linear transistor 25 is formed to the surface of the layer 23 in a region in which only the buried layer 24 is shaped. An IIL 27 is formed to the surface of the layer 23 in a region in which the buried layer 26 is shaped. Accordingly, the thickness of the epitaxial layer section is thinned substantially by rediffusion in the upward direction of the layer 26 in the IIL 27, and approximately the whole thickness of the layer 23 can be used in the linear transistor 25.
JP62194873A 1987-08-04 1987-08-04 Semiconductor integrated circuit Pending JPS6437861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62194873A JPS6437861A (en) 1987-08-04 1987-08-04 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62194873A JPS6437861A (en) 1987-08-04 1987-08-04 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6437861A true JPS6437861A (en) 1989-02-08

Family

ID=16331727

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62194873A Pending JPS6437861A (en) 1987-08-04 1987-08-04 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6437861A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02215887A (en) * 1989-02-17 1990-08-28 Taguchi Kenkyusho:Kk Grouting

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02215887A (en) * 1989-02-17 1990-08-28 Taguchi Kenkyusho:Kk Grouting

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