JPS62214657A - Manufature of semiconductor integarated circuit device - Google Patents

Abstract

PURPOSE:To improve the integration of a semiconductor integrated circuit device by diffusing the lower diffused layer of upper and lower separating regions at the position deeper than the half of the thickness of an epitaxial layer, driving in a base region, and then diffusing the upper diffused layer of the separating regions until it arrives at the lower diffused layer. CONSTITUTION:A P-type emitter region 30 of approx. 1.5mum of diffusing depth is formed on a base region 27, and an N<+> type base contact region 31 of approx. 1.0mum of diffusing depth is then formed. The region 30 is formed in the step of diffusing the base of a normal NPN transistor, and the region 31 is formed in the step of diffusing the emitter of the normal NPN transistor. In this vertical NPN transistor, upper and lower separating regions 23 are coupled at the position shallower than the half of the thickness of an epitaxial layer 26, and a lower diffused layer 25 is formed wider than an upper diffused layer 28. Accordingly, the base region 27 of one of an element forming region is diffused sufficiently deeply, while the layer 28 and a collector leading region 29 can be formed shallow to suppress the lateral diffusion, thereby largely contracting the surface occupying area.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a method of manufacturing a semiconductor integrated circuit device, particularly a vertical PN
A method of manufacturing a device incorporating a P transistor or an IIL is related.

(B) Prior Art A method of manufacturing a semiconductor integrated circuit incorporating a conventional vertical PNP transistor will be described with reference to FIGS. 3(a) to 3(*).

First, as shown in FIG. 3(A), a P-type silicon substrate is used as the semiconductor substrate (1), antimony (Sb) is selectively deposited on the substrate (1), and an N+ type buried layer (2) is deposited.
), and boron (B) is deposited on the buried layer (2) and on the surface of the substrate (1) surrounding the buried layer (2) to form a collector buried layer (3) and upper and lower separation regions (4). Spread below! (5
) to form, do.

Next, as shown in FIG. 3(B), an N-type epitaxial layer (6) is formed to a predetermined thickness over the entire surface of the substrate (1) by a well-known vapor phase growth method. At this time, the buried layer (2), collector buried layer (3) and upper diffusion layer (5) are slightly diffused in the vertical direction.

Next, as shown in FIG. 3(c), an epitaxial layer (6) is formed.
Phosphorus (P) is selectively ion-implanted into a region corresponding to the collector buried layer (3) on the surface to attach a base region (7), which is one of the element formation regions. This ion implantation uses phosphorus (P) at a dose of 101! ,, 10IScrI′,
-8 and an acceleration voltage of 80 to 100 KeV.

Next, as shown in FIG. 3(d), an epitaxial layer (6) is formed.
From the surface, the upper diffusion layer (8) and the collector lead-out region (9) of the upper and lower separation regions (4) are diffused at about 1200°C for 3 to 4 hours, and at the same time the buried layer (2) and the collector buried layer (3 ) and an upper diffusion layer (5) are crawled up into the epitaxial layer (6) and diffused to drive in the base region (7). In this step, the upper diffusion layer (8) is connected to the upper diffusion layer (5), the epitaxial layer (6) is junction-separated, and the collector lead-out region (
9) reaches the collector buried layer (3) and forms the base region (7).
〉Surround all around. Specifically, when the thickness of the epitaxial layer (6) is 13 μm, the upper diffusion layer (8) is diffused to a depth of about 9 μm, and the upper diffusion layer (5) is raised to a depth of about 7 μm. In addition, the collector embedding M (3) is raised to a depth of about 7 μm, the buried layer (2) is raised to a depth of about 3 μm, and the base region (7) is shallower than the upper diffusion Ji (8) to a depth of about 4 μm due to the difference in impurity concentration. is diffused to a depth of

Next, as shown in FIG. 3(N), a P-type emitter region (10) with a diffusion depth of approximately 2 μm is formed on the surface of the base region (7), followed by an N+ type base contact region with a diffusion depth of approximately 1.5 μm. (11) is formed. The emitter region (10) is formed by the base diffusion process of the NPN transistor, and the base contact region (11) is formed by the emitter diffusion process of the NPN transistor.

In the vertical PNP transistor formed in this way, most of the active base is formed in the base region (7) formed by ion implantation, so the impurity concentration generates an internal drift electric field and holes injected from the emitter. , and a high gain-bandwidth product f1 can be obtained. Furthermore, since h□ of the vertical PNP transistor is determined almost entirely by the ion-implanted base region (7), it does not vary much even if the resistivity and thickness of the epitaxial layer (6) vary.

Local vertical PNP transistors are described, for example, in Japanese Patent Application Laid-Open No. 1983-
It is described in No. 211270.

Next, a method of manufacturing a semiconductor integrated circuit device incorporating a conventional IIL will be described with reference to FIGS. 4(a) to 4(*).

First, as shown in Figure 4, P is used as the semiconductor substrate (1).
Using a type silicon substrate, antimony (Sb) is selectively deposited on the substrate (1) to form an N0 type buried layer (2).
Boron (B) is deposited on the surface of the substrate (1) surrounding the buried layer (2) to form an upper diffusion layer (5) of the upper and lower separation regions (4).

Next, as shown in FIG. 4(b), an N-type epitaxial layer (6) is formed to a predetermined thickness over the entire surface of the substrate (1) by a well-known vapor phase growth method. At this time, the buried layer (2) and the upper diffusion layer (5) are slightly diffused in the vertical direction.

Next, as shown in FIG. 4(c), an epitaxial layer (6) is formed.
Boron (B) ions are selectively implanted into the surface to form a base region (7), which is one of the element formation regions. This ion implantation is performed at a dose of 10'A to 1014cTn1 and an acceleration voltage of 80 to 100 KeV.

Next, as shown in FIG. 4(d), an epitaxial layer (6) is formed.
The upper diffusion layer (8) of the upper and lower separation regions (4) from the surface is about 12
Diffusion takes place at 00°C for 3 to 4 hours, and at the same time, the buried layer (2) and upper diffusion layer (5) are crawled up into the epitaxial layer (6) and diffused, and the base region (7) is driven in. . In this step, the upper diffusion layer (8) is connected to the upper diffusion layer (5) to separate the epitaxial layer (6), and the base region (7) is shallower than the upper diffusion layer 1 (8) due to the concentration difference. Can be formed. Specifically, the thickness of the epitaxial layer (6) was set to 13μ.
If m, the upper diffusion layer (8) is diffused to a depth of approximately 9 μm, and the upper diffusion layer (5) is raised to a depth of approximately 7 μm.

Furthermore, the base region (7) is diffused to a depth of about 4 μm, and the buried layer (2>) is raised by about 3 μm.

Next, as shown in FIG. 4 (*), the P-type injector region (12) and base contact region (13) are simultaneously diffused to a diffusion depth of approximately 2 μm, and then to a diffusion depth of approximately 1.5 μm.
m N+ type collector regions (14) are formed.

Note that the injector region (12) and base contact region (13) are formed by the base diffusion process of the NPN l-transistor, and the collector region (14) is formed by the emitter diffusion process of the NPN transistor.

In III, which is formed in a similar manner, the active base is formed by the low concentration base region (7) formed by ion implantation, so a high reverse current amplification factor inverse β can be obtained, and the collector region (14) Variations in inverse β due to variations in can be suppressed.

IIL, which cuts the surface, is described in, for example, Japanese Patent Application No. 60-209387.

(c) Problems to be solved by the invention However, in the conventional manufacturing method, the upper and lower separated regions (4)
Since the upper diffusion layer (8) and the lower diffusion layer H (5) and the base region (7) (7), which is one of the element formation regions, are simultaneously diffused, the low concentration base region (7) (7) In order to diffuse sufficiently deeply, and the upper diffusion layer (8) is
In case 5), since the impurities that can be supplied are diffused in a smaller amount, it was necessary to diffuse the upper diffusion layer (8) considerably deeper than the upper diffusion layer (5). Therefore, the diffusion time is longer and the lateral diffusion of the upper diffusion layer (8) is also longer, so the epitaxial layer (8) is
6) There was a drawback that the surface area occupied was large and the degree of integration could not be further improved.

(d) Means for Solving the Problems The present invention has been developed in view of the above-mentioned drawbacks, and the upper diffusion layer (25) of the upper and lower separation regions (24) is formed by forming the upper diffusion layer (25) of the upper and lower separation regions (24) to be more than half the thickness of the epitaxial layer (26). The base region (27) (27) is one of the element forming regions.
) is driven in, and then the upper diffusion layer (28) of the upper and lower separation regions (24) is diffused until it reaches the upper diffusion layer (25). This is what we provide.

(f) Function According to the present invention, the upper diffusion layer (25) is raised in advance to a depth of at least half the thickness of the epitaxial layer R (26) and diffused.1. Since the upper diffusion layer (28) of the upper and lower isolation regions (24) is formed after driving in the element formation region at the same time, the low concentration base regions (27) (27) are sufficiently While it can be formed deeply, the upper diffusion layer (28) can be diffused shallower than the upper diffusion layer (25). As a result, the degree of integration can be significantly improved by suppressing the lateral diffusion of the upper diffusion [(28)] without causing deterioration of the characteristics of the element.

(F) Embodiment A method for manufacturing a vertical PNP transistor, which is a first embodiment of the present invention, will be described below with reference to FIGS. 1(A) to 1(F).

First, as shown in FIG. 1(A), a P-type silicon substrate is used as the semiconductor substrate (21), antimony (Sb) is selectively deposited on the substrate (21), and an N+ type buried layer (22) is formed. ) on the buried layer (22) and on the buried layer (2
2), boron (B) is deposited on the surface of the substrate (21) surrounding the collector buried layer (23) and the upper and lower separation regions (24).
) to form an upper diffusion layer (25).

Next, as shown in FIG. 1(b), an N-type epitaxial layer (26) is formed on the entire surface of the substrate (21) by a well-known vapor phase growth method.
is formed to have a thickness of about 7 μm. At this time, the buried layer (22), collector buried M3 (23), and upper diffusion layer (25) are slightly diffused in the vertical direction.

Next, as shown in FIG. 1(c), an epitaxial layer (26
) Phosphorus (P) is selectively ion-implanted into a region corresponding to the collector buried layer (23) on the surface to attach a base region (27), which is one of the element forming regions. This ion implantation is performed at a dose of phosphorus (P) of 1011 to IQ"am-1 and an acceleration voltage of 80 to 100 KeV.

Next, as shown in FIG. 1(d), approximately 1
By applying heat treatment at 200°C for 2 hours, the upper diffusion layer (25) of the upper and lower separation regions (24) and the collector buried layer (2) are heated.
3) is raised to a depth of more than half the thickness of the epitaxial layer (26) and diffused, and at the same time, the base region (27) is diffused to a depth equal to or deeper than the upper diffusion layer (28).

Specifically, the upper diffusion layer (25) and the collector buried layer (23)
) are approximately 5 μm, 4, and 5 μm from the surface of the substrate (21), respectively.
The base region (27) is diffused by about 3 μm from the surface of the epitaxial layer (26). Therefore, the base region (27) completely reaches the collector buried layer (23). The buried layer (22) is also approximately 2μ from the surface of the substrate (21).
m Crawling up and spreading.

Next, as shown in Figure 1 (*), an epitaxial layer (26
) The upper diffusion layer (28) and the collector lead-out region (29) of the upper and lower isolation regions (24) are simultaneously selectively diffused from the surface, and the upper and lower isolation regions (24) are formed at a position shallower than half the thickness of the epitaxial layer (26). Connect them and separate them.

In addition, the collector lead-out region (29) is a collector buried layer (23).
) and completely surrounds the base area (27).

This step is a characteristic step of the present invention, since the upper diffusion layer (28) is formed after the upper diffusion layer (25) and the base region (27) have been sufficiently deeply diffused in the previous step. , the upper diffusion layer (28) can be made as shallow as approximately 3 μm, and the upper diffusion layer (28) can be made as shallow as approximately 3 μm.
The diffusion time of 28) can be shortened to about 1200°C and 1 hour. Therefore, the lateral diffusion of the upper diffusion layer (28) can be suppressed to about 3 μm, and the surface area occupied by the upper diffusion layer (28) can be significantly reduced. Specifically, the size of the diffusion window is 4μ.
m, the upper diffusion layer (25) is formed to have a width of approximately 14 μm, whereas the width of the upper diffusion layer Jm (28) is approximately 10 μm. In addition, the collector lead-out region (29) is also the upper diffusion layer (28).
), it can be formed shallowly, and the surface area occupied can be significantly reduced.

Next, as shown in FIG. 1(f), a P-type emitter region (30) with a diffusion depth of approximately 1.5 μm is formed on the surface of the base region (27), and then an N+ type emitter region (30) with a diffusion depth of approximately 1.0 μm is formed on the surface of the base region (27). A base contact region (31) is formed. Furthermore, the emitter area (3
0) is formed by a normal NPN transistor base diffusion process, and the base contact region (31) is formed by a normal NPN transistor base diffusion process.
) Formed in transistor emitter diffusion process.

In the vertical PNP transistor formed in this way, the upper and lower isolation regions (24) are connected at a position shallower than half the thickness of the epitaxial layer (26), and the upper diffusion layer (25) is wider than the upper diffusion layer (28). is formed. In addition, the collector buried layer (23) is also largely raised and the collector lead-out region (
29) is formed shallowly. The base region (27) has been diffused sufficiently deep to reach the collector buried layer (23) and the collector lead-out region (29).
) is completely surrounded by

Therefore, according to this embodiment, the base region (27), which is one of the element forming regions, can be sufficiently deeply diffused, while the upper diffusion layer (28) and the collector lead-out region (29) can be made shallow, and the lateral regions thereof can be made shallow. Directional diffusion can be suppressed and the surface area occupied can be significantly reduced. Moreover, although the upper diffusion layer (25) of the upper and lower separation regions (24) is formed wide, the upper diffusion layer (25)
and the collector derivation area (29), or upper wide dispersion! (25) and the collector buried layer (23) have their peripheral edges curved due to lateral diffusion, and a certain distance is maintained in the deep part of the epitaxial layer (26). The layer (25) does not significantly prevent an increase in the degree of integration on the surface of the epitaxial Jl (26), and can narrow the distance between the upper diffusion layer (28) and the collector lead-out region (29). Therefore, the pattern size of the vertical PNP transistor can be significantly reduced.

In addition, the collector buried layer (23) rises greatly like the upper diffused JW (25), and the base region (27) is diffused deeply enough to reach this layer, so that the active base is entirely formed by ion implantation. Low concentration base region (27)
Formed only by. Therefore, the f-a can be further improved compared to the conventional one in which part of the epitaxial layer (26) is formed, and the variation in the epitaxial layer (26) can be improved. It is possible to suppress the variation in Since the collector buried layer (23) rises significantly, the collector resistance decreases and a low Vct (Sat) can be obtained.

In the above-described embodiment, the impurity concentration in the base region (27) is relatively high so that it completely reaches the collector buried layer (23), but the impurity concentration is lowered so that the impurity concentration is lower than that in the emitter region (30). Even with a structure shallower than deep collector embedding/1l (23>), the effect of the present invention aimed at miniaturization can be fully achieved.

Next, a method for manufacturing a semiconductor integrated circuit device incorporating an IIL, which is a second embodiment of the present invention, is shown in FIGS.
l! This will be explained using J (to).

First, as shown in FIG. 2, a P-type silicon substrate is used as the semiconductor substrate (21), and antimony (Sb) is selectively deposited on the substrate (21) to form an N1-type buried Jl.
(22) and a substrate (21) surrounding the buried layer (22)
Boron (B) is deposited on the surface to create upper and lower separation areas (
24) Form an upper diffusion layer (25).

Next, as shown in FIG. 2(b), an N-type epitaxial layer (26) is formed on the entire surface of the substrate (21) by a well-known vapor phase growth method.
is formed to have a thickness of 7 μm. At this time, the buried layer (22) and the diffusion layer (25) are slightly diffused in the vertical direction.

Next, as shown in FIG. 2(c), an epitaxial layer (26
) Boron (B) ions are selectively implanted into the surface to form a base region (27), which is one of the element forming regions.

This ion implantation has a dose of 10Is to 10I4cITl.
-2 and an acceleration voltage of 80 to 100 KeV.

Next, as shown in FIG. 2(d), approximately 1
The upper and lower separated regions (2
4) The diffusion layer (25) and the buried layer (22) are crawled into the epitaxial layer (26) and diffused, and the base region (27) is driven in at the same time. Specifically, the diffusion layer (25) is approximately 5 μm from the surface of the substrate (21), and the buried layer (
22) is raised by about 2 μm and diffused, and the base region (27
) diffuses approximately 3 μm from the surface of the epitaxial layer (26).

Next, as shown in FIG. 2(N), an epitaxial layer (26
) The upper diffusion layer (28) of the upper and lower isolation regions (24) is selectively diffused from the surface, and the upper and lower isolation regions (24) are connected at a position shallower than half the thickness of the epitaxial layer (26) to junction-isolate them.

This step is a characteristic step of the present invention, in which the upper diffusion layer (28) is formed after the diffusion layer (25) and the base region (27) have been sufficiently deeply diffused in the previous step.
The upper diffusion layer (28) can be made as shallow as approximately 3 μm, and the upper diffusion layer (28) can be made as shallow as approximately 3 μm.
8) The diffusion time can be shortened to 1 hour at about 1200°C. Therefore, the lateral diffusion of the upper diffusion layer (28) can be suppressed to about 3 μm, and the surface area occupied by the upper diffusion layer (28) can be significantly reduced. Specifically, the size of the diffusion window is 4μ.
m, the width of the military diffusion layer (25) is approximately 14 μm, while the width of the upper diffusion layer (28) is approximately 110 μm.
become.

Next, as shown in FIG. 2(f), the P-type injector region (32) and base contact region (33) are simultaneously diffused to a diffusion depth of approximately 2 μm, and then to a diffusion depth of approximately 1.5 μm.
An N-type collector region (34) of m is formed. Note that the injector area (32) and base contact area (33)
) is formed by the base diffusion process of the NPN transistor, and the collector region (34) is formed by the emitter diffusion process of the NPN transistor.

In the IIL formed in this way, the upper and lower isolation regions (24) are connected at a position shallower than half the thickness of the epitaxial layer (26), and the military diffusion layer (25) is formed wider than the upper diffusion layer (28). . The base region (27) is also diffused deeper than the base contact region (33).

Therefore, according to this embodiment, while the base region (27), which is one of the element formation regions, can be diffused sufficiently deeply, the upper diffusion layer (28) of the vertical separation region (24) can be made shallow, and the lateral diffusion can significantly reduce the surface area. Moreover, although the upper wide dispersion Ji (25) of the upper and lower separation regions (24) is formed wide, the military dispersion layer (25) and the base region (27)
is that their peripheral edges are curved due to lateral diffusion,
Since a certain distance is maintained in the deep part of the epitaxial layer (26), the military diffusion layer (25) cannot significantly prevent the degree of integration from increasing on the surface of the epitaxial layer (26), and the upper diffusion layer (28) Base area (27) or spread over!
(28) and the base contact region (33) can be narrowed. Therefore, the IIL pattern size can be significantly reduced.

In addition, while forming the upper diffusion layer (28) shallowly, the base region (27) can be formed sufficiently low concentration and sufficiently deep, so that a high inverse β can be obtained, and the inverse Variations in β can be suppressed.

(G) As described in detail, according to the present invention, the Kamihiro San J!
(25) is increased by more than half the thickness of the epitaxial layer (26) and then diffused before forming the upper diffusion layer (28), suppressing lateral diffusion of the upper diffusion layer (28) and reducing its surface area. This has the advantage that the pattern size can be reduced significantly. Furthermore, while the upper diffusion layer (28) is made shallower, the base region (27), which is one of the element formation regions,
It has the advantage that it can be formed at a sufficiently low concentration and sufficiently deep, thereby producing vertical PNP transistors, IILs, etc. with good characteristics.

And since the diffusion time of the upper diffusion layer (28) is short,
It has the advantage that crystal defects on the surface of the epitaxial layer (26) due to thermal diffusion are suppressed, and the upper diffusion layer (28)
) Since the diffusion layer (25) is formed to be wider, it has the advantage that complete junction separation can be obtained even if there is some mask misalignment.

[Brief explanation of drawings]

1(A) to 1(F) are process sectional views for explaining the first embodiment of the present invention, and FIGS. 2(A) to 2(F) are process sectional views for explaining the first embodiment of the present invention. 3(a) to 3(e) are process cross-sectional views for explaining the embodiment of the conventional vertical PN.
FIG. 4 (*) is a process cross-sectional view for explaining a method for manufacturing a P transistor. (21) is a process cross-sectional view for explaining a conventional method for manufacturing an IIL. , (22) is the embedded layer, (23
) is the collector buried layer, (25) is the upper and lower separation region (24
), (28) is the upper diffusion layer of the upper and lower separation region (24), (27) (27) is the base region which is one of the element forming regions. Applicant Sanyo Electric Co., Ltd. and one other agent Patent attorney Takuji Nishino and one other person Figure 1 ) Figure 2 (See Figure 2 (B) Figure 2 (C) Figure 2 (22) Figure 4 (Sun Figure 4 (B) Figure 4 (C) Figure 4 (2) Figure 4 (E)

Claims (1)

[Claims] (1) Impurities of opposite conductivity type are deposited on the surface of a semiconductor substrate of one conductivity type to form a buried layer of opposite conductivity type, and a diffusion layer below the upper and lower separation regions of one conductivity type is formed surrounding the buried layer. a step of depositing an impurity of one conductivity type on the surface of the substrate; a step of laminating an epitaxial layer of an opposite conductivity type over the entire surface of the substrate; an impurity of one conductivity type or an opposite conductivity type forming an element formation region on the surface of the epitaxial layer. a step of heat-treating the substrate to raise the lower diffusion layer by half or more of the thickness of the epitaxial layer and diffusing it, and simultaneously driving in the element forming region; 1. A method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming an upper diffusion layer forming an isolation region, and causing the upper diffusion layer to reach the lower diffusion layer.