JPS62219556A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS62219556A JPS62219556A JP61062452A JP6245286A JPS62219556A JP S62219556 A JPS62219556 A JP S62219556A JP 61062452 A JP61062452 A JP 61062452A JP 6245286 A JP6245286 A JP 6245286A JP S62219556 A JPS62219556 A JP S62219556A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- region
- epitaxial layer
- diffused layers
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000009792 diffusion process Methods 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000926 separation method Methods 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims 2
- 230000010354 integration Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 238000002955 isolation Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- -1 Boron ions Chemical class 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
- H01L27/0244—I2L structures integrated in combination with analog structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はＩ Ｉ Ｌ （Ｉｎｔｅｇｒａｔｅｄ Ｉｎｊ
ｅｃｔｉｏｎ Ｌｏｇｉｃ）と通常のバイポーラＮＰＮ
トランジ誠夕とを組み込んだ半導体集積回路の製造方法
の改良に関する。[Detailed description of the invention] (a) Industrial application field The present invention is directed to I
(ection Logic) and normal bipolar NPN
The present invention relates to an improvement in a method for manufacturing a semiconductor integrated circuit incorporating a transistor.
（ロ）従来の技術
従来の半導体集積回路の製造方法を第２図（イ）乃至第
２図（＊）を用いて説明する。(B) Prior Art A conventional method for manufacturing a semiconductor integrated circuit will be explained with reference to FIGS. 2(a) to 2(*).
先ず第２図（イ）に示す如く、半導体基板（１）として
Ｐ型のシリコン基板を用い、基板（１）上に選択的にア
ンチモン（Ｓｂ）をデポジットして複数個の埋込Ｍ（２
）を形成し、埋込層（２）を囲む基板（１）表面にはポ
ロン（Ｂ）をデポジットして上下分離領域（３〉の上拡
散層（４）を形成する。First, as shown in FIG. 2(A), a P-type silicon substrate is used as the semiconductor substrate (1), antimony (Sb) is selectively deposited on the substrate (1), and a plurality of embedded M(2) are formed.
), and poron (B) is deposited on the surface of the substrate (1) surrounding the buried layer (2) to form an upper diffusion layer (4) of the upper and lower separation regions (3).
次に第２図（ロ）に示す如く、基板（１）全面に周知の
気相成長法によりＮ型のエピタキシャル層（５）を所定
厚きに積層する。この時埋込層（２）および上拡散層（
４）は」二下方向に若干拡散きれる。Next, as shown in FIG. 2(B), an N-type epitaxial layer (5) is laminated to a predetermined thickness over the entire surface of the substrate (1) by a well-known vapor phase growth method. At this time, the buried layer (2) and the upper diffusion layer (
4) can be slightly diffused in the downward direction.
次に第２図（ハ）に示す如く、エピタキシャル層（１）
表面に選択的にポロンをイオン注入し、ＩＩＬのベース
領域（６〉を付着する。このイオン注入はドーズ量１０
′３〜ＩＱ”ｃｎ＋−”、加速電圧８０〜１００ＫｅＶ
で行う。Next, as shown in FIG. 2(c), an epitaxial layer (1) is formed.
The base region (6) of the IIL is deposited by selectively implanting poron into the surface. This ion implantation is performed at a dose of 10
'3~IQ"cn+-", acceleration voltage 80~100KeV
Do it with
次に第２図（ニ）に示す如く、エピタキシャル層（５）
表面から上下分離領域（３）の上拡散層（７〉を約１２
００°Ｃ１３〜４時間で選択拡散し、同時に埋込層（２
）と上拡散層（７）及びＩＩＬのベース領域（６）をド
ライブインする。本工程で上拡散層（７）は上拡散層（
４）と連結し、エピタキシャル層（５）を接合分離して
第１、第２の島領域（８）（９）を形成する。ＩＩＬの
ベース領域（６）は濃度差により上拡散層より浅く形成
きれる。具体的にはエピタキシャル層（５）の厚みが１
３μｍであれば、上拡散層（７）は約９μｍ、上拡散層
（４）は約７μｍの深さに形成され、ベース領域り６〉
は約４μｍの深さに形成される。Next, as shown in FIG. 2(d), an epitaxial layer (5) is formed.
The upper diffusion layer (7) of the upper and lower separation regions (3) from the surface is approximately 12
Selective diffusion was carried out at 00°C for 13 to 4 hours, and at the same time the buried layer (2
), the upper diffusion layer (7) and the base region (6) of the IIL are driven in. In this step, the upper diffusion layer (7) is changed to the upper diffusion layer (
4), and the epitaxial layer (5) is junction-separated to form first and second island regions (8) and (9). The base region (6) of the IIL can be formed shallower than the upper diffusion layer due to the concentration difference. Specifically, the thickness of the epitaxial layer (5) is 1
If the depth is 3 μm, the upper diffusion layer (7) is formed to a depth of approximately 9 μm, the upper diffusion layer (4) is formed to a depth of approximately 7 μm, and the base region 6>
is formed to a depth of approximately 4 μm.
次に第２図（＊〉に示す如く、エピタキシへ・ル層（５
）表面よりポロン（Ｂ）を選択的に拡散し、第１の島領
域（８）にはＮＰＮ トランジスタのベース領域（１０
）を、第２の島領域（９）にはＩＩＬのインジェクタ領
域（１１）とベースコンタクト領域（１２）を夫々形成
し、続いてリン（Ｐ）を選択拡散して第１の島領域（８
）にはＮＰＮ トランジスタのエミッタ領域（１３）と
コレクタコンタクト領域（１４）を、第２の島領域（９
）にはコレクタ領域（１５）を夫々形成する。Next, as shown in Figure 2 (*>), an epitaxial layer (5
) is selectively diffused from the surface of the NPN transistor base region (10) to the first island region (8).
), an IIL injector region (11) and a base contact region (12) are respectively formed in the second island region (9), and then phosphorus (P) is selectively diffused to form the first island region (8).
), the emitter region (13) and collector contact region (14) of the NPN transistor are placed in the second island region (9).
) are respectively formed with collector regions (15).
この様に形成した装置では、ＮＰＮ ｌ−ランジスタの
耐圧をある程度に保ちつつ、ＩＩＬでは活性ベースを低
濃度で深く形成したベース領域（６）で形成するので高
い逆βが得られ、高速性を保てる。In the device formed in this way, while maintaining the breakdown voltage of the NPN l-transistor to a certain level, in IIL, the active base is formed in the base region (6) formed deeply with low concentration, so a high inverse β is obtained, and high speed is achieved. I can keep it.
尚斯る構造は、例えば特願昭６０−２０６９７１号に記
載されている。Such a structure is described, for example, in Japanese Patent Application No. 60-206971.
（ハ）発明が解決しようとする問題点
しかしながら、従来の製造方法では上下分離領域（３）
の上拡散層（７）を形成すると同時にＩＩＬのベース領
域（６）をドライブインしている。そのためＮＰＮ Ｉ
−ランジスタ、ＩＩＬ共に更に高速化を求めてエピタキ
シヤルＭ（５）を薄くしても、ＩＩＬの逆βを所定の値
にするため、上拡散層（７）の拡散工程には低濃度のベ
ース領域（６）を十分に深くするだけの処理時間が要求
される。しかも上拡散Ｍ（７）と上拡散層（４）とでは
、上拡散層（７）の方が供給される不純物が多い状態、
即ちポロン（Ｂ）を多量に含む拡散源膜を付着したまま
の状態で拡散するため、どうしても上拡散層（７）の方
が上拡散層（４）より深く形成きれてしまう。(c) Problems to be solved by the invention However, in the conventional manufacturing method, the upper and lower separated regions (3)
At the same time as forming the upper diffusion layer (7) of the IIL, the base region (6) of the IIL is driven in. Therefore, NPN I
- Even if the epitaxial M (5) is made thinner in order to further increase the speed of both the transistor and the IIL, in order to maintain the inverse β of the IIL to a predetermined value, a low concentration base is used in the diffusion process of the upper diffusion layer (7). Processing time is required to make region (6) sufficiently deep. Furthermore, between the upper diffusion layer M(7) and the upper diffusion layer (4), the upper diffusion layer (7) is supplied with more impurities than the upper diffusion layer (7).
That is, since the diffusion source film containing a large amount of poron (B) is diffused while remaining attached, the upper diffusion layer (7) is inevitably formed deeper than the upper diffusion layer (4).
従ってエピタキシャル層（５）を薄くしても上拡散層（
７）はかなり深く形成しなければならず、横方向拡散が
大で集積度を向上できない欠点があった。Therefore, even if the epitaxial layer (5) is made thinner, the upper diffusion layer (
7) had the disadvantage that it had to be formed quite deep and the lateral diffusion was large, making it impossible to improve the degree of integration.
＝４−
（ニ）問題点を解決するための手段
本発明は斯上した欠点に鑑みてなされ、上下分離領域（
３〉の上拡散層（７）をエピタキシャル層（５）の厚み
の半分以上はい上げて拡散し、同時にＩＩＬのベース領
域（６）を十分に深くドライブインした後、上下分離領
域（３）の上拡散層（４）を形成することにより、集積
度を大幅に向上した、バイボー □うＮＰＮトラ
ンジスタとＩＩＬとを共存させた半導体集積回路の製造
方法を提供するものである。=4- (d) Means for solving the problems The present invention has been made in view of the above-mentioned drawbacks, and includes a top and bottom separation area (
3> Raise and diffuse the upper diffusion layer (7) by more than half the thickness of the epitaxial layer (5), and at the same time drive in the base region (6) of the IIL sufficiently deeply, and then By forming an upper diffusion layer (4), the present invention provides a method for manufacturing a semiconductor integrated circuit in which a biborder NPN transistor and an IIL coexist, and the degree of integration is greatly improved.
（ホ）作用
本発明によれば、あらかじめ上拡散層（４）とベース領
域（６）とを十分に深く拡散した後、上拡散層（７）を
形成するので、上拡散層（７）はベース領域（６）とは
無関係に浅くでき、その横方向拡散を抑制できる。よっ
てＩＩＬの特性を劣化許せずに集積度を大幅に向上でき
る。(E) Function According to the present invention, the upper diffusion layer (7) is formed after the upper diffusion layer (4) and the base region (6) are sufficiently deeply diffused in advance. It can be made shallow independently of the base region (6), and its lateral diffusion can be suppressed. Therefore, the degree of integration can be greatly improved without allowing the IIL characteristics to deteriorate.
（へ）実施例
以下、本発明の一実施例を第１図（イ）乃至第１図（へ
）を用いて説明する。(F) Example An embodiment of the present invention will be described below with reference to FIG. 1(A) to FIG. 1(F).
先ず第１図（イ）に示す如く、半導体基板（１）として
Ｐ型のシリコン基板を用い、基板（１）上に選択的にア
ンチモン（Ｓｂ）をデポジットして複数個の埋込層（２
）を形成し、埋込層（２）を囲む基板（１）表面にはボ
ロン（Ｂ）をデポジットして上下分離領域（３）の上拡
散層（４）を形成する。First, as shown in FIG. 1(A), a P-type silicon substrate is used as a semiconductor substrate (1), antimony (Sb) is selectively deposited on the substrate (1), and a plurality of buried layers (2) are formed.
) is formed, and boron (B) is deposited on the surface of the substrate (1) surrounding the buried layer (2) to form an upper diffusion layer (4) of the upper and lower separation regions (3).
次に第１図（ロ）に示す如く、基板（１）全面に周知の
気相成長法によりＮ型のエピタキシャル層（５）を約７
μｍ厚に積層する。この時埋込層（２）および上拡散層
（４）は上下方向に若干拡散される。Next, as shown in FIG. 1(b), an N-type epitaxial layer (5) is deposited on the entire surface of the substrate (1) by a well-known vapor phase epitaxy method for about 70 cm.
Laminated to a thickness of μm. At this time, the buried layer (2) and the upper diffusion layer (4) are slightly diffused in the vertical direction.
次に第１図（ハ）に示す如く、エピタキシャル層（５）
表面に選択的にボロンをイオン注入し、工■Ｌのベース
領域（６）を付着する。このイオン注入はドーズ量１０
’″〜ｌ Ｑ ”ｃｍ−’、加速電圧８０〜１００Ｋｅ
Ｖで行う。Next, as shown in FIG. 1(c), an epitaxial layer (5) is formed.
Boron ions are selectively implanted into the surface to attach the base region (6) of the process L. This ion implantation has a dose of 10
'''~l Q "cm-', acceleration voltage 80~100Ke
Do it with V.
次に第１図（ニ）に示す如く、基板（１）全体に約１２
００℃、２時間の熱処理を加えることにより上下分離領
域（３）の上拡散層（４）をエピタキシャル層（５）の
厚みの半分以上はい上げて拡散し、同時にＩＩＬのベー
ス領域（６）をドライブインする。具体的には、上拡散
層（４）は基板（１）表面より約５μｍはい上げ、ベー
ス領域（６）は約３μｍドライブインする。Next, as shown in Figure 1 (d), about 12
By applying heat treatment at 00°C for 2 hours, the upper diffusion layer (4) of the upper and lower separation regions (3) is increased and diffused by more than half the thickness of the epitaxial layer (5), and at the same time, the base region (6) of the IIL is expanded. Drive in. Specifically, the upper diffusion layer (4) is elevated by about 5 μm from the surface of the substrate (1), and the base region (6) is driven in by about 3 μm.
次に第１図（ホ）に示す如く、エピタキシャル層（５）
表面より上下分離領域（３）の上拡散層（７）を選択拡
散し、上拡散層（４〉と連結して第１、第２の島領域（
８）（９）を形成する。Next, as shown in FIG. 1 (e), an epitaxial layer (5) is formed.
The upper diffusion layer (7) of the upper and lower separation regions (3) is selectively diffused from the surface, and connected to the upper diffusion layer (4>) to form the first and second island regions (
8) Form (9).
本工程は本発明の特徴とする工程で、あらかじめ上拡散
層（４〉をエピタキシャル層（５〉の厚みの半分以上は
い上げて拡散し、同時にＩＩＬのベース領域（６）をド
ライブインした後に上拡散層（７）を形成しているので
、上拡散層（７）はベース領域（６）に制限されずに約
３μｍと浅くでき、拡散時間を約１時間と短くできる。This step is a characteristic step of the present invention, in which the upper diffusion layer (4) is raised and diffused in advance by more than half the thickness of the epitaxial layer (5), and at the same time the base region (6) of the IIL is driven in, and then the upper diffusion layer (4) is raised and diffused. Since the diffusion layer (7) is formed, the upper diffusion layer (7) can be made shallow to about 3 μm without being limited by the base region (6), and the diffusion time can be shortened to about 1 hour.
このため上拡散層（７）の横方向拡散を約３μｍに抑え
ることができ、それらの表面占有面積を大幅に縮小でき
る。具体的には、拡散窓の幅が４μｍであれば上拡散層
（７）の幅は約１０μｍに形成される。尚上拡散層（４
）は上拡散層（７）より深く拡散した分だけ幅広になり
、幅は約１４μｍに形成される。Therefore, the lateral diffusion of the upper diffusion layer (7) can be suppressed to about 3 μm, and the surface area occupied by the upper diffusion layer (7) can be significantly reduced. Specifically, if the width of the diffusion window is 4 μm, the width of the upper diffusion layer (7) is approximately 10 μm. Furthermore, the diffusion layer (4
) becomes wider as it is diffused deeper than the upper diffusion layer (7), and has a width of approximately 14 μm.
次に第１図≦へ）に示す如く、エピタキシャル層（５）
表面よりボロン（Ｂ）を選択的に拡散し、第１δ島領域
（８）にはＮＰＮ）ランジスタのベース領域（１０）を
、第２の島領域（９）にはＩＩＬのインジェクタ領域（
１１）とベースコンタクト領域（１２）を約２μｍの深
さに夫々形成し、続いてリン（Ｐ）を選択拡散して第１
の島領域（８）にはＮＰＮ）ランジスタのエミッタ領域
（１３）とコレクタフンタクト領域（１４）を、第２の
島領域（９）にはコレクタ領域（１５）を夫々的１．５
μｍの深さに形成する。Next, as shown in Figure 1≦), an epitaxial layer (5) is formed.
Boron (B) is selectively diffused from the surface, and the first δ island region (8) is provided with the base region (10) of the NPN) transistor, and the second island region (9) is provided with the IIL injector region (
11) and base contact region (12) to a depth of approximately 2 μm, and then phosphorus (P) is selectively diffused to form the first
The island region (8) has an emitter region (13) and a collector contact region (14) of the NPN transistor, and the second island region (9) has a collector region (15) of 1.5
Formed to a depth of μm.
この様にして形成した半導体集積回路では、上拡散層（
７）を浅くできるので、その横方向拡散を抑え、表面占
有面積を大幅に縮小できる。この時下拡散層（４）を上
拡散層（７）より幅広に形成するものの、上拡散層（４
）の周端部は横方向拡散によって湾曲し、基板（１）表
面から上方向に向って徐々に幅狭になるので基板（１）
表面で約１４μｍの幅があっても上拡散層（４）最上部
では拡散窓の線幅である約４μｍになる。従って幅広に
形成した上拡散層（４）はエピタキシャル層（５）表面
における集積度の向上を防げず、上下分離領域（３）の
表面占省面積は上拡散層（７）のみで決定できるので集
積度を大幅に向上できる。In the semiconductor integrated circuit formed in this way, the upper diffusion layer (
7) can be made shallow, suppressing its lateral diffusion and greatly reducing the surface area occupied. At this time, although the lower diffusion layer (4) is formed wider than the upper diffusion layer (7), the upper diffusion layer (4) is formed wider than the upper diffusion layer (7).
) is curved due to lateral diffusion and gradually becomes narrower upward from the surface of the substrate (1).
Even if the width is about 14 μm at the surface, the line width at the top of the upper diffusion layer (4) becomes about 4 μm, which is the line width of the diffusion window. Therefore, the upper diffusion layer (4) formed wide cannot prevent an increase in the degree of integration on the surface of the epitaxial layer (5), and the surface area occupied by the upper and lower separation regions (3) can be determined only by the upper diffusion layer (7). The degree of integration can be greatly improved.
さらに第２の島領域（９）に形成したＩＩＬでは、イオ
ン注入により形成する低濃度のベース領域（６）を上拡
散層（４）と同時にドライブインするので十分に深く形
成できる。従って、ベース幅が広くても十分に低濃度で
あることと、エピタキシャル層（５）を薄くできるので
ベース領域（６〉底部から埋込層（２）までの距離が短
いことから、ｆＴが高く更に高速のＩＩＬが得られる。Further, in the IIL formed in the second island region (9), the low concentration base region (6) formed by ion implantation is driven in at the same time as the upper diffusion layer (4), so that it can be formed sufficiently deep. Therefore, even if the base width is wide, the concentration is sufficiently low, and since the epitaxial layer (5) can be made thin, the distance from the bottom of the base region (6) to the buried layer (2) is short, resulting in a high fT. Even faster IIL can be obtained.
そうして第１の島領域（８）には、ＩＩＬのベースコン
タクト領域（１２）と同時に形成したベース領域（１０
）と、ＩＩＬのコレクタ領域（１５）と同時に形成した
エミッタ領域（１３）及びコレクタコンタクト領域（１
４）とで構成するバイポーラＮＰＮ）ランジスタが、Ｉ
ＩＬと一体化共存されている。The first island region (8) has a base region (10) formed at the same time as the base contact region (12) of the IIL.
), an emitter region (13) and a collector contact region (1) formed at the same time as the collector region (15) of IIL.
4) A bipolar NPN) transistor consisting of I
It is integrated and coexists with IL.
（ト）発明の詳細
な説明した如く本発明によれば、あらかじめ上拡散層（
４）をエピタキシャル層（５）の厚みの半分以上はい上
げて拡散した後、上拡散層（７）を形成するので、上拡
散層（７）を浅くでき、その横方向拡散を抑えて集積度
を大幅に向上できるという利点を有する。(g) As described in detail, according to the present invention, the upper diffusion layer (
4) is increased by more than half the thickness of the epitaxial layer (5) and then diffused, and then the upper diffusion layer (7) is formed, so the upper diffusion layer (7) can be made shallow, suppressing its lateral diffusion and increasing the integration density. It has the advantage of being able to significantly improve
さらに本発明によれば、ベース領域（６）は下拡散層（
４）と同時にドライブインするのでエピタキシャル層（
５）を薄くしても十分に深く且つ低濃度に設定でき、更
に高速化したＩＩＬとバイポーラＮＰＮ ｌ−ランジス
タとを一体化共存できるという利点をも有する
また本発明によれば、上拡散！（７）の拡散時間が短い
ので熱拡散によるエピタキシヤルＭ （５）表面の結晶
欠陥が少く、さらに下拡散層（４）を上拡散層（７〉よ
り幅広に形成するので、多少のマスクずれがあっても完
全な接合分離が得られるという利点をも有する。Furthermore, according to the invention, the base region (6) is formed by the lower diffusion layer (
4) Since it is driven in at the same time as the epitaxial layer (
5) can be set sufficiently deep and at a low concentration even if it is thinned, and has the advantage that a faster IIL and a bipolar NPN l-transistor can coexist in an integrated manner.Furthermore, according to the present invention, upper diffusion! (7) Epitaxial M due to thermal diffusion is short because the diffusion time is short. (5) There are few crystal defects on the surface, and since the lower diffusion layer (4) is formed wider than the upper diffusion layer (7>), some mask misalignment may occur. It also has the advantage that complete junction separation can be obtained even if there is
第１図（イ）乃至（へ）は本発明による製造方法を説明
するための断面図、第２図（イ）乃至第２図（ホ）は従
来の製造方法を説明するための断面図である。
（１）は半導体基板、 （２）は埋込層、 （４）は
上下分離領域（３）の下拡散層、 （５）はエピタキシ
ャル層、 （６〉はＩＩＬのベース領域、 （７）は上
下分離領域（３）の上拡散層である。
出願人 三洋電機株式会社外１名
代理人 弁理士 西野卓嗣 外１名
＠ 銖
＠ 派
堤 法
味 壕 ゛
区
へ
七や
鵠５Figures 1 (A) to (F) are cross-sectional views for explaining the manufacturing method according to the present invention, and Figures 2 (A) to (E) are cross-sectional views for explaining the conventional manufacturing method. be. (1) is the semiconductor substrate, (2) is the buried layer, (4) is the lower diffusion layer of the upper and lower isolation region (3), (5) is the epitaxial layer, (6> is the base region of IIL, (7) is This is the upper diffusion layer of the upper and lower separation regions (3). Applicant Sanyo Electric Co., Ltd. and one other agent Patent attorney Takuji Nishino and one other person
Claims (1)
する逆導電型の不純物を付着し、該埋込層を囲んで上下
分離領域の下拡散層を形成する一導電型の不純物を付着
する工程、前記基板全面に逆導電型のエピタキシャル層
を積層する工程、 前記エピタキシャル層表面にＩＩＬのベース領域を形成
する一導電型の不純物を付着する工程、前記基板全体を
加熱処理して前記下拡散層を前記エピタキシャル層の厚
みの半分以上はい上らせて拡散し、同時に前記ベース領
域をドライブインする工程、 前記エピタキシャル層表面より前記上下分離領域の上拡
散層を形成し、前記下拡散層に到達させて第１、第２の
島領域を形成する工程、 前記エピタキシャル層表面より一導電型の不純物を選択
拡散し、前記第１の島領域にはベース領域を、前記ＩＩ
Ｌのベース領域が作り込まれた第２の島領域にはインジ
ェクタ領域及びベースコンタクト領域を形成する工程、 前記エピタキシャル層表面より逆導電型の不純物を選択
拡散し、前記第１の島領域にはエミッタ領域を、前記第
２の島領域にはコレクタ領域を形成する工程とを具備す
ることを特徴とする半導体集積回路の製造方法。(1) Impurities of opposite conductivity type that form multiple buried layers are attached to the surface of a semiconductor substrate of one conductivity type, and impurities of one conductivity type that surround the buried layers to form a lower diffusion layer in the upper and lower separation regions. a step of depositing an epitaxial layer of the opposite conductivity type on the entire surface of the substrate; a step of depositing an impurity of one conductivity type to form a base region of the IIL on the surface of the epitaxial layer; and a step of heat-treating the entire substrate. a step of increasing the lower diffusion layer by more than half the thickness of the epitaxial layer and driving in the base region at the same time; forming an upper diffusion layer of the upper and lower separation regions from the surface of the epitaxial layer; forming first and second island regions by reaching the diffusion layer; selectively diffusing impurities of one conductivity type from the surface of the epitaxial layer;
forming an injector region and a base contact region in the second island region in which the base region of L is formed; selectively diffusing impurities of the opposite conductivity type from the surface of the epitaxial layer; A method of manufacturing a semiconductor integrated circuit, comprising the step of forming an emitter region and a collector region in the second island region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61062452A JPS62219556A (en) | 1986-03-19 | 1986-03-19 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61062452A JPS62219556A (en) | 1986-03-19 | 1986-03-19 | Manufacture of semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62219556A true JPS62219556A (en) | 1987-09-26 |
| JPH0577299B2 JPH0577299B2 (en) | 1993-10-26 |
Family
ID=13200610
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61062452A Granted JPS62219556A (en) | 1986-03-19 | 1986-03-19 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62219556A (en) |
-
1986
- 1986-03-19 JP JP61062452A patent/JPS62219556A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0577299B2 (en) | 1993-10-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |