JPH0618202B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a semiconductor integrated circuit incorporating a vertical PNP transistor.

(B) Conventional Technique A conventional method for manufacturing a semiconductor integrated circuit will be described in detail with reference to FIGS. 3A to 3D.

First, as shown in FIG. 3A, a P-type silicon substrate is used as a semiconductor substrate (41), and antimony is selectively deposited on the surface of the substrate (41) to form an N ⁺ -type buried layer (43). , The lower diffusion layer (44 ') of the upper and lower isolation regions (44) by depositing boron on the surface of the substrate (41) surrounding the buried layer (43).
Is formed.

Next, as shown in FIG. 3B, an N type epitaxial layer (42) is grown on the substrate (41). Boron is deposited on the surface of the epitaxial layer (42) at a position corresponding to the lower diffusion layer (44 ') to form an upper diffusion layer (44 ") of the upper and lower isolation regions (44).

Next, as shown in FIG. 3C, the substrate (41) is heated to fill the upper diffusion layer (44 ″) and the lower diffusion layer (44 ′) of the upper and lower isolation regions (44) with the buried layer (43) and the epitaxial layer (43). The upper diffusion layer (44 ″) and the lower diffusion layer (44 ′) are connected to form an upper and lower separation region (44) by being lifted up and diffused in 42). This diffusion process is performed at about 1100 ° C. for 3 to 4 hours, and when the thickness of the epitaxial layer (42) is 13 μ, the upper diffusion layer (44 ″) is diffused to a depth of about 10 μ and the lower diffusion layer (44 ′) is about It has been raised to a depth of 5μ.

Further, as shown in FIG. 3D, P is formed on the surface of the island region (45) formed by the epitaxial layer (42) surrounded by the upper and lower isolation regions (44).
The base region (46) of the type and the emitter region (47) of the N type are diffused, and the collector contact region (48) is formed by the emitter diffusion on the surface of the island region (45).

By the above process, the NPN transistor can be formed in the island region (45). In addition, as a method of separating the upper and lower parts
No. 4015, Japanese Patent Publication No. 49-45629, and the like.

Next, as shown in FIG. 4, a conventional vertical PNP transistor has an N type epitaxial layer (52) grown on a P type silicon semiconductor substrate (51) and an N ⁺ type epitaxial layer provided on the substrate (51). And the P ⁺ -type upper and lower isolation regions (54) penetrating the epitaxial layer (52) so as to completely surround the buried layer (53), and the buried layer (53) of the substrate (51). and 53) P ⁺ type collector region provided on top (55), an epitaxial layer (52) and the collector lead region of the P ⁺ -type reaching the collector region (55) from the surface (56), the collector region (55) And collector derivation area (56)
And a P region formed on the surface of the base region (57) and a base region (57) which is completely surrounded by and is formed by the epitaxial layer (52).
^{A +} type emitter region (58), an oxide film (59) covering the surface of the epitaxial layer (52), and a collector lead-out region (56), a base contact region (60) and an oxide film (59) through an electrode hole of the oxide film (59). It is composed of a collector electrode (61), a base electrode (62) and an emitter electrode (63) which are in ohmic contact with the emitter region (58). Such a vertical PNP transistor is disclosed in, for example, Japanese Patent Laid-Open No. 172738/1984.

In the above vertical PNP transistor, the active base region
Since (57) is formed by the epitaxial layer (52), 10 ¹⁶
Since the impurity concentration is as low as cm ^-3 or less and the base width is wide, there is a drawback that the gain bandwidth product (f _T ) is low. Further, variations in the specific resistance or thickness of the epitaxial layer (52) directly result in variations in the impurity concentration or base width of the active base region (57), which causes a defect that it appears as variations in h _FE of the vertical PNP transistor. .

FIG. 5 shows a vertical PNP transistor in which such a drawback is improved. This vertical PNP transistor includes a P-type silicon semiconductor substrate (71), an N-type epitaxial layer (72) stacked on the substrate (71), and an N ⁺ -type buried layer provided on the substrate (71). The layer (73) and the P ⁺ -type upper and lower isolation regions (7) which penetrate the epitaxial layer (72) so as to completely surround the buried layer (73).
And 4) a buried layer (73) of P ⁺ -type which is provided on the collector region (75), an epitaxial layer (72) reaching from the surface to the collector region (75) P ⁺ type collector taking-out region (76) A base region (77) completely surrounded by the collector region (75) and the collector lead-out region (76) and formed by the epitaxial layer (72)
A P ⁺ -type emitter region (78) provided on the surface of the base region (77), an N ⁺ -type base contact region (80) formed on the surface of the base region (77), and an epitaxial layer (72) surface An oxide film (79) for covering the collector lead-out region (76) and the collector electrode (81) in ohmic contact with the base contact region (80) and the emitter region (78) through the electrode hole of the oxide film (79). It comprises a base electrode (82) and an emitter electrode (83), and is composed of an N-type ion implantation region (84) provided on the surface of the base region (77) and having a higher impurity concentration than the base region (77).

According to the above structure, as is clear from the impurity concentration distribution characteristics shown in FIG. 6, an N type ion implantation region (84) is formed on the surface side of the epitaxial layer (72) of the conventional base region. The ion implantation region (84) is set to a high impurity concentration about 10 times higher than the impurity concentration of the epitaxial layer (72), and the base region (77) is formed by the ion implantation region (84) and the epitaxial (72). Has been done. Therefore, the base region (7
The impurity distribution of (7) varies from the emitter region (78) to the collector region (7
As the impurity concentration decreases toward 5), a drift electric field is generated inside and the holes are accelerated. As a result, vertical P
NP transistor has a conventional f _T of 50 MHz to 100 MH
Can be improved to z.

Also even if variations in thickness and resistivity of the epitaxial layer (72), since the h _FE of the vertical PNP transistor is determined substantially by the depth of the ion implantation region (84), variation in h _FE is greatly by ion implantation Can be reduced to Specifically, it is about half or less of the conventional variation.

(C) Problems to be Solved by the Invention However, in the conventional method of manufacturing a semiconductor integrated circuit of the upper and lower separation method described above, the diffusion time can be shortened compared to the upper separation method, but the upper diffusion layer (44 ″) And the lower diffusion layer (44 ′) are diffused at the same time, it is necessary to diffuse the upper diffusion layer (44 ″) considerably deeper than the lower diffusion layer (44 ′) because of the impurity concentration. Therefore, the diffusion time is 3-4
It takes a long time, the lateral diffusion of the upper diffusion layer (44 ″) becomes large, the area occupied by the upper diffusion layer (44 ″) on the surface of the epitaxial layer (42) is large, and the integration degree cannot be improved so much.

Also, in the above-described improved conventional vertical PNP transistor, the width of the base region (77) forming the base region (77) in the epitaxial layer (72) is large and f _T cannot be further improved. In addition, h _FE easily fluctuates due to variations in the thickness of the epitaxial layer (72), and the collector region (7
Since the impurity concentration of 5) is as low as 10 ¹⁷ cm ⁻³ , the collector-emitter saturation voltage V _CE (sat) becomes large, and there is a drawback that it is difficult to manufacture.

(D) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and the upper and lower isolation regions are formed by diffusing the lower diffusion layer of the upper and lower isolation regions and the deep element diffusion region from the surface of the epitaxial layer into the epitaxial layer. The present invention provides a method for manufacturing a semiconductor integrated circuit in which the conventional drawbacks are greatly improved by diffusing the upper diffusion layer of the region.

Further, the present invention has been made in view of the drawbacks of the conventional vertical PNP transistor, and is a vertical P that double-diffuses the base region and the emitter region on the collector region surface which is formed by ion implantation from the epitaxial layer surface and reaches the collector buried layer.
A method for manufacturing a semiconductor integrated circuit incorporating an NP transistor is provided.

(E) Action According to the present invention, since the lower diffusion layer of the upper and lower isolation regions and the element diffusion region are diffused sufficiently deep into the epitaxial layer, the upper diffusion layer of the upper and lower isolation regions is diffused. The layer can be formed sufficiently shallow and the element diffusion region can be formed sufficiently deep. As a result, the area occupied by the diffusion layer can be reduced and the degree of integration can be improved.

Further, according to the present invention, since the manufacturing method in which the base region and the emitter region are double-diffused on the surface of the collector region is adopted, the base width can be formed narrow and the variation can be reduced.

(F) Embodiment A first embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention will be described in detail with reference to FIGS. 1A to 1F.

First, as shown in FIG. 1A, a P-type silicon substrate is used as a semiconductor substrate (1), and antimony is selectively deposited on the surface of the substrate (1) to form an N ⁺ -type buried layer (3). The substrate on and surrounding the buried layer (3)
(1) Boron is deposited on the surface to form a collector buried layer (5) and a lower diffusion layer (4 ') of the upper and lower isolation regions (4).

Next, as shown in FIG. 1B, an N type epitaxial layer (2) is grown to a thickness of about 7 μm on the substrate (1). At this time, the buried layer (3), the collector buried layer (5) and the upper and lower isolation regions
(4) The lower diffusion layer (4 ') is slightly diffused in the vertical direction. Specifically, the lower diffusion layer (4') and the collector buried layer (5) of the upper and lower isolation regions (4) are about 1.5 μm. Yes go up. In this step, the collector buried layer on the surface of the epitaxial layer (2)
(5) Boron is selectively ion-implanted into a region corresponding to the upper portion, and a collector region (6) which is one of element diffusion regions is attached. This ion implantation uses a boron dose of 10 ¹³ -1.
The acceleration voltage is 80 to 200 KeV at 0 ¹⁵ cm ^-2 .

Next, as shown in FIG. 1C, the entire substrate (1) is heated to about 1200 ° C.
The upper diffusion region (4), the lower diffusion layer (4 '), the buried layer (3) and the collector buried layer (5) are heated in the epitaxial layer (2) and diffused, and at the same time, the collector region is heated.
Diffuse (6) deeply into the epitaxial layer (2). Specifically, the lower diffusion layer (4 ') and the collector buried layer (5) of the upper and lower isolation regions (4) are about 5 μm from the lower surface of the epitaxial layer (2).
The collector region (6) is driven in to a depth of about 4 μm from the surface of the epitaxial layer (2).
Therefore, the collector region (6) reaches the collector buried layer (5) completely.

Next, as shown in FIG. 1D, phosphorus is ion-implanted into the surface of the collector region (6) to form a base region (7). This ion implantation is performed with phosphorus at a dose amount of 10 ¹⁵ to 10 ¹⁷ cm ^-2 and an acceleration voltage of 60 to 100 KeV, and the base region (7) is attached to the surface of the collector region (6).

Next, as shown in FIG. 1E, the upper diffusion layer (4 ″) and the collector lead-out region from the surface of the epitaxial layer (2) are separated from the upper and lower isolation regions (4).
(8) is simultaneously diffused to connect the upper and lower isolation regions (4) to separate the epitaxial layer (2) by PN. The collector lead-out region (8) reaches the collector buried layer (5), and the collector lead-out region (8) surrounds the entire circumference of the collector region (6). Further, by driving in the base region (7) formed in the previous step by this diffusion, the base region (7) having a depth of about 2.5 μm is driven.
Is formed.

This process is a feature of the present invention, and the upper and lower separation regions (4)
After fully lifting the upper diffusion layer (4 '), the upper diffusion layer (4 ")
The depth of the upper diffusion layer (4 ″) is about 3 μm.
And the diffusion time of the upper diffusion layer (4 ″) is about 1200 ℃
Can be shortened to 1 hour. For this reason, the lateral diffusion of the upper diffusion layer (4 ″) can be greatly reduced, and the surface diffusion area of the upper diffusion layer (4 ″) can be greatly reduced by being set within about 3 μm from the peripheral edge of the diffusion hole. .

Furthermore, as shown in FIG. 1F, an emitter region (9) and a collector contact region (10) are diffused on the surface of the base region (7) and the surface of the collector lead-out region (8). This spread is N
This is performed in the base diffusion process of the PN transistor. After that, a base contact region (11) is formed on the surface of the base region (7) by an emitter diffusion process of an NPN transistor. The emitter region (9) is formed to a depth of about 2 μm, and the base contact region (11) is formed to a depth of about 1.5 μm.

Next, a second embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention will be described in detail with reference to FIGS. 2A to 2F.

First, as shown in FIG. 2A, a P type silicon substrate is used as a semiconductor substrate (21), and an N ⁺ type buried layer (23) is formed on the substrate (21) by selectively depositing antimony, Substrate above and surrounding the buried layer (23)
(21) A collector burying layer (25) and a lower diffusion layer (24 ') of the upper and lower isolation regions (24) are also formed on the surface by using boron as a deposition.

Next, as shown in FIG. 2B, an epitaxial layer 22 is grown on the substrate 21 to a thickness of about 7 μm. Then substrate (21)
By heat-treating the buried layer (23) and collector buried layer (2
5) and the lower diffusion layer (24 ') of the upper and lower isolation regions (24) are vertically diffused to form a buried layer (23) and a collector buried layer (25) having a predetermined width. Specifically, upper and lower separation area
The lower diffusion layer (24 ') of (24) is an epitaxial layer of about 5 μm.
(22) Rise above the bottom surface.

Subsequently, as shown in FIG. 2C, a collector region 26 is formed by ion implantation, which is a feature of the present invention. This ion implantation uses boron at a dose of 10 ¹³ to 10 ¹⁵ cm ^-2 and an acceleration voltage of 8
Performing at 0 to 200 KeV, implanting impurities into the surface of the epitaxial layer (22) on the collector burying layer (25), and then driving in to a depth of about 4 μm, the collector burying layer (2
Reach 5). It is convenient to carry out this drive-in simultaneously with the diffusion of the lower diffusion layer (24 ') of the upper and lower separation regions (24).

Further, phosphorus is ion-implanted on the surface of the collector region (26) to form a base region (28). This ion implantation is performed with phosphorus at a dose amount of 10 ¹⁵ to 10 ¹⁷ cm ^-2 and an acceleration voltage of 60 to 100 KeV, and is driven in to a depth of about 2.5 μm to form a base region.
(8) is formed. It is convenient to drive-in the base region (28) at the same time as diffusing the upper diffusion layer (24 ″) of the upper and lower separation regions (24).

Further, as shown in FIG. 2D, the upper diffusion layer (24 ″) and the collector lead-out region (27) are simultaneously diffused from the surface of the epitaxial layer (22) to connect the upper and lower isolation regions (24). Then, the epitaxial layer (22) is PN-separated, and the collector lead-out region (27) reaches the collector buried layer (25), and the collector lead-out region (27) surrounds the entire circumference of the collector region (26). The upper diffusion layer (24 ″) is diffused to a depth of about 3 μm by diffusion at 1200 ° C. for 1 hour.

Furthermore, as shown in FIG. 2E, an emitter region (30) and a collector contact region (31) are diffused on the surface of the base region (28) and the surface of the collector lead-out region (27). This diffusion is performed in the base diffusion process of the NPN transistor. After that, a base contact region (29) is formed on the surface of the base region (28) by an emitter diffusion process of an NPN transistor. Specifically, the base region (28) is about 2.5 μm, the emitter region
(30) is about 2 μm, base contact area (29) is about 1.5 μm
It is formed to a depth of μm.

Further, as shown in FIG. 2F, the collector electrode 33, the base electrode 34 and the emitter electrode 35 are formed of vapor-deposited aluminum by a well-known vapor deposition technique.

The vertical PNP transistor according to the above-described manufacturing method of the present invention comprises a P-type silicon semiconductor substrate (21), an N-type epitaxial layer (22) laminated on the substrate (21), and a substrate (21). The N ⁺ -type buried layer (23) provided above and this buried layer (2
3) P ⁺ type upper and lower isolation regions (24) penetrating the epitaxial layer (22) so as to completely surround the epitaxial layer (22), the P ⁺ type buried layer (25) provided on the buried layer (23), and the epitaxial layer (22) A P-type collector region (26) formed by ion implantation which reaches the collector buried layer (25) from the surface, and P ⁺ which reaches the collector buried layer (25) from the surface of the epitaxial layer (22).
-Type collector lead-out region (27), N-type base region (28) formed by ion implantation on the surface of collector region (26), and N ⁺ -type base contact region formed on the surface of base region (28) (29), a P-type emitter region (30) formed on the surface of the base region (28), and a P ⁺ -type collector contact region (31) formed on the surface of the collector lead-out region (27). ,
An oxide film (32) covering the surface of the epitaxial layer (22) and a collector contact region (31), a base contact region (29) and an emitter region (30) are respectively provided through contact holes provided in the oxide film (32). Ohmic contact collector electrode (3
3) It is composed of a base electrode (34) and an emitter electrode (35).

Such a vertical PNP transistor is characterized in that the epitaxial layer (22) is used as a collector region (26) formed entirely by ion implantation, and the collector region (26) has a base region.
Double diffusion of (28) and emitter region (30) realizes a diffused base region and a base width with little variation.

(G) According to the present invention, according to the present invention, the lower diffusion layer (4 ') of the upper and lower isolation regions (4) and the collector region (6) are sufficiently deeply diffused before the upper and lower isolation regions (4). Since the diffusion layer (4 ″) is diffused, the upper diffusion layer (4 ′) of the upper and lower separation regions (4) can be formed shallowly, and the upper diffusion layer (4 ″) of the upper and lower separation regions (4) can be laterally oriented. About 3 μm
The epitaxial layer (2) of the upper diffusion layer (4 ″), which is suppressed below
The area occupied by the surface can be greatly reduced, and the degree of integration can be greatly improved.

Further, according to the present invention, since the upper diffusion layer (4 ″) of the upper and lower isolation regions (4) is much shallower than the lower diffusion layer (4 ′), the upper diffusion layer (4 ″) of the upper and lower isolation regions (4) is The diffusion time is about 1 compared to the conventional 3-4 hours.
It can be greatly reduced in time. This results in an epitaxial layer
(2) The heat stress and damage to the surface can be greatly reduced,
It is possible to prevent a decrease in h _FE when the transistor has a very small current, and to significantly reduce noise.

Further, according to the present invention, the base region (28) is changed from the conventional uniform base structure by the epitaxial layer to the diffusion base structure, and the drift electric field can be generated. Also, since the base width can be controlled by the double diffusion structure of the base region (28) and the emitter region (30), the base width can be made much narrower than the conventional one, and the manufacturing variations can be greatly reduced. . As a result, the vertical PNP transistor of the present invention has an f _T of about 200.
It has the advantage that it can be greatly improved up to MHZ.

Further in accordance with the invention, the base region (28) and the emitter region (30)
Since it can be formed by double diffusion, the variation in the base width can be greatly reduced as compared with the conventional one in which the base width is formed by the epitaxial layer, and the variation in the production of h _FE can be greatly reduced.

Furthermore, according to the present invention, the collector burying layer (25) can be sufficiently lifted and diffused, so that the collector region (26) can reach the collector burying layer (25) sufficiently, and
(26) is a collector embedding layer (25) and collector lead-out region (27)
Since it is surrounded by, the saturation voltage V _CE (sat) can be greatly reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1F are sectional views for explaining a first embodiment of a method for manufacturing a semiconductor integrated circuit according to the present invention, and FIGS. 2A to 2F show the present invention. Sectional view for explaining the second embodiment of the
3A to 3D are cross-sectional views for explaining a conventional method for manufacturing a semiconductor integrated circuit, and FIGS. 4 and 5 are conventional vertical PNs.
FIG. 6 is a sectional view for explaining the P-transistor, and FIG. 6 is a characteristic diagram for explaining the impurity profile of the conventional vertical PNP transistor shown in FIG. (1) is a semiconductor substrate, (2) is an epitaxial layer, (3) is a buried layer, (4) is an upper and lower isolation region, (4 ′) is a lower diffusion layer, and (4 ″).
Is an upper diffusion layer, (5) is a collector buried layer, (6) is a collector region, (7) is a base region, (9) is an emitter region, (21) is a semiconductor substrate, (22) is an epitaxial layer, (23) ) Is a buried layer, (24) is a vertical separation region, (24 ′) is a lower diffusion layer, (24 ″) is an upper diffusion layer, (25) is a collector buried layer, (26) is a collector region, and (28) is The base region, (30) is the emitter region.

Claims (1)

[Claims] 1. A buried layer of opposite conductivity type is formed on a surface of a semiconductor substrate of one conductivity type, a collector buried layer of one conductivity is formed so as to overlap with the buried layer, and the buried surface is surrounded to the substrate surface. A step of depositing a lower diffusion layer of one conductivity type on the upper and lower isolation regions, a step of laminating an epitaxial layer of the opposite conductivity type on the surface of the substrate, and selectively ion-implanting impurities forming a collector region on the surface of the epitaxial layer Step, heat treatment is applied to the entire substrate to diffuse the lower diffusion layer of the upper and lower isolation regions so as to rise to more than half of the thickness of the epitaxial layer, and at the same time, the collector buried layer and the buried layer into the epitaxial layer. Yes, it is allowed to rise and diffuse, and this heat treatment expands and diffuses the ion-implanted impurities into the epitaxial layer. Forming a deep collector region reaching the collector buried layer than the diffusion layer on the lower isolation region,
Forming a base region of a transistor by ion-implanting an impurity of opposite conductivity type into the surface of the collector region; diffusing an upper diffusion layer of one conductivity type in an upper and lower isolation region shallower than half the thickness of the epitaxial layer from the surface of the epitaxial layer And then reaching the lower diffusion layer, and diffusing an impurity of one conductivity type into the surface of the base region to form an emitter region of a transistor.