JPH0638476B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0638476B2 JPH0638476B2 JP59232870A JP23287084A JPH0638476B2 JP H0638476 B2 JPH0638476 B2 JP H0638476B2 JP 59232870 A JP59232870 A JP 59232870A JP 23287084 A JP23287084 A JP 23287084A JP H0638476 B2 JPH0638476 B2 JP H0638476B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- epitaxial layer
- pnp transistor
- region
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 22
- 239000012535 impurity Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 35
- 229910052710 silicon Inorganic materials 0.000 description 35
- 239000010703 silicon Substances 0.000 description 35
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0826—Combination of vertical complementary transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8224—Bipolar technology comprising a combination of vertical and lateral transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0821—Combination of lateral and vertical transistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明はｎｐｎトランジスタとｐｎｐトランジスタとを
それぞれ具備する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an npn transistor and a pnp transistor, respectively.
従来の技術 従来、この種の半導体装置として、バイポーラＩＣが知
られている。このバイポーラＩＣを構成する素子として
は、通常ｎｐｎトランジスタが主として用いられ、回路
構成上混用すると有利な場合にはｎｐｎトランジスタが
併用されている。このｐｎｐトランジスタには、動作方
向が基板表面と平行な横形ｐｎｐトランジスタ（または
ラテラルｐｎｐトランジスタ）と、動作方向が基板表面
と垂直な縦形トランジスタ（またはサブｐｎｐトランジ
スタ）とがある。2. Description of the Related Art Conventionally, a bipolar IC has been known as a semiconductor device of this type. An npn transistor is usually mainly used as an element forming the bipolar IC, and an npn transistor is also used when it is advantageous to mix the two in terms of circuit configuration. The pnp transistor includes a horizontal pnp transistor (or lateral pnp transistor) whose operation direction is parallel to the substrate surface, and a vertical transistor (or sub pnp transistor) whose operation direction is vertical to the substrate surface.
これらのｎｐｎトランジスタ、横形ｐｎｐトランジスタ
及び縦形ｐｎｐトランジスタを同時に用いたバイポーラ
ＩＣは、従来例えば第５Ａ図〜第５Ｃ図に示すような方
法により製造されている。すなわち、まず第５Ａ図に示
すように、ｐ型シリコン基板１にn+型の埋込層２，３を
形成し、次いでこのｐ型シリコン基板１上にｎ型のシリ
コンエピタキシヤル層４を形成した後、このシリコンエ
ピタキシヤル層４中にｐ型シリコン基板１にまで達する
p+型の分散拡散領域５を形成する。次に第５Ｂ図に示す
ように、上記シリコンエピタキシヤル層４にｎｐｎトラ
ンジスタ用のｐ型のベース領域７と、縦形ｐｎｐトラン
ジスタ用のｐ型のエミツタ領域８及びコレクタ取出し領
域９と、横形ｐｎｐトランジスタ用のｐ型のエミツタ領
域１０及びコレクタ領域１１とをそれぞれ形成する。次
に第５Ｃ図に示すように、シリコンエピタキシヤル層４
にｎｐｎトランジスタ用のn+型のエミッタ領域１２及び
コレクタ取出し領域１３と、縦形ｐｎｐトランジスタ用
のn+型のベース取出し領域１４と、横形ｐｎｐトランジ
スタ用のベース取出し領域１５とをそれぞれ形成する。
この後、上記各領域７〜１５に電極（図示せず）を形成
して、バイポーラＩＣを完成させる。A bipolar IC using the npn transistor, the lateral pnp transistor and the vertical pnp transistor at the same time has been conventionally manufactured by a method shown in FIGS. 5A to 5C, for example. That is, as shown in FIG. 5A, first, n + type buried layers 2 and 3 are formed on a p type silicon substrate 1, and then an n type silicon epitaxial layer 4 is formed on the p type silicon substrate 1. And then reach the p-type silicon substrate 1 in the silicon epitaxial layer 4.
A p + type dispersion diffusion region 5 is formed. Next, as shown in FIG. 5B, in the silicon epitaxial layer 4, a p-type base region 7 for an npn transistor, a p-type emitter region 8 and a collector extraction region 9 for a vertical pnp transistor, and a lateral pnp transistor are formed. A p-type emitter region 10 and a collector region 11 are formed respectively. Next, as shown in FIG. 5C, a silicon epitaxial layer 4 is formed.
To the n + -type emitter region 12 and collector take-out region 13 for the npn transistor, the n + -type base extraction region 14 for vertical pnp transistor are formed respectively a base take-out region 15 for lateral pnp transistor.
After that, electrodes (not shown) are formed in the regions 7 to 15 to complete the bipolar IC.
このようにして製造される第５Ｃ図に示すバイポーラＩ
Ｃにおいては、エミツタ領域１２と、ベース領域７と、
このベース領域７と埋込層３との間のシリコンエピタキ
シヤル層４から成るコレクタ領域１６とでｎｐｎトラン
ジスタ１７が構成されている。またエミツタ領域８と、
このエミツタ領域８の下方のシリコンエピタキシヤル層
４から成るベース領域１８と、上記エミツタ領域８の下
方のｐ型シリコン基板１から成るコレクタ領域１９とで
縦形ｐｎｐトランジスタ２０が構成されている。さらに
エミツタ領域１０と、コレクタ領域１１と、これらのエ
ミツタ領域１０及びコレクタ領域１１間のシリコンエピ
タキシヤル層４から成るベース領域２１とで横形ｐｎｐ
トランジスタ２２が構成されている。なお縦形ｐｎｐト
ランジスタ２０の下方に埋込層を設けていないのは、直
流電流増幅率hFEを得るためである。The bipolar I shown in FIG. 5C manufactured in this way
In C, the emitter region 12, the base region 7,
The base region 7 and the collector region 16 formed of the silicon epitaxial layer 4 between the buried layer 3 form an npn transistor 17. In addition, the emission area 8
A vertical pnp transistor 20 is composed of a base region 18 made of the silicon epitaxial layer 4 below the emitter region 8 and a collector region 19 made of the p-type silicon substrate 1 below the emitter region 8. Further, the emitter region 10, the collector region 11, and the base region 21 formed of the silicon epitaxial layer 4 between the emitter region 10 and the collector region 11 form a lateral pnp.
The transistor 22 is configured. The buried layer is not provided below the vertical pnp transistor 20 in order to obtain the direct current amplification factor h FE .
上述の第５Ｃ図に示すバイポーラＩＣは次のような欠点
を有している。すなわち、低電圧、高速バイポーラＩＣ
を得るためには、シリコンエピタキシヤル層４の厚さを
１〜２μｍ程度に薄くする必要があるが、このようにシ
リコンエピタキシヤル層４を薄くすると横形ｐｎｐトラ
ンジスタ２２のhFEが低下してしまうので、これを防止
するためにはベース幅Ｗを小さく設計する必要がある。
しかしながら、Ｗを例えば２μｍ程度に小さくすると、
コレクタ・エミツタ間でパンチスルーが起きてしまうと
いう欠点がある。同様に縦形ｐｎｐトランジスタ２０
も、シリコンエピタキシヤル層４が薄くなると縦方向に
パンチスルーが起きてしまうという欠点がある。The bipolar IC shown in FIG. 5C has the following drawbacks. That is, low voltage, high speed bipolar IC
In order to obtain the above, it is necessary to reduce the thickness of the silicon epitaxial layer 4 to about 1 to 2 μm. However, when the silicon epitaxial layer 4 is reduced in this way, h FE of the lateral pnp transistor 22 decreases. Therefore, in order to prevent this, it is necessary to design the base width W small.
However, if W is reduced to about 2 μm, for example,
There is a drawback that punch through occurs between the collector and the emitter. Similarly, a vertical pnp transistor 20
However, there is a drawback that punch-through occurs in the vertical direction when the silicon epitaxial layer 4 becomes thin.
発明が解決しようとする問題点 本発明は、上述の問題にかんがみ、従来のパイポーラＩ
Ｃ等の半導体装置が有する上述のような欠点を是正した
半導体装置を提供することを目的とする。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In view of the above-mentioned problems, the present invention is based on the conventional PIpolar
An object of the present invention is to provide a semiconductor device in which the above-mentioned drawbacks of a semiconductor device such as C are corrected.
問題点を解決するための手段 本発明に係る半導体装置は、ｎｐｎトランジスタ（例え
ばｎｐｎトランジスタ１７）とｐｎｐトランジスタ（例
えば横型ｐｎｐトランジスタ２２及び縦型ｐｎｐトラン
ジスタ２０）とをそれぞれ具備する半導体装置（例えば
バイポーラＩＣ）において、半導体基板（例えばｐ型シ
リコン基板１）上にｎ型エピタキシャル層（例えばシリ
コンエピタキシャル層４）を設けると共に、上記ｎ型エ
ピタキシャル層中に上記ｎｐｎトランジスタを設け、更
に、上記ｎ型エピタキシャル層よりも高いｎ型不純物濃
度を有するｎ型半導体領域（例えばｎ型領域２６、２
７）を上記ｎ型エピタキシャル層中に直接設けると共
に、上記ｎ型半導体領域中に上記ｐｎｐトランジタを設
けている。Means for Solving the Problems A semiconductor device according to the present invention includes a semiconductor device (for example, a bipolar device) including an npn transistor (for example, an npn transistor 17) and a pnp transistor (for example, a lateral pnp transistor 22 and a vertical pnp transistor 20). In an IC), an n-type epitaxial layer (eg, silicon epitaxial layer 4) is provided on a semiconductor substrate (eg, p-type silicon substrate 1), the npn transistor is provided in the n-type epitaxial layer, and the n-type epitaxial layer is further provided. N-type semiconductor region having a higher n-type impurity concentration than the layer (for example, n-type regions 26, 2)
7) is directly provided in the n-type epitaxial layer, and the pnp transistor is provided in the n-type semiconductor region.
また、上記ｎｐｎトランジスタは横形ｐｎｐトランジス
タであることが好ましい。The npn transistor is preferably a lateral pnp transistor.
また、上記ｎ型不純物濃度は、１×１０16ｃｍ-3以上〜
１×１０17ｃｍ-3以下の範囲であることが好ましい。The n-type impurity concentration is 1 × 10 16 cm −3 or more.
It is preferably in the range of 1 × 10 17 cm −3 or less.
実施例 以下本発明に係る半導体装置をバイポーラＩＣに適用し
た一実施例につち図面に基づいて説明する。なお以下の
第１Ａ図〜第１Ｄ図においては、第５Ａ図〜第５Ｃ図と
同一部分には同一の符号を付し、必要に応じてその説明
を省略する。Embodiment An embodiment in which the semiconductor device according to the present invention is applied to a bipolar IC will be described below with reference to the drawings. In FIGS. 1A to 1D below, the same parts as those in FIGS. 5A to 5C are designated by the same reference numerals, and the description thereof will be omitted as necessary.
まず本実施例によるバイポーラＩＣの製造方法につき説
明する。First, a method of manufacturing the bipolar IC according to this embodiment will be described.
第１Ａ図に示すように、まずｐ型シリコン基板１にヒ素
(As)、アンチモン(Sb)等のｎ型の不純物を高濃度に拡散
させてn+型の埋込層２，３を形成した後、ｐ型シリコン
基板１上に例えば厚さが２μｍで比抵抗ρが１Ωcmのｎ
型のシリコンエピタキシヤル層４を形成する。次にこの
シリコンエピタキシヤル層４の表面にSiO2膜２４を形成
した後、このSiO2膜２４を介してこのシリコンエピタキ
シヤル層４中にAs等のｎ型不純物を設定条件で選択的に
イオン注入する（シリコンエピタキシヤル層４中の注入
不純物をＯで表す）。As shown in FIG. 1A, arsenic is first formed on the p-type silicon substrate 1.
After n-type impurities such as (As) and antimony (Sb) are diffused at a high concentration to form n + -type buried layers 2 and 3, a p-type silicon substrate 1 having a thickness of, for example, 2 μm is used. N with resistance ρ of 1Ωcm
A silicon epitaxial layer 4 of the mold is formed. Next, an SiO 2 film 24 is formed on the surface of the silicon epitaxial layer 4, and then an n-type impurity such as As is selectively ionized in the silicon epitaxial layer 4 through the SiO 2 film 24 under a set condition. Implant (impurity impurity in silicon epitaxial layer 4 is represented by O).
次に、第１Ｂ図に示すように、SiO2間２４の所定部分を
エツチング除去して開口２４ａ〜２４ｄを形成した後、
これらの開口２４ａ〜２４ｄを通じでｐ型不純物、例え
ばホウ素(B)をシリコンエピタキシヤル層４中に拡散さ
せて、ｐ型シリコン基板１にまで達するp+型の分離拡散
領域５を形成する。この分離拡散領域５を形成するため
の熱処理の際には、シリコンエピタキシヤル層４中の上
記注入不純物が深さ方向に拡散されると共に電気的に活
性化される。その結果、シリコンエピタキシヤル層４中
にこのシリコンエピタキシヤル層４の不純物濃度よりも
高く、また後述のｎｐｎトランジスタ１７のベース領域
７の不純物濃度よりも低い不純物濃度、例えば５×１０
16cm-3程度のｎ型領域２６〜２８を形成する。この後、
SiO2膜２４をエツチング除去する。Next, as shown in FIG. 1B, a predetermined portion of the SiO 2 space 24 is etched and removed to form openings 24a to 24d,
A p-type impurity such as boron (B) is diffused into the silicon epitaxial layer 4 through the openings 24a to 24d to form a p + -type isolation diffusion region 5 reaching the p-type silicon substrate 1. During the heat treatment for forming the isolation diffusion region 5, the implanted impurities in the silicon epitaxial layer 4 are diffused in the depth direction and electrically activated. As a result, the impurity concentration in the silicon epitaxial layer 4 is higher than the impurity concentration of the silicon epitaxial layer 4 and lower than the impurity concentration of the base region 7 of the npn transistor 17 described later, for example, 5 × 10 5.
The n-type regions 26 to 28 of about 16 cm −3 are formed. After this,
The SiO 2 film 24 is removed by etching.
次に第１Ｃ図に示すように、上記ｎ型領域２６中にそれ
ぞれｐ型のコレクタ領域１１及びエミツタ領域１０を、
上記ｎ型領域２７中にｐ型のエミツタ領域８を、また上
記シリコンエピタキシヤル層４中にｐ型ベース領域７を
形成する。この後、上記ベース領域７にp+型のグラフト
・ベース領域２９を、また上記エミツタ領域８，１０に
それぞれp+型領域３０，３１を形成する。Next, as shown in FIG. 1C, a p-type collector region 11 and an emitter region 10 are formed in the n-type region 26, respectively.
A p-type emitter region 8 is formed in the n-type region 27, and a p-type base region 7 is formed in the silicon epitaxial layer 4. After that, a p + type graft base region 29 is formed in the base region 7, and p + type regions 30 and 31 are formed in the emitter regions 8 and 10, respectively.
次に第１Ｄ図に示すように、ｎ型領域２６〜２８にそれ
ぞれn+型のベース取出し領域１５，１４、コレクタ取出
し領域１３をそれぞれ形成すると共に、ベース領域７中
にn+型のエミツタ領域１２を形成した後、各領域９，１
１〜１５，２９〜３１にそれぞれ電極（図示せず）を形
成して、目的とするバイポーラＩＣを完成させる。Next, as shown in FIG. 1D, n + type base take-out regions 15 and 14 and collector take-out regions 13 are formed in the n type regions 26 to 28, respectively, and the n + type emitter regions are formed in the base region 7. After forming 12, each area 9, 1
Electrodes (not shown) are formed on 1 to 15 and 29 to 31, respectively, to complete the intended bipolar IC.
上述のようにして製造された第１Ｄ図に示すパイポーラ
ＩＣにおける横形ｐｎｐトランジスタ２２の動作周波数
fTとコレクタ電流ICとの関係をベース幅Ｗをパラメータ
として第２図に示す。またこの横形ｐｎｐトランジス２
２の直流電流増幅率hFE及びコレクタ・エミツタ間耐圧
ＶCEOとベース幅Ｗとの関係を第３図に示す。Operating frequency of the lateral pnp transistor 22 in the bipolar IC shown in FIG. 1D manufactured as described above.
The relationship between f T and collector current I C is shown in FIG. 2 with the base width W as a parameter. Also this horizontal pnp Transis 2
The relationship between the direct current amplification factor h FE, the collector-emitter breakdown voltage V CEO, and the base width W of No. 2 is shown in FIG.
この第３図から明らかなように、Ｗ＝２μｍにすると、
従来ではＶCEOが５Ｖ以下となつてパンチスルーが起き
てしまうのに対して、本実施例によればhFEをあまり低
下させることなくＶCEOを１０Ｖ程度と従来に比べて高
くすることができる。このため、第２図から明らかなよ
うに、５０〜６０ＭHz程度の地のfTを得ることができ
る。As is clear from FIG. 3, when W = 2 μm,
Conventionally, punch-through occurs when V CEO is 5 V or less, but according to the present embodiment, V CEO can be increased to about 10 V as compared with the prior art without significantly reducing h FE. . Therefore, as is clear from FIG. 2, it is possible to obtain a ground f T of about 50 to 60 MHz.
次に上述の実施例によるバイポーラＩＣにおける縦形ｐ
ｎｐトランジスタ２０のfTとICとの関係を第４図に示
す。この第４図から明らかなように、従来のバイポーラ
ＩＣにおける縦形ｐｎｐトランジスタ２０においてもパ
ンチスルーが起きない厚さ（５μｍ以上）のシリコンエ
ピタキシヤル層４を用いた場合には２０ＭHz程度の地の
fTしか得られないのに対して、本実施例によれば、厚さ
２μｍのシリコンエピタキシヤル層４を用いることによ
り１０ＭHz程度の値のfTを得ることができ、しかもＶ
CEOを１５Ｖ以上とすることができる。Next, the vertical p in the bipolar IC according to the above-described embodiment
The relationship between f T and I C of the np transistor 20 is shown in FIG. As is apparent from FIG. 4, when the vertical epitaxial pnp transistor 20 in the conventional bipolar IC also uses the silicon epitaxial layer 4 having a thickness (5 μm or more) at which punch-through does not occur, it is about 20 MHz.
While only f T can be obtained, according to the present embodiment, by using the silicon epitaxial layer 4 having a thickness of 2 μm, f T of about 10 MHz can be obtained, and V
CEO can be 15V or higher.
このように、上述の実施例によれば、シリコンエピタキ
シヤル層４の厚さを例えば２μｍと極めて薄くした場合
においても、横形ｐｎｐトランジスタ２２及び縦形ｐｎ
ｐトランジスタ２０のＶCEOを十分に高くすることがで
きるので、パンチスルーを起こすことなく従来に比べて
極めて高いfTを得ることができる。このようにパンチス
ルーが起きるのを防止することができるのは、次のよう
な理由による。すなわちシリコンエピタキシヤル層４中
にこのシリコンエピタキシヤル層４よりも不純物濃度の
高いｎ型領域２６，２７を形成し、これらのｎ形領域２
６，２７中にそれぞれ横形ｐｎｐトランジスタ２２及び
縦形ｐｎｐトランジスタ２０を形成しているので、コレ
クタ・ベース間の接合における空乏層のベース側への広
がりを不純物濃度が高い分だけ従来に比べて小さくする
ことができるためである。As described above, according to the above-described embodiment, even when the thickness of the silicon epitaxial layer 4 is extremely thin, for example, 2 μm, the lateral pnp transistor 22 and the vertical pnp transistor 22 are formed.
Since V CEO of the p-transistor 20 can be made sufficiently high, an extremely high f T can be obtained as compared with the conventional one without causing punch through. The reason why punch through can be prevented in this way is as follows. That is, n-type regions 26 and 27 having an impurity concentration higher than that of the silicon epitaxial layer 4 are formed in the silicon epitaxial layer 4, and these n-type regions 2 are formed.
Since the lateral pnp transistor 22 and the vertical pnp transistor 20 are formed in 6 and 27, respectively, the expansion of the depletion layer at the junction between the collector and the base toward the base side is made smaller than that of the conventional one due to the higher impurity concentration. This is because it is possible.
以上本発明を実施例につき説明したが、本発明は上述の
実施例に限定されるものではなく、本発明の技術的思想
に基づく種々の変形が可能である。例えば、上述の実施
例においてはｎ型領域２６〜２８の不純物濃度を５×１
０16cm-3としたが、必要に応じて不純物濃度をこれより
も高くすることも低くすることも可能である。しかし、
パンチスルーを効果的に防止すること等のためには、１
×１０16〜１×１０17cm-3の範囲の不純物濃度とするの
が好ましい。Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention. For example, in the above embodiment, the impurity concentration of the n-type regions 26 to 28 is set to 5 × 1.
Although it is set to 0 16 cm −3 , the impurity concentration can be set higher or lower than this as required. But,
To effectively prevent punch-through, etc., 1
The impurity concentration is preferably in the range of x10 16 to 1x10 17 cm -3 .
発明の効果 本発明に係る半導体装置によれば、半導体基板上に設け
られているｎ型エピタキシヤル層中にｎｐｎトランジス
タを設けると共に、上記ｎ型エピタキシヤル成長層中に
設けられかつこのｎ型エピタキシヤル層よりも不純物濃
度の高いｎ型半導体領域中にｐｎｐトランジスタを設け
ているので、ｎ型エピタキシヤル層を薄くした場合にお
いてもｐｎｐトランジスタのパンチスルーが起きるのを
防止することが可能であり、従つて高速動作の半導体装
置を提供することが可能である。According to the semiconductor device of the present invention, the npn transistor is provided in the n-type epitaxial layer provided on the semiconductor substrate, and the npn transistor is provided in the n-type epitaxial growth layer. Since the pnp transistor is provided in the n-type semiconductor region having an impurity concentration higher than that of the jar layer, punch-through of the pnp transistor can be prevented even when the n-type epitaxial layer is thinned. Therefore, it is possible to provide a high-speed operation semiconductor device.
第１Ａ図〜第１Ｄ図は本発明の一実施例によるバイポー
ラＩＣの製造方法の一例を工程順に示す断面図、第２図
は横形ｐｎｐトランジスタの動作周波数fTとコレクタ電
流ICとの関係をベース幅Ｗをパラメータとして示すグラ
フ、第３図は横形ｐｎｐトランジスタの直流電流増幅率
hFE及びコレクタ・エミツタ間耐圧ＶCEOとベース幅Ｗと
の関係を示すグラフ、第４図は縦形ｐｎｐトランジスタ
の動作周波数fTとコレクタ電流ICとの関係を示すグラ
フ、第５Ａ図〜第５Ｃ図は従来のバイポーラＩＣの製造
方法を工程順に示す断面図である。 なお図面に用いた符号において、 １……ｐ型シリコン基板 ４……シリコンエピタキシヤル層 ５……分散拡散領域 7,8,21……ベース領域 8,10,12……エミツタ領域 11,16,19……コレクタ領域 17……ｎｐｎトランジスタ 20……縦形ｐｎｐトランジスタ 22……横形ｐｎｐトランジスタ 26,27,28……ｎ型領域 である。1A to 1D are sectional views showing an example of a method of manufacturing a bipolar IC according to an embodiment of the present invention in the order of steps, and FIG. 2 shows the relationship between the operating frequency f T of a lateral pnp transistor and the collector current I C. A graph showing the base width W as a parameter, and FIG. 3 shows a direct current amplification factor of a lateral pnp transistor.
A graph showing the relationship between h FE and the collector-emitter breakdown voltage V CEO and the base width W, FIG. 4 is a graph showing the relationship between the operating frequency f T of the vertical pnp transistor and the collector current I C, and FIGS. 5A to 5A. FIG. 5C is a cross-sectional view showing the method of manufacturing the conventional bipolar IC in the order of steps. In the reference numerals used in the drawings, 1 ... p-type silicon substrate 4 ... silicon epitaxial layer 5 ... dispersion diffusion region 7,8,21 ... base region 8,10,12 ... emitter region 11,16, 19 ... Collector region 17 ... npn transistor 20 ... Vertical pnp transistor 22 ... Horizontal pnp transistor 26, 27, 28 ... N-type region.
Claims (3)
とをそれぞれ具備する半導体装置において、 半導体基板上にｎ型エピタキシャル層を設けると共に、 上記ｎ型エピタキシャル層中に上記ｎｐｎトランジスタ
を設け、 更に、上記ｎ型エピタキシャル層よりも高いｎ型不純物
濃度を有するｎ型半導体領域を上記ｎ型エピタキシャル
層中に直接設けると共に、 上記ｎ型半導体領域中に上記ｐｎｐトランジスタを設け
たことを特徴とする半導体装置。1. A semiconductor device comprising an npn transistor and a pnp transistor, respectively, wherein an n-type epitaxial layer is provided on a semiconductor substrate, and the npn transistor is provided in the n-type epitaxial layer. A semiconductor device, wherein an n-type semiconductor region having an n-type impurity concentration higher than that of the layer is directly provided in the n-type epitaxial layer, and the pnp transistor is provided in the n-type semiconductor region.
ンジスタであることを特徴とする特許請求の範囲第１項
に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the pnp transistor is a lateral pnp transistor.
以上〜１×１０17ｃｍ-3以下の範囲であることを特徴と
する特許請求の範囲第１項に記載の半導体装置。3. The n-type impurity concentration is 1 × 10 16 cm −3.
The semiconductor device according to claim 1, wherein the range is from 1 to 10 17 cm −3 or less.
Priority Applications (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59232870A JPH0638476B2 (en) | 1984-11-05 | 1984-11-05 | Semiconductor device |
| KR1019850007581A KR940005447B1 (en) | 1984-11-05 | 1985-10-15 | Semiconductor device |
| CA000493970A CA1254671A (en) | 1984-11-05 | 1985-10-28 | Semiconductor device with npn and pnp transistors |
| GB08526749A GB2167231B (en) | 1984-11-05 | 1985-10-30 | Semiconductor devices |
| CN85108134.7A CN1004845B (en) | 1984-11-05 | 1985-11-02 | Semiconductor device |
| AU49315/85A AU572005B2 (en) | 1984-11-05 | 1985-11-04 | Semiconductor device with npn and pnp transistors |
| NL8503033A NL194711C (en) | 1984-11-05 | 1985-11-05 | Semiconductor device with a lateral pnp transistor and a vertical pnp transistor. |
| FR8516362A FR2572850B1 (en) | 1984-11-05 | 1985-11-05 | DEVICE OF A SEMICONDUCTOR COMPONENT, IN PARTICULAR A BIPOLAR INTEGRATED CIRCUIT, COMPRISING NPN AND PNP, LATERAL AND VERTICAL TRANSISTORS |
| AT0318985A AT395272B (en) | 1984-11-05 | 1985-11-05 | SEMICONDUCTOR DEVICE WITH VERTICAL AND LATERAL NPN AND PNP TRANSISTORS ON A COMMON SUBSTRATE |
| DE3539208A DE3539208C2 (en) | 1984-11-05 | 1985-11-05 | Semiconductor device with a lateral and a vertical pnp transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59232870A JPH0638476B2 (en) | 1984-11-05 | 1984-11-05 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5279026A Division JP2777054B2 (en) | 1993-10-01 | 1993-10-12 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61111575A JPS61111575A (en) | 1986-05-29 |
| JPH0638476B2 true JPH0638476B2 (en) | 1994-05-18 |
Family
ID=16946115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59232870A Expired - Lifetime JPH0638476B2 (en) | 1984-11-05 | 1984-11-05 | Semiconductor device |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JPH0638476B2 (en) |
| KR (1) | KR940005447B1 (en) |
| CN (1) | CN1004845B (en) |
| AT (1) | AT395272B (en) |
| AU (1) | AU572005B2 (en) |
| CA (1) | CA1254671A (en) |
| DE (1) | DE3539208C2 (en) |
| FR (1) | FR2572850B1 (en) |
| GB (1) | GB2167231B (en) |
| NL (1) | NL194711C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6768183B2 (en) * | 2001-04-20 | 2004-07-27 | Denso Corporation | Semiconductor device having bipolar transistors |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1520515A (en) * | 1967-02-07 | 1968-04-12 | Radiotechnique Coprim Rtc | Integrated circuits incorporating transistors of opposite types and methods of making them |
| JPS5710964A (en) * | 1980-06-25 | 1982-01-20 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58212159A (en) * | 1982-06-02 | 1983-12-09 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| DE3361832D1 (en) * | 1982-04-19 | 1986-02-27 | Matsushita Electric Ind Co Ltd | Semiconductor ic and method of making the same |
-
1984
- 1984-11-05 JP JP59232870A patent/JPH0638476B2/en not_active Expired - Lifetime
-
1985
- 1985-10-15 KR KR1019850007581A patent/KR940005447B1/en not_active IP Right Cessation
- 1985-10-28 CA CA000493970A patent/CA1254671A/en not_active Expired
- 1985-10-30 GB GB08526749A patent/GB2167231B/en not_active Expired
- 1985-11-02 CN CN85108134.7A patent/CN1004845B/en not_active Expired
- 1985-11-04 AU AU49315/85A patent/AU572005B2/en not_active Expired
- 1985-11-05 AT AT0318985A patent/AT395272B/en not_active IP Right Cessation
- 1985-11-05 NL NL8503033A patent/NL194711C/en not_active IP Right Cessation
- 1985-11-05 FR FR8516362A patent/FR2572850B1/en not_active Expired
- 1985-11-05 DE DE3539208A patent/DE3539208C2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| AU4931585A (en) | 1986-05-15 |
| NL194711B (en) | 2002-08-01 |
| AU572005B2 (en) | 1988-04-28 |
| FR2572850A1 (en) | 1986-05-09 |
| JPS61111575A (en) | 1986-05-29 |
| DE3539208A1 (en) | 1986-05-15 |
| GB2167231A (en) | 1986-05-21 |
| KR940005447B1 (en) | 1994-06-18 |
| CN85108134A (en) | 1986-07-02 |
| NL194711C (en) | 2002-12-03 |
| KR860004472A (en) | 1986-06-23 |
| GB2167231B (en) | 1988-03-02 |
| FR2572850B1 (en) | 1988-09-09 |
| CA1254671A (en) | 1989-05-23 |
| CN1004845B (en) | 1989-07-19 |
| NL8503033A (en) | 1986-06-02 |
| DE3539208C2 (en) | 1998-04-09 |
| GB8526749D0 (en) | 1985-12-04 |
| ATA318985A (en) | 1992-03-15 |
| AT395272B (en) | 1992-11-10 |
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