GB2167231A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- GB2167231A GB2167231A GB08526749A GB8526749A GB2167231A GB 2167231 A GB2167231 A GB 2167231A GB 08526749 A GB08526749 A GB 08526749A GB 8526749 A GB8526749 A GB 8526749A GB 2167231 A GB2167231 A GB 2167231A
- Authority
- GB
- United Kingdom
- Prior art keywords
- type
- epitaxial layer
- region
- silicon epitaxial
- type epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 32
- 229910052710 silicon Inorganic materials 0.000 claims description 32
- 239000010703 silicon Substances 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000003247 decreasing effect Effects 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0826—Combination of vertical complementary transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8224—Bipolar technology comprising a combination of vertical and lateral transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0821—Combination of lateral and vertical transistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
In a high-speed semiconductor integrated circuit, with npn and pnp transistors, an npn transistor 17 is formed in an n type epitaxial layer 4 formed on a semiconductor substrate 1, and a pnp transistor 20,22 is formed in an n type semiconductor region 26,27 formed in the n type epitaxial layer 4, the n type semiconductor region 26,27 having a higher impurity concentration than that of the n type epitaxial layer 4. <IMAGE>
Description
SPECIFICATION
Semiconductor devices
This invention relates to semiconductor devices.
More usually the transistors in a bipolar integrated circuit (IC) are npn transistors. However, pnp transistors are also used, together with npn transistors, when it is advantageous to use transistors of both conductivity types.
Conventional pnp transistors are classified into lateral pnp transistors having a conduction direction parallel to the surface of the substrate, and vertical pnp transistors having a conduction direction perpendicular to the surface of the substrate.
A known bipolar IC with npn transistors, and lateral and vertical pnp transistors is manufactured by the method shown in Figs. 1A to 1C of the accompanying drawings. As shown in Fig. 1A, n+ type buried layers 2 and 3 are formed in a p type silicon substrate 1. Subsequently, an n type silicon epitaxial layer 4 is formed on the p type silicon substrate 1. A p+ type isolation diffusion region 5 is formed in the silicon epitaxial layer 4 reaching to the p type silicon substrate 1. As shown in Fig.
1 B, a p type base region 7 for an npn transistor, a p type emitter region 8 and a p type collector electrode region 9 for a vertical pnp transistor, and a p type emitter region 10 and a p type collector electrode region 11 for a lateral pnp transistor are formed in the silicon epitaxial layer 4. As shown in Fig. 1C, an n' type emitter region 12 and an n type collector electrode region 13 for the npn transistor, an nt type base electrode region 14 for the vertical pnp transistor, and an n type base electrode region 15 for the lateral pnp transistor are formed in the silicon epitaxial layer 4.
Thereafter, electrodes (not shown) are formed in contact with the regions 7 to 15, thereby completing a bipolar IC.
In the bipolar IC shown in Fig. 1C, the emitter region 12, the base region 7 and a collector region 16 comprising the silicon epitaxial layer 4 between the base region 7 and the buried layer 3 form an npn transistor 17. The emitter region 8, a base region 18 comprising the silicon epitaxial layer 4 under the emitter region 8, and a collector region 19 comprising the p type silicon substrate 1 under the emitter region 8 form a vertical pnp transistor 20.
The emitter region 10, the collector region 11 and a base region 21 comprising the silicon epitaxial layer 4 between the emitter region
10 and the collector region 11 form a lateral pnp transistor 22. It should be noted that a buried layer is not formed under the vertical pnp transistor 20.
The bipolar IC shown in Fig. 1C has the drawback that in order to obtain low-voltage, high-speed operation, the thickness of the silicon epitaxial layer 4 must be as small as 1 to 2,um. When such a thin silicon epitaxial layer is formed, the direct current gain hFE of the lateral pnp transistor 22 is decreased. In order to prevent this, a base width W must be small. When the base width W is as small as about 2,am, however, a punch-through phenomenon occurs between the collector and the emitter. Similarly, when the silicon epitaxial layer 4 becomes thin, punch-through occurs in the perpendicular direction.
According to the present invention there is provided a semiconductor device with npn and pnp transistors, wherein a said npn transistor is formed in an n type epitaxial layer formed on a semiconductor substrate, and a said pnp transistor is formed in an n type semiconductor region formed in said n type epitaxial layer, said n type semiconductor region having a higher impurity concentration than that of said n type epitaxial layer.
In embodiments of the present invention, even if the thickness of the n type epitaxial layer is decreased, punch-through of the pnp transistor can be prevented, thereby obtaining a high-speed semiconductor device.
The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which:
Figures 1A to 1C are sectional views sequentially showing a manufacturing method of a known bipolar IC;
Figures 2A to 2D are sectional views sequentially showing a manufacturing method of an embodiment of bipolar IC according to the present invention;
Figure 3 is a graph showing the relationship between the frequency of operation fT and the collector current lc of a lateral pnp transistor, using a base width W as a parameter;
Figure 4 is a graph showing the relationship between the direct current gain hFE, the collector-emitter breakdown voltage VCEO and the base width W of a lateral pnp transistor; and
Figure 5 is a graph showing the relationship between the frequency of operation fT and the collector current lc of a vertical pnp transistor.
A method of manufacturing an embodiment of bipolar IC will now be described. As shown in Fig. 2A, n type impurities such as arsenic (As) or antimony (Sb) are highly diffused into a p type silicon substrate 1 to form n+ type buried layers 2 and 3. An n type silicon epitaxial layer 4 having a thickness of, for example 2#m, and a resistivity p of Incm (corresponding to an impurity concentration of 5X10'5 cm 3) is formed on the p type silicon substrate 1. Subsequently, a silicon dioxide (SiO2) film 24 is formed on the surface of the silicon epitaxial layer 4. Subsequently, n type impurities such as As are selectively ion-implanted into the silicon epitaxial layer 4 through the SiO2 film 24 under predetermined conditions. The implanted impurities in the silicon epitaxial layer 4 are represented by hol low dots.
As shown in Fig. 2B, a predetermined portion of the SiO2 film 24 is etched to form openings 24a to 24d. Subsequently, p type impurities such as boron (B) are diffused into the silicon epitaxial layer 4 through the openings 24a to 24d to form a p+ type isolation diffusion region 5 reaching the p type silicon substrate 1. In the heating process for forming the isolation diffusion region 5, the implanted impurities are diffused into the silicon epitaxial layer 4 to a predetermined depth and the impurities are electrically activated. As a result, n type regions 26 to 28 are formed in the silicon epitaxial layer 4. In this case, the regions 26 to 28 have an impurity concentration of, for example, 5X 1016 cm-3, that is higher than that of the silicon epitaxial layer 4, but lower than that of a p type base region 7 of an npn transistor 17 (to be described later).
As shown in Fig. 2C, a p type collector region 11 and an emitter region 10 are formed in the n type region 26, a p type emitter region 8 is formed in the n type region 27, and a p type base region 7 is formed in the silicon epitaxial layer 4. At the same time, a p type collector electrode region 9 for a vertical pnp transistor is formed in the layer 4. Thereafter, a p' type graft-base region 29 is formed in the base region 7, and p type regions 30 an 31 are formed in the emitter regions 8 and 10, respectively.
As shown in Fig. 2D, n' type base electrode regions 15 and 14 and an n' type collector electrode region 13 are formed in the n type regions 26 to 28, respectively. At the same time, after an n type emitter region 12 has been formed in the base region 7, electrodes (not shown) are formed in contact with the regions 9, 11 to 15 and 29 to 31, thereby completing a bipolar IC.
The relationship between the frequency of operation fT and the collector current lc of a lateral pnp transistor 22 in the bipolar IC of
Fig. 2D is shown in Fig. 3, using the base width W as a parameter. The relationship between the direct current gain h,E, the collector- emitter breakdown voltage VCEO, and the base width W of the lateral pnp transistor 22 is shown in Fig. 4.
As is apparent from Fig. 4, if W=2 ,um is given, the voltage VCEO in the conventional transistor is less than 5 V and the punchthrough phenomenon occurs. However, with the lateral pnp transistor 22 of this embodiment, the voltage VCEO can be kept as high as about 10 V without greatly decreasing the gain hFE. For this reason, as apparent from Fig.
3, a frequency fT of about 50 to 60 MHz can be be obtained.
The relationship between the frequency fT and the collector current Ic of the vertical pnp transistor in this embodiment of bipolar IC is shown in Fig. 5. As is apparent from Fig. 5, only the frequency fT of about 20 MHz is obtained by using a silicon epitaxial layer 4 having a thickness (5 ijm or more) free from the punch-through phenomenon, even in the vertical pnp transistor in the known bipolar IC.
However, the frequency fT of the vertical pnp transistor in this embodiment of bipolar IC can be as high as 100 MHz, by using the silicon epitaxial layer 4 having a thickness of 2 ,am.
In addition, the voltage VCEO can be increased to 15 V or more.
With the embodiment, even if the thickness of the silicon epitaxial layer 4 is as small as 2 #m, the voltages VCEC of the lateral and vertical pnp transistors 22 and 20 can be kept high, thereby obtaining a high frequency fT without the punch-through phenomenon. The punch-through phenomenon can be prevented for the following reason. The n type regions 26 and 27 are formed in the silicon epitaxial layer 4 having an impurity concentration higher than that thereof, and the lateral and vertical pnp transistors 22 and 20 are formed in the n type regions 26 and 27, respectively. Therefore, a depletion layer width at the collectorbase junction within the base region can be increased by a difference between the impurity concentration of the region 26 or 27, and that of the silicon epitaxial layer 4.
Various modifications are of course possible. In the above embodiment, the impurity concentration of the n type regions 26 to 28 is 5X10'6 cm 3. However, the impurity concentration may be increased or decreased as needed. However, in order effectively to prevent the punch-through phenbmenon, the impurity concentration range is preferably 1X1016 to 1X1017 cm 3
Claims (8)
1. A semiconductor device with npn and pnp transistors, wherein a said npn transistor is formed in an n type epitaxial layer formed on a semiconductor substrate, and a said pnp transistor is formed in an n type semiconductor region formed in said n type epitaxial layer, said n type semiconductor region having a higher impurity concentration than that of said n type epitaxial layer.
2. A device according to claim 1 comprising lateral and vertical pnp transistors.
3. A device according to claim 1 or claim 2 wherein the impurity concentration of said n type semiconductor region falls in the range 1x10l6 cm 3 to 1 X 1017 cm-3.
4. A device according to claim 1, claim 2 or claim 3 wherein said n type epitaxial layer has a thickness of not more than 5,us.
5. A device according to any one of the preceding claims wherein said n type epitaxial layer has a thickness in the range 1 to 2 ,am.
6. A device according to any one of the preceding claims wherein said n type epitaxial layer comprises an n type silicon epitaxial layer.
7. A device according to any one of the preceding claims wherein said semiconductor device comprises a bipolar integrated circuit.
8. A semiconductor device substantially as hereinbefore described with reference to Fig.
2D of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59232870A JPH0638476B2 (en) | 1984-11-05 | 1984-11-05 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8526749D0 GB8526749D0 (en) | 1985-12-04 |
| GB2167231A true GB2167231A (en) | 1986-05-21 |
| GB2167231B GB2167231B (en) | 1988-03-02 |
Family
ID=16946115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08526749A Expired GB2167231B (en) | 1984-11-05 | 1985-10-30 | Semiconductor devices |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JPH0638476B2 (en) |
| KR (1) | KR940005447B1 (en) |
| CN (1) | CN1004845B (en) |
| AT (1) | AT395272B (en) |
| AU (1) | AU572005B2 (en) |
| CA (1) | CA1254671A (en) |
| DE (1) | DE3539208C2 (en) |
| FR (1) | FR2572850B1 (en) |
| GB (1) | GB2167231B (en) |
| NL (1) | NL194711C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6768183B2 (en) * | 2001-04-20 | 2004-07-27 | Denso Corporation | Semiconductor device having bipolar transistors |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1520515A (en) * | 1967-02-07 | 1968-04-12 | Radiotechnique Coprim Rtc | Integrated circuits incorporating transistors of opposite types and methods of making them |
| JPS5710964A (en) * | 1980-06-25 | 1982-01-20 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58212159A (en) * | 1982-06-02 | 1983-12-09 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
| DE3361832D1 (en) * | 1982-04-19 | 1986-02-27 | Matsushita Electric Ind Co Ltd | Semiconductor ic and method of making the same |
-
1984
- 1984-11-05 JP JP59232870A patent/JPH0638476B2/en not_active Expired - Lifetime
-
1985
- 1985-10-15 KR KR1019850007581A patent/KR940005447B1/en not_active IP Right Cessation
- 1985-10-28 CA CA000493970A patent/CA1254671A/en not_active Expired
- 1985-10-30 GB GB08526749A patent/GB2167231B/en not_active Expired
- 1985-11-02 CN CN85108134.7A patent/CN1004845B/en not_active Expired
- 1985-11-04 AU AU49315/85A patent/AU572005B2/en not_active Expired
- 1985-11-05 AT AT0318985A patent/AT395272B/en not_active IP Right Cessation
- 1985-11-05 NL NL8503033A patent/NL194711C/en not_active IP Right Cessation
- 1985-11-05 FR FR8516362A patent/FR2572850B1/en not_active Expired
- 1985-11-05 DE DE3539208A patent/DE3539208C2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6768183B2 (en) * | 2001-04-20 | 2004-07-27 | Denso Corporation | Semiconductor device having bipolar transistors |
Also Published As
| Publication number | Publication date |
|---|---|
| AU4931585A (en) | 1986-05-15 |
| NL194711B (en) | 2002-08-01 |
| AU572005B2 (en) | 1988-04-28 |
| FR2572850A1 (en) | 1986-05-09 |
| JPS61111575A (en) | 1986-05-29 |
| DE3539208A1 (en) | 1986-05-15 |
| KR940005447B1 (en) | 1994-06-18 |
| JPH0638476B2 (en) | 1994-05-18 |
| CN85108134A (en) | 1986-07-02 |
| NL194711C (en) | 2002-12-03 |
| KR860004472A (en) | 1986-06-23 |
| GB2167231B (en) | 1988-03-02 |
| FR2572850B1 (en) | 1988-09-09 |
| CA1254671A (en) | 1989-05-23 |
| CN1004845B (en) | 1989-07-19 |
| NL8503033A (en) | 1986-06-02 |
| DE3539208C2 (en) | 1998-04-09 |
| GB8526749D0 (en) | 1985-12-04 |
| ATA318985A (en) | 1992-03-15 |
| AT395272B (en) | 1992-11-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |