JPS63128751A - Vertical-type pnp transistor - Google Patents
Vertical-type pnp transistorInfo
- Publication number
- JPS63128751A JPS63128751A JP27585486A JP27585486A JPS63128751A JP S63128751 A JPS63128751 A JP S63128751A JP 27585486 A JP27585486 A JP 27585486A JP 27585486 A JP27585486 A JP 27585486A JP S63128751 A JPS63128751 A JP S63128751A
- Authority
- JP
- Japan
- Prior art keywords
- region
- collector
- buried layer
- base
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 18
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052796 boron Inorganic materials 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052787 antimony Inorganic materials 0.000 abstract description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract 2
- 239000012535 impurity Substances 0.000 description 13
- 238000000926 separation method Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 238000005192 partition Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 101150091051 cit-1 gene Proteins 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は集積回路に組込まれる縦型ＰＮＰトランジスタ
に関し、特に微細化し且つ特性良好な縦型ＰＮＰトラン
ジスタに関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a vertical PNP transistor incorporated into an integrated circuit, and particularly to a vertical PNP transistor that is miniaturized and has good characteristics.
（ロ）従来の技術
従来の縦型ＰＮＰ トランジスタとしては、例えば特開
昭５９−２１１２７０号公報の第１図に記載されている
ものが一般的である。(B) Prior Art As a conventional vertical PNP transistor, for example, the one shown in FIG. 1 of Japanese Unexamined Patent Publication No. 59-211270 is generally used.
第３図は斯る構造の縦型ＰＮＰ トランジスタを示し、
Ｐ型シリコン半導体基板（１）上に積層して形成したＮ
型エピタキシャル層（２）と、基板（１〉表面に形成し
たＮ＋型の埋込層（３）と、埋込層（３）を取囲む様に
エピタキシャル層（２〉を貫通したＰ“型の上下分離領
域（りと、埋込層（３）に重畳して形成したＰ＋型のコ
レクタ埋込層（５）と、エピタキシャル層（２）表面か
らコレクタ埋込層（５）まで達し、且つベース領域（６
）を囲む様に形成したＰ型のコレクタ導出領域（７）と
、ベース領域（６）表面に形成したＰ型のエミッタ領域
（８）及びＮ＋型のベースコンタクト領域（９）と、酸
化膜（１０）と、電極（１１）とで構成されている。Figure 3 shows a vertical PNP transistor with such a structure.
N layered and formed on a P-type silicon semiconductor substrate (1)
type epitaxial layer (2), an N+ type buried layer (3) formed on the surface of the substrate (1>), and a P" type buried layer (3) that penetrates through the epitaxial layer (2) surrounding the buried layer (3). A P+ type collector buried layer (5) formed to overlap with the buried layer (3) and a layer extending from the surface of the epitaxial layer (2) to the collector buried layer (5) and the base. Area (6
), a P-type emitter region (8) and an N+-type base contact region (9) formed on the surface of the base region (6), and an oxide film ( 10) and an electrode (11).
（ハ）発明が解決しようとする問題点
しかしながら、斯上した構造ではベース領域（６〉とし
てエピタキシャル層（２〉を用いる為、その領域を区画
し且つコレクタ埋込層（５）を取出すべくリング状にコ
レクタ導出領域（７）を設ける必要があり、それは上下
分離領域（りの上側の拡散層と同一工程で形成するのが
普通である。また、ベースを低不純物濃度のエピタキシ
ャル層（２）で形成するので、耐圧を考慮してベース幅
を十分広くとる必要がある。従ってコレクタ導出領域（
７）及び上下分離領域（４）の上側の拡散層をかなり深
く形成しなければならず、パターン面積が非常に大きく
なる欠点があった。また、ベースをエピタキシャル層（
２）で形成する均一ベース構造である為、ｆＴを高くで
きずり、のばらつきも大きい欠点があった。(c) Problems to be solved by the invention However, in the above structure, since the epitaxial layer (2) is used as the base region (6), a ring is required to partition the region and take out the collector buried layer (5). It is necessary to provide a collector lead-out region (7), which is usually formed in the same process as the upper diffusion layer of the upper and lower isolation regions. Therefore, the base width must be made sufficiently wide considering the withstand voltage.
7) and the upper diffusion layer of the upper and lower separation regions (4) must be formed quite deep, resulting in a drawback that the pattern area becomes very large. In addition, the base is coated with an epitaxial layer (
Since the uniform base structure is formed in step 2), fT cannot be made high, and there is a large variation in fT.
（ニ）問題点を解決するための手段
本発明は斯上した欠点に鑑みてなされ、エピタキシャル
層（２２）表面からコレクタ埋込層（２５）まで完全に
達する低不純物濃度のコレクタ領域（２６）と、コレク
タ領域（２６）表面に形成したＮ型のベース領域（２７
〉と、ベース領域（２６）表面に形成したＰ型のエミッ
タ領域（２８）とを具備し、さらにコレクタ領域（２６
）表面にベース領域（２７）を囲むようにリング状にＰ
型のコレクタコンタクト領域（２９）を設けたことを特
徴とする。(d) Means for Solving Problems The present invention has been made in view of the above-mentioned drawbacks, and includes a collector region (26) with a low impurity concentration that completely reaches from the surface of the epitaxial layer (22) to the collector buried layer (25). and an N-type base region (27) formed on the surface of the collector region (26).
), a P-type emitter region (28) formed on the surface of the base region (26), and a collector region (26).
) P on the surface in a ring shape surrounding the base region (27)
It is characterized by providing a type collector contact region (29).
（ネ）作用
本発明によれば、コレクタ領域（２６）とベース領域（
２７）とを共に拡散によって形成したので、ベースにな
る領域を区画するための領域が不要になり、エピタキシ
ャル層（２２）を薄くできるので、パターンサイズを縮
小できる。きらに、コレクタコンタクト領域（２９）を
リング状に配設したので、コレクタ領域（２６）表面に
おけるＮ型反転層を防止し、それによってコレクタ領域
（２６）を十分に低不純物濃度に設定できる。(f) Function According to the present invention, the collector region (26) and the base region (
27) are formed by diffusion, there is no need for a region for partitioning the base region, and the epitaxial layer (22) can be made thinner, so the pattern size can be reduced. Furthermore, since the collector contact region (29) is arranged in a ring shape, an N-type inversion layer is prevented from forming on the surface of the collector region (26), thereby making it possible to set the collector region (26) to a sufficiently low impurity concentration.
（へ）実施例 以下、本発明を図面を参照しながら詳細に説明する。(f) Example Hereinafter, the present invention will be explained in detail with reference to the drawings.
第１図は本発明による縦型ＰＮＰ トランジスタを示し
、Ｐ型半導体基板（２１）上に積層して形成したＮ型の
エピタキシャル層（２２）と、基板（２１）表面に埋込
んで形成したＮ＋型の埋込層（２３）と、この埋込層（
２３）を囲むようにしてエピタキシャル層（２２）を貫
通したＰ９型の上下分離領域（都）と、埋込層（２３）
に重畳して基板（２１）表面から上方向へ拡散形成した
Ｐ″′型のコレクタ埋込層（２５）と、エピタキシャル
！（２２）表面からコレクタ埋込層（２５）まで完全に
達する低不純物濃度のＰ型コレクタ領域（２６）と、コ
レクタ領域（２６）の表面に形成したＮ型のベース領域
り２７）と、ベース領域（２７）表面に形成したＰ型の
エミッタ領域（２８）と、コレクタ領域り２６）表面に
ベース領域（２７）を囲むようにリング状に形成したコ
レクタ領域（２６）より高濃度のコレクタコンタクト領
域（２９）と、ベース領域（２７）表面に形成したベー
スコンタクト領域（３０）と、酸化膜（３１）及びコン
タクトホールを介して各領域とオーミンクコンタクトす
る電極（３２）とで構成きれている。FIG. 1 shows a vertical PNP transistor according to the present invention, which includes an N-type epitaxial layer (22) laminated on a P-type semiconductor substrate (21), and an N+ layer formed embedded in the surface of the substrate (21). The embedded layer (23) of the mold and this embedded layer (
A P9 type upper and lower separation region (capital) penetrating the epitaxial layer (22) surrounding the epitaxial layer (23) and the buried layer (23)
A P'' type collector buried layer (25) which is superimposed and diffused upward from the substrate (21) surface, and a low impurity which completely reaches from the epitaxial! (22) surface to the collector buried layer (25). a concentrated P-type collector region (26), an N-type base region (27) formed on the surface of the collector region (26), and a P-type emitter region (28) formed on the surface of the base region (27); Collector region 26) A collector contact region (29) with a higher concentration than the collector region (26) formed in a ring shape surrounding the base region (27) on the surface, and a base contact region formed on the surface of the base region (27). (30), and an electrode (32) that makes ohmink contact with each region via an oxide film (31) and a contact hole.
次に本発明による縦型ＰＮＰ トランジスタの製造方法
を説明する。Next, a method for manufacturing a vertical PNP transistor according to the present invention will be explained.
先ず第２図Ａに示す如く、半導体基板（２１）表面に埋
込層（２３）を形成するアンチモン（５ｂ）をデポジッ
トし、埋込層（２３）上及び埋込層（２３）を囲む基板
（２１）表面にはコレクタ埋込層（２５）と上下分離領
域（２４）の下側拡散層（３３）を形成するボロン（Ｂ
）をデポジットする。First, as shown in FIG. 2A, antimony (5b) to form a buried layer (23) is deposited on the surface of a semiconductor substrate (21), and the substrate is deposited on the buried layer (23) and surrounding the buried layer (23). (21) On the surface, boron (B) forms the collector buried layer (25) and the lower diffusion layer (33) of the upper and lower separation regions (24).
).
次に第２図Ｂに示す如く、基板（２１）全面に周知の気
相成長法によってエピタキシャル層（２２）を約７μｍ
程度に積層して形成し、コレクタ埋込層（２５）に対応
するエピタキシャル層（２２）表面にコレクタ領域（２
６）を形成するボロン（Ｂ）をドーズ量１０”ａｎ−”
、加速電圧８０〜２００ＫｅＶ程度の条件でイオン注入
する。Next, as shown in FIG. 2B, an epitaxial layer (22) is formed to a thickness of approximately 7 μm over the entire surface of the substrate (21) by a well-known vapor phase growth method.
A collector region (2) is formed on the surface of the epitaxial layer (22) corresponding to the collector buried layer (25).
6) The dose of boron (B) to form 10"an-"
, ion implantation is performed under conditions of an acceleration voltage of about 80 to 200 KeV.
読いて第２図Ｃに示す如く、基板（２１）全体に熱処理
を加えてデポジット又はイオン注入した各領域をドライ
ブインし、コレクタ領域（２６）がコレクタ埋込層（２
５）に完全に達するように約２〜３μｍの深さに形成す
る。As shown in FIG. 2C, the entire substrate (21) is subjected to heat treatment and each deposited or ion-implanted region is driven in, and the collector region (26) becomes the collector buried layer (2).
5) to a depth of approximately 2 to 3 μm so as to completely reach .
そして第２図りに示す如く、コレクタ領域（２６）表面
にベース領域（２７）を形成するリン（Ｐ）をドーズ量
１０ ”ｃｍ−”、加速電圧６０〜１ＯＯＫａＶ程度の
条件でイオン注入を行い、上下分離領域（ハ）の上側拡
散層（３４）を拡散形成すると同時にベース領域（２７
）を約１〜２μｍの深きにドライブインする。Then, as shown in the second diagram, ion implantation of phosphorus (P) to form the base region (27) is performed on the surface of the collector region (26) at a dose of 10 cm and an acceleration voltage of about 60 to 1 OOKaV. At the same time, the upper diffusion layer (34) of the upper and lower separation regions (c) is formed by diffusion.
) to a depth of about 1-2 μm.
さらに第２図Ｅに示す如く、通常のバイポーラＮＰＮト
ランジスタのベース拡散工程によってＰ型のエミッタ領
域（２８）とコレクタコンタクト領域（２９）を拡散形
成し、続いてＮＰＮ トランジスタのエミッタ拡散工程
によってベース領域（２７）表面にベースコンタクト領
域（３０）を形成する。そして各領域上に電極（３２）
を配設して製造工程を終了する。Furthermore, as shown in FIG. 2E, a P-type emitter region (28) and a collector contact region (29) are formed by diffusion through a normal bipolar NPN transistor base diffusion process, and then a base region is formed through an NPN transistor emitter diffusion process. (27) Form a base contact region (30) on the surface. and electrodes (32) on each area
and complete the manufacturing process.
斯上した如く形成した縦型ＰＮＰ トランジスタによれ
ば、エピタキシャル層（２２）表面からコレクタ埋込層
（２５）に達するまで低濃度のＰ型コレクタ領域（２６
）を拡散形成したので、その表面に拡散によってベース
領域（２７）を形成することが可能になり、ベースとな
る領域を分離区画する必要が無くなる。具体的には従来
のコレクタ導出領域（７）が不要になり、そのため構造
的にパターンサイズを大幅に縮小することができる。According to the vertical PNP transistor formed as described above, a low concentration P-type collector region (26) is formed from the surface of the epitaxial layer (22) to the collector buried layer (25).
) is formed by diffusion, it becomes possible to form the base region (27) on the surface thereof by diffusion, and there is no need to separate and partition the region to serve as the base. Specifically, the conventional collector lead-out region (7) is no longer necessary, and therefore the pattern size can be structurally significantly reduced.
また、ベース領域（２７）はエピタキシャル層（２２）
より高不純物濃度にするのでベース幅を狭くでき、且つ
濃度勾配による加速電圧が働くので、１ｌｔＫ及びｆｌ
を向上でき、ｈＦＩｌのばらつきを抑えられる。Furthermore, the base region (27) is an epitaxial layer (22).
Since the impurity concentration is higher, the base width can be narrowed, and the acceleration voltage due to the concentration gradient works, so 1ltK and fl
can be improved, and variations in hFIl can be suppressed.
そして、コレクタ領域（２６）表面にリング状にコレク
タコンタクト領域（２９）を形成したので、コレクタ領
域（２６）のオーミックコンタクトをとると同時に表面
反転層を防止し、それによってコレクタ領域（２６）を
十分低不純物濃度に設定できる。つまり、コレクタ領域
（２６）としては、ベース・コレクタ間の耐圧をある程
度保つ為とエミッタ領域（２８）を形成するボロン（Ｂ
）のシリコンに対する固溶度に限界がある為に１０１Ｊ
〜１０″ｃＩＴ１′″１とかなり低不純物濃度であるこ
とが望ましい。ところが、この様な設定を行うとコレク
タ領域（２６）表面のボロン（Ｂ）が固溶度の差異によ
ってシリコン酸化膜（ＳｉＯ８）に吸収され、表面の不
純物濃度が低下してＮ型の反転層を生じてしまう。そこ
で本発明によれば、コレクタコンタクト領域（２９）を
ベース領域（２７）をリング状に完全に囲むように形成
することによって反転層によるベース領域（２７）から
エピタキシャル層（２２）へのリーク電流を防止してお
くのである。尚、反転層は深さが約５００Å以下である
ことから、コレクタコンタクト領域（２９）としてはそ
れ以上の深さとオーミンクコンタクトが得られる不純物
濃度であれば良い。Since the collector contact region (29) is formed in a ring shape on the surface of the collector region (26), ohmic contact is made with the collector region (26) and at the same time, a surface inversion layer is prevented. The impurity concentration can be set to a sufficiently low level. In other words, the collector region (26) is made of boron (B) to maintain a certain degree of breakdown voltage between the base and collector, and to form the emitter region (28).
) because there is a limit to its solid solubility in silicon.
It is desirable that the impurity concentration be quite low, such as ~10''cIT1''1. However, when such settings are made, boron (B) on the surface of the collector region (26) is absorbed into the silicon oxide film (SiO8) due to the difference in solid solubility, and the impurity concentration on the surface decreases, forming an N-type inversion layer. will occur. Therefore, according to the present invention, by forming the collector contact region (29) so as to completely surround the base region (27) in a ring shape, leakage current from the base region (27) to the epitaxial layer (22) due to the inversion layer is reduced. This is to prevent this. Note that since the inversion layer has a depth of about 500 Å or less, the collector contact region (29) may have a depth greater than that and an impurity concentration that provides an ohmink contact.
また、コレクタ領域（２６）を低不純物濃度に設定して
も、その底部に高濃度のコレクタ埋込層（２５）を設け
ていることと、従来よりエピタキシャル層（２２）を薄
く設定できることにより、従来と同等かそれ以上の飽和
電圧Ｖｃｔ（ｓａｔ）特性を有する。Furthermore, even if the collector region (26) is set to a low impurity concentration, the high concentration collector buried layer (25) is provided at the bottom of the collector region (26), and the epitaxial layer (22) can be set thinner than before. It has saturation voltage Vct (sat) characteristics that are equal to or higher than conventional ones.
そしてさらに、上述した製造方法によれば、コレクタ領
域（２６）を上下分離領域（都）の下側拡散層（３３）
の拡散工程で、ベース領域（２７）を上下分離領域（ハ
）の上側拡散層（３４）の拡散工程によって夫々ドライ
ブインするので、エピタキシャル層（２２）表面の分離
に要する占有面積を無駄に増加させずに済む。Furthermore, according to the manufacturing method described above, the collector region (26) is formed into the lower diffusion layer (33) of the upper and lower separation region (capital).
In the diffusion process, the base region (27) is driven in by the diffusion process of the upper diffusion layer (34) of the upper and lower separation regions (c), which increases the occupied area required for separating the surface of the epitaxial layer (22). I don't have to let it happen.
（ト）発明の詳細
な説明した如く、本発明によればコレクタ領域（２６）
をコレクタ埋込層（２５）に達するまで形成したので、
ベースとなる領域を拡散によって形成することができ、
それによってベースとなる領域を分離区画する必要が無
いのでパターンサイズを大幅に縮小できる利点を有する
。(G) As described in detail, according to the present invention, the collector area (26)
was formed until it reached the collector buried layer (25), so
The base region can be formed by diffusion,
Thereby, there is no need to separate and partition the base region, so there is an advantage that the pattern size can be significantly reduced.
また、ベース幅をベース領域〈２７）とエミッタ領域（
２８）との二重構造で制御できるので、その幅を大幅に
狭くでき、しかも濃度勾配によるドリフト電界が発生す
るので、ｈ□及びｆ’ｔを大幅に向上できる他、ｈ、Ｅ
のばらつきをも大幅に少くすることができる。Also, the base width is changed between the base area (27) and the emitter area (
28), the width can be significantly narrowed, and since a drift electric field is generated due to the concentration gradient, h□ and f't can be greatly improved, and h, E
It is also possible to significantly reduce the variation in
さらに、コレクタ領域（２６）表面にベース領域（２７
）を完全に囲むようにコレクタコンタクト領域（２９）
を設けたので、表面のＮ型反転層によるリーク電流を防
止することができ、それによってコレクタ領域（２６）
を１０′６程度と十分に低不純物濃度に設定して所定の
耐圧が得られる利点を有する。Further, a base region (27) is provided on the surface of the collector region (26).
) to completely surround the collector contact region (29)
, it is possible to prevent leakage current due to the N-type inversion layer on the surface, and thereby the collector region (26)
It has the advantage that a predetermined breakdown voltage can be obtained by setting the impurity concentration to a sufficiently low impurity concentration of about 10'6.
そして、コレクタ領域（２６）底部に高不純物濃度のコ
レクタ埋込層（２５）が存在するので、コレクタ領域（
２６）を低不純物濃度に設定しても良好なＶＣ！（ｓａ
ｔ）特性が得られる利点をも有する。Since the collector buried layer (25) with a high impurity concentration exists at the bottom of the collector region (26),
26) Good VC even when set to a low impurity concentration! (sa
t) It also has the advantage of obtaining characteristics.
第１図は本発明に依る縦型ＰＮＰトランジスタを説明す
る断面図、第２図Ａ乃至第２図Ｅは本発明の縦型ＰＮＰ
トランジスタの製造方法を説明する断面図、第３図は
従来の縦型ＰＮＰトランジスタを説明する断面図である
。
（２１）は半導体基板、（２２）はエピタキシャル層、
（２３）は埋込層、 （２５）はコレクタ埋込層、（２
６）はコレクタ領域、 （２７）はベース領域、 （２
８）はエミッタ領域、 （２９）はコレクタコンタクト
領域である。
出願人 王洋電機株式会社外１名
代理人 弁理士 西野卓嗣 外１名
第１図
第２図Ａ
第２図Ｂ
第２図Ｃ
第２図り
第２図Ｅ
第３図FIG. 1 is a cross-sectional view illustrating a vertical PNP transistor according to the present invention, and FIGS. 2A to 2E are vertical PNP transistors according to the present invention.
FIG. 3 is a sectional view illustrating a method of manufacturing a transistor, and FIG. 3 is a sectional view illustrating a conventional vertical PNP transistor. (21) is a semiconductor substrate, (22) is an epitaxial layer,
(23) is a buried layer, (25) is a collector buried layer, (2
6) is the collector area, (27) is the base area, (2
8) is an emitter region, and (29) is a collector contact region. Applicant: Ohyo Denki Co., Ltd. and one other agent Patent attorney Takuji Nishino and one other person Figure 1 Figure 2 A Figure 2 B Figure 2 C Figure 2 Figure 2 E Figure 3
Claims (1)
電型のエピタキシャル層と、前記基板表面に形成した逆
導電型の埋込層と、該埋込層を囲むように前記エピタキ
シャル層を貫通した一導電型の分離領域と、前記埋込層
に重畳して上方向へ拡散形成した一導電型のコレクタ埋
込層と、前記エピタキシャル層表面から前記コレクタ埋
込層まで完全に達する一導電型のコレクタ領域と、該コ
レクタ領域表面に形成した逆導電型のベース領域と、該
ベース領域表面に形成した一導電型のエミッタ領域と、
前記ベース領域をリング状に囲むように前記コレクタ領
域表面に形成した一導電型のコレクタコンタクト領域と
を具備することを特徴とする縦型ＰＮＰトランジスタ。(1) An epitaxial layer of an opposite conductivity type formed by stacking on a semiconductor substrate of one conductivity type, a buried layer of an opposite conductivity type formed on the surface of the substrate, and the epitaxial layer surrounding the buried layer. an isolation region of one conductivity type penetrating through the buried layer, a collector buried layer of one conductivity type formed by overlapping with the buried layer and diffused upward, and a collector buried layer of one conductivity type extending completely from the surface of the epitaxial layer to the collector buried layer. a collector region of a conductivity type, a base region of an opposite conductivity type formed on a surface of the collector region, and an emitter region of one conductivity type formed on a surface of the base region;
A vertical PNP transistor comprising a collector contact region of one conductivity type formed on the surface of the collector region so as to surround the base region in a ring shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27585486A JPS63128751A (en) | 1986-11-19 | 1986-11-19 | Vertical-type pnp transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27585486A JPS63128751A (en) | 1986-11-19 | 1986-11-19 | Vertical-type pnp transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63128751A true JPS63128751A (en) | 1988-06-01 |
Family
ID=17561357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27585486A Pending JPS63128751A (en) | 1986-11-19 | 1986-11-19 | Vertical-type pnp transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63128751A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5455383A (en) * | 1977-10-12 | 1979-05-02 | Japan Radio Co Ltd | Semiconductor |
| JPS60247968A (en) * | 1984-05-23 | 1985-12-07 | Nec Corp | Semiconductor device |
| JPS61242062A (en) * | 1985-04-19 | 1986-10-28 | Sanyo Electric Co Ltd | Manufacture of semiconductor integrated circuit |
| JPS61244066A (en) * | 1986-01-13 | 1986-10-30 | Sanyo Electric Co Ltd | Vertical-type pnp transistor |
-
1986
- 1986-11-19 JP JP27585486A patent/JPS63128751A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5455383A (en) * | 1977-10-12 | 1979-05-02 | Japan Radio Co Ltd | Semiconductor |
| JPS60247968A (en) * | 1984-05-23 | 1985-12-07 | Nec Corp | Semiconductor device |
| JPS61242062A (en) * | 1985-04-19 | 1986-10-28 | Sanyo Electric Co Ltd | Manufacture of semiconductor integrated circuit |
| JPS61244066A (en) * | 1986-01-13 | 1986-10-30 | Sanyo Electric Co Ltd | Vertical-type pnp transistor |
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