JPS649742B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a constant voltage diode whose Zener breakdown voltage changes little over time.

Conventionally, as a method for forming a constant voltage diode in a semiconductor integrated circuit, for example, as shown in FIG.
After growing an N-type epitaxial layer 2 on a type semiconductor substrate 1 and providing a P-type insulating separation layer 3 by a selective diffusion method, P-type and N-type impurity layers are sequentially diffused into the epitaxial layer 2 to form a transistor. A constant voltage diode was constructed by forming a base region 5 and an emitter region 6 of the structure, and a junction (hereinafter referred to as an emitter junction) formed by contacting the base region 5 and the emitter region 6.

The breakdown voltage of the voltage regulator diode having the above structure shows a significant change over time, especially at high temperatures, for example.
After passing a reverse breakdown current for a predetermined time, e.g., 3 mA, for 30 minutes in a temperature atmosphere of 125°C, e.g.
A test where the product is left in an atmosphere at a temperature of 150℃ (hereinafter referred to as H・
It was confirmed by the T・O・R test) that it has instability that changes from tens to hundreds of millivolts in a short period of time, and that this instability increases when molded with ordinary epoxy resin. It was done. For example, as a method for forming the base region, the H impurity is deposited as a P-type impurity at 980°C by selective diffusion, and then diffused at 1150°C for 50 minutes in a water vapor atmosphere (for example, the Zener voltage is 6.8V). - A change in breakdown voltage of approximately 50 to 200 mV before molding and approximately 200 to 500 mV after molding occurred in the T.O.R test.

As a result of investigating the causes of breakdown voltage instability through the H・T・O・R test, the present invention has discovered that a portion where a breakdown phenomenon occurs in a constant voltage diode (hereinafter referred to as a Zener breakdown portion) is located on the surface of a semiconductor substrate. The fact that the above instability increases as it approaches
and that the instability is reduced by covering the surface of the semiconductor substrate at the Zener breakdown region with a wiring metal via an insulating film, and that the Zener breakdown region of the semiconductor region forms an effective junction as a diode. This was done by focusing on the fact that the impurity occurs at the maximum concentration in the region with low impurity concentration, and eliminates the instability in the H・T・O・R test and suppresses the occurrence of changes in the Zener breakdown voltage over time. An object of the present invention is to provide a semiconductor device having no constant voltage diode.

In order to achieve the above object, the semiconductor device of the present invention comprises a semiconductor substrate of a first conductivity type, which is formed from a surface of a semiconductor substrate of a first conductivity type, and a semiconductor substrate of a second conductivity type having a higher impurity concentration than that of the semiconductor substrate.
a second conductivity type region formed from the surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate, with a predetermined interval between the second conductivity type first region and the second conductivity type first region; A region formed in contact with the first conductivity type region and the second region of the first conductivity type, the impurity concentration of which is lower than the concentration of the first conductivity type second region, and the maximum impurity concentration portion thereof is located from the surface of the semiconductor substrate. a second region having a depth of approximately 0.4μ or more and formed in contact with a side surface of the second region of the first conductivity type;
a third region of conductivity type; a second region of first conductivity type and a third region of second conductivity type;
A technical means is adopted that includes a wiring metal that completely covers the surface of the semiconductor substrate corresponding to the PN junction formed with the region with an insulating film interposed therebetween.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to embodiments shown in the drawings. 2 to 4 are cross-sectional views illustrating the method of manufacturing a semiconductor device of the present invention, and are an example of a case where a plurality of integrated circuit elements such as transistors (not shown) are also formed at the same time. First, as shown in FIG. 2, an N-type epitaxial layer 2 is grown on a P-type silicon semiconductor substrate 1, a P-type insulating isolation layer 3 is provided by selective diffusion as in the conventional method, and then the epitaxial layer is grown. P-type and N-type impurities having an impurity concentration required for an integrated circuit element are sequentially diffused into the transistor structure to form a P-type semiconductor region 5 at the same time as the base region of the transistor structure, and an N-type semiconductor region 6 at the same time at the emitter region. Form. It should be noted that since these P-type semiconductor region 5 and N-type semiconductor region 6 are formed by diffusion in the epitaxial layer 2, their impurity concentration is naturally higher than that of the epitaxial layer 2. It is generally highly concentrated because it is formed simultaneously with the base and emitter regions of the structure. Next, the oxide film 4 on the substrate surface in the area to be used as a constant voltage diode is
As shown in FIG. 2, after removing all or part of the P-type semiconductor region 5 and the N-type semiconductor region 6 by photoetching, a P-type impurity of the same conductivity type as the P-type semiconductor region 5, For example, boron ions are implanted at a predetermined acceleration voltage to form the P-type semiconductor region 8. This P-type semiconductor region 8 is in contact with the P-type semiconductor region 5 and the N-type semiconductor region 6, and
It is formed so as to be in contact with the side surface of the type semiconductor region 6. Thereafter, as shown in FIG. 3, a surface protective film 7 is formed by, for example, chemical vapor deposition, and annealed at, for example, 1000° C. for 10 minutes in a nitrogen atmosphere. After that, electrode formation is performed in the same manner as before.
As shown in FIG. 4, a relationship is established in which the junction formed between the N-type semiconductor region 6 and the P-type semiconductor region 8 formed by ion implantation is completely covered by the wiring metal of the electrode 9 in contact with the N-type semiconductor region 6. At the same time, as shown in the partially enlarged view of FIG. 5, which is an enlarged view of the part indicated by the dotted line frame A in FIG.
The length l of the electrode extension portion 9a extending on the upper part of the insulating film 4 covering the semiconductor substrate surface is approximately equal to 1 after the electrode is formed.
Set it to be 1μ or more.

The impurity ions implanted as described above are
In the depth direction, it is thought that there is a Gaussian distribution centered on the average penetration depth Rp of ions (referred to as projected range) depending on the ion accelerating voltage. FIG. 6 shows the relationship between the projected range Rp and the ion acceleration voltage E.
FIG. 7 shows the electrode extension portion 9 of the electrode 9 as shown in FIG.
Characteristic (a) when the length l of a is approximately 1 μ or more (hereinafter referred to as overlap), and the characteristics of the N-type semiconductor region 6 and the P-type semiconductor region 8 formed by ion implantation.
The relationship between the ion accelerating voltage E and the breakdown voltage change ΔVz is shown for the characteristic (b) when there is no electrode 9 (that is, an electrode extension part) on the junction formed by.

The breakdown voltage of the effective junction as a diode using the above-mentioned formation method is generally determined when the impurity concentration of the P-type semiconductor region 8 formed by ion implantation is 1, compared to the N-type semiconductor region 6 formed at the same time as the emitter of the transistor. Because the ^P It is understood that it is mostly determined by the distance (equal to the projected range Rp). This makes it possible to control the region where a breakdown phenomenon occurs in the diode junction formed by ion implantation by the acceleration voltage of the implanted ions. H・T・O・ after molding the constant voltage diode formed by the above method.
Characteristics a and b in FIG. 7 show the breakdown voltage change ΔVz due to the R test using the acceleration voltage E and the presence or absence of electrode overlap as parameters. As is clear from this figure, the higher the accelerating voltage E, the smaller ΔVz becomes, and ΔVz with overlap of the electrodes 9 is better than without overlap.
It can be seen that it is possible to form a constant voltage diode with small changes over time. As shown in characteristic a in Figure 7, if the electrodes overlap and the ion implantation acceleration voltage is at least 150 KeV, the maximum P ⁺ concentration will be at a depth of approximately 0.4 μ or more from the substrate surface, leading to breakdown. It has been found that the voltage change ΔVz can be made very small.

The reason for this is that by forming a part inside the diode junction that causes a breakdown phenomenon, hot carriers generated at breakdown enter the insulating film and create charge, which causes the breakdown voltage to change. In addition, by covering the surface of the semiconductor substrate corresponding to the diode junction with wiring metal through an insulating film, the wiring metal can prevent contaminants from entering the insulating film from the molding resin. This is because changes in breakdown voltage can be prevented.

Furthermore, according to this embodiment, N
Since the configuration is such that no PN junction is formed on the surface of the semiconductor substrate corresponding to the junction between the type semiconductor region 6 and the P-type semiconductor region 8, for example, when a PN junction is formed on the surface of the semiconductor substrate, The spread of the depletion layer in the PN junction does not affect the width of the depletion layer at the junction where the breakdown phenomenon occurs, which in turn changes the breakdown voltage. Can be made smaller.

Further, from the junction between the N-type semiconductor region 6 and the P-type semiconductor region 8, each region connected to the electrodes 9 and 10, that is, the P-type semiconductor regions 5 and 8, and the N
Since the type semiconductor region 6 has a high impurity concentration, the operating resistance of the diode can be reduced, and even if the amount of current flowing through the diode changes, the change in breakdown voltage can be reduced.

Note that although the above embodiments have described semiconductor integrated circuit devices including NPN transistors,
It goes without saying that the present invention can be similarly applied to semiconductor integrated circuit devices including transistors of completely opposite polarity, and semiconductor integrated circuit devices including MOS transistors. Moreover, it can be widely implemented as long as it is a Brehner type constant voltage diode.

As described above, according to the semiconductor device of the present invention, the instability caused by the H・T・O・R test is eliminated,
There is almost no change in the Zener breakdown voltage over time, and even if the current flowing through the diode changes, the change in the breakdown voltage can be made small, making it possible to obtain a semiconductor device having a highly reliable constant voltage diode. There is an effect.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a conventionally used constant voltage diode, FIGS. 2 to 4 are cross-sectional views during each manufacturing process in an embodiment of the semiconductor device of the present invention, and FIG. 5 is a cross-sectional view of the same semiconductor device. An enlarged cross-sectional view, FIG. 6 is a characteristic diagram showing changes in projected range with respect to boron ion implantation accelerating voltage, and FIG. 7 is a characteristic diagram showing changes in breakdown voltage of a constant voltage diode with respect to boron ion implantation accelerating voltage and electrode overlap. It is. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type epitaxial layer corresponding to a semiconductor base portion, 3... P-type insulating separation layer, 4... Oxide film, 5... P-type semiconductor region, 6... N type semiconductor region, 7... oxide film, 8...
...P-type semiconductor region formed by ion implantation, 9
. . . Electrode of N-type semiconductor region, 10 . . . Electrode of P-type semiconductor region.

Claims (1)

[Claims] 1. Formed from the surface of a semiconductor substrate of a first conductivity type,
a first region of a second conductivity type having a higher impurity concentration than the semiconductor substrate; and a first region of the second conductivity type formed from the surface of the semiconductor substrate with a predetermined interval and having a higher impurity concentration than the semiconductor substrate. a second region of a first conductivity type; a region formed in contact with the first region of the second conductivity type and the second region of the first conductivity type, the impurity concentration of which is lower than the concentration of the second region of the first conductivity type; a second region having a maximum impurity concentration at a depth of approximately 0.4μ or more from the surface of the semiconductor substrate and in contact with a side surface of the second region of the first conductivity type;
a third region of conductivity type; a second region of first conductivity type and a third region of second conductivity type;
1. A semiconductor device comprising: a wiring metal that completely covers a surface of the semiconductor substrate corresponding to a PN junction formed with a region with an insulating film interposed therebetween.