JPS6064481A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6064481A JPS6064481A JP17383583A JP17383583A JPS6064481A JP S6064481 A JPS6064481 A JP S6064481A JP 17383583 A JP17383583 A JP 17383583A JP 17383583 A JP17383583 A JP 17383583A JP S6064481 A JPS6064481 A JP S6064481A
- Authority
- JP
- Japan
- Prior art keywords
- region
- electrode
- semiconductor
- main surface
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 239000013078 crystal Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims 1
- 230000006866 deterioration Effects 0.000 abstract description 5
- 238000011109 contamination Methods 0.000 abstract description 4
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 238000009413 insulation Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置に係シ、特にラテラル型ダイオード
、ラテラル型トランジスタ、２チラル型サイリスタ等の
ラテラル型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to semiconductor devices, and more particularly to lateral semiconductor devices such as lateral diodes, lateral transistors, and 2-chiral thyristors.
従来のラテラル型半導体装置の一例として、第１図＜ａ
＞にラテラル型ダイオードの平面図を、第１図（ｂ）に
第１図（ａ）のＡ−Ａ’の「面図をそれぞれ示す。As an example of a conventional lateral type semiconductor device, FIG.
> shows a plan view of the lateral type diode, and FIG. 1(b) shows a cross-sectional view taken along line AA' in FIG. 1(a).
１１はｎｉｉシリコンから成るシリコン単結晶領域で、
１２はシリコンｊｉ１ｉ１１と多結晶シリコンから構成
される半導体支持領域１３の間にあって、これを電気的
に絶縁する絶縁族となる５１０ｚ膜である。１４は、シ
リコン単結晶領域１１の底面および側面に５ｊ０２膜１
２に接する様に形成したチャンネル阻止層で、高濃匿の
ｎ“型領域である。11 is a silicon single crystal region made of NII silicon;
Reference numeral 12 denotes a 510z film which is an insulating group and is located between the semiconductor support region 13 made of silicon ji1i11 and polycrystalline silicon and electrically insulates the semiconductor support region 13. 14 is a 5j02 film 1 on the bottom and side surfaces of the silicon single crystal region 11.
This is a channel blocking layer formed so as to be in contact with 2, and is a highly concentrated n'' type region.
１５はシリコン単結晶領域１１表面に形成したｐ型領域
で、この部分とシリコン単結晶領域１１のｎ型領域との
間に整流接合を形成している。１６は単結晶領域１１の
表面に形成される高不純物繭就のｎ＋型憤域である。１
７は誘電体膜となる５ｉＯｚｌｌｌでパッシベーション
と表面絶縁の役をする。１８はポンディングパッドであ
る。このような構造によれば、単結晶領域１１は絶縁物
であるところの８１０２膜に被れている為、近隣するダ
イオードとの間に極めて良好な絶縁が保たれる。A p-type region 15 is formed on the surface of the silicon single-crystal region 11, and a rectifying junction is formed between this region and the n-type region of the silicon single-crystal region 11. Reference numeral 16 denotes an n+ type region containing high impurities formed on the surface of the single crystal region 11. 1
7 is a dielectric film of 5iOzll, which serves as passivation and surface insulation. 18 is a bonding pad. According to this structure, since the single crystal region 11 is covered with the 8102 film, which is an insulator, extremely good insulation is maintained between the adjacent diodes.
しかしこの様な表面構造の場会、窒乏層の広がる、ｎ層
１１が底面に誘電体１１ｋをかいして露出している為、
誘電体膜である８ｊ０２膜の汚染によシ素子が劣化する
という事が兄生していた。However, in the case of such a surface structure, the nitrogen-depleted layer spreads and the n-layer 11 is exposed through the dielectric material 11k on the bottom surface.
It has been known that contamination of the 8J02 film, which is a dielectric film, causes deterioration of the device.
本発明の目的は、上記欠点を除去し、誘電体膜の汚染に
よる素子の耐圧劣化を防止し得る半導体装置を提供する
ことにるる。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which can eliminate the above-mentioned drawbacks and prevent deterioration of the breakdown voltage of the device due to contamination of the dielectric film.
上記目的を達成する本発明半導体装置の特徴とするとこ
ろは、一対の主表面を利し、その一部に少なくとも、一
方の主表面に蕗出する第１尋亀型の第１の領域、上記一
方の主表面に蕗出し上記第１の領域よシ尚不純物濃度の
第１専電型の第２の領域、上記第１の領域との間に形成
されるｐｎ接合が上記一方の主＆ａｌに終端する様に設
けられる第２４゛亀型の第３の領域、を有する半導体基
体と、上記一方の主表面に於いて上記第２の領域と低抵
抗接触し、かつ誘電体膜を介して上記第１の壊滅を超え
て上日己第３の領域上に蝙仕するように形成される第１
の電極と、上記一方の主表面に於いてトｉｔｌ’＋第３
の領域と低τ代抗ｌゲＨ＋Ｈすて）弔−２（ｒ抽（臥と
へ・具備することにある。The semiconductor device of the present invention that achieves the above object is characterized by a first turtle-shaped first region that utilizes a pair of main surfaces and protrudes on at least one of the main surfaces. A pn junction formed between the first region, which is exposed on one main surface, and the second region of the first exclusive type, which has an impurity concentration, and the first region, is formed on one main surface. a semiconductor substrate having a 24° tortoise-shaped third region disposed so as to terminate; and a semiconductor substrate having a low resistance contact with the second region on one main surface thereof and the second region through a dielectric film. The first one is formed to go beyond the first destruction and attack the third realm of Kaminichi.
and the third electrode on the one main surface.
The area of and low τ resistance is to have H + H away) -2 (r draw).
本発明の一実施例となるダイオードアレイの概略十面図
を第２図に示す。FIG. 2 shows a schematic ten-sided view of a diode array according to an embodiment of the present invention.
第２図に於いて、３０はｐ型アノードのコンタクト電極
、３１はＮ型カソードのコンタクト−極である、。In FIG. 2, 30 is a contact electrode for a p-type anode, and 31 is a contact electrode for an n-type cathode.
第３図（ａ）は、第２図に示すダイオードプレイの１個
のダイオードの平面図であシ、第３図（ｂ）は第３図（
ａ）のＢ−Ｂ’断面図、第３図（Ｃ）は第３図（ａ）の
Ｃ−Ｃ’断面図である。3(a) is a plan view of one diode of the diode play shown in FIG. 2, and FIG. 3(b) is a plan view of one diode of the diode play shown in FIG.
3(C) is a sectional view taken along CC' of FIG. 3(a).
第３図に於いて、４０は半導体基体でおシ、多結晶シリ
コンよシ成る半導体支持領域４３と、半導体支持領域４
３に５ｌｏｚ膜より成る絶縁膜４２を介して隣接し、か
つ半導体支持領域４３の一生表面に露出するように埋設
されるシリコン単結晶領域１０とから形成される。４１
はシリコン単結晶領域１０に設けられ、一部が半導体基
体４０の一方の主表面に露出するカソード領域となるｎ
型の第１の半導体領域で１．４６は第１の半導体領域４
１に接し、半導体基体４０の一方の主表面に露出し、か
つ第１の半導体領域４１よシ高不純物濃度のｎ９の第２
の半導体領域であシ、４４゜４４′及び４５は第１の半
導体領域４１との間に形成されるｐｉｅ合が半導体基体
４０の一方の主表面に終端する様に設けられるアノード
領域となるｐ型の第３の半導体領域である。第３０半導
体領域４４．４４’は絶縁層４２と接して、シリコン単
結晶領域１０の底面部分及び１１４１１ ［ｉ１部分に
設けられる。また、ｐ型の第３の半導体領域４５は、（
ω
第３図に示す様にＢ方向、Ｃ方向、及びＣ′力方向
の３方で側面部のｐ型の第３の半導体領域４４′と接し
ている。In FIG. 3, reference numeral 40 denotes a semiconductor substrate, and a semiconductor support region 43 made of polycrystalline silicon;
3 and a silicon single crystal region 10 which is adjacent to the silicon single crystal region 10 with an insulating film 42 made of a 5LOZ film interposed therebetween and which is buried so as to be permanently exposed on the surface of the semiconductor support region 43. 41
is provided in the silicon single crystal region 10 and serves as a cathode region partially exposed on one main surface of the semiconductor substrate 40.
1.46 in the first semiconductor region of the mold is the first semiconductor region 4
1, is exposed on one main surface of the semiconductor substrate 40, and has a higher impurity concentration than the first semiconductor region 41.
44°, 44', and 45 are anode regions provided such that the piezoelectric bond formed between the semiconductor region 44 and the first semiconductor region 41 terminates on one main surface of the semiconductor substrate 40. This is the third semiconductor region of the mold. The 30th semiconductor region 44, 44' is provided in contact with the insulating layer 42 at the bottom portion of the silicon single crystal region 10 and the 11411[i1 portion. Further, the p-type third semiconductor region 45 is (
ω As shown in FIG. 3, it is in contact with the p-type third semiconductor region 44' on the side surface in three directions: the B direction, the C direction, and the C' force direction.
４７は半導体基体４０の一方の主表面に形成した８１０
ｚＭよシ成る第１の誘電体膜であシ、ｎ型の第２の半導
体領域４６及びｐ型の第３の半導体領域４５にコンタク
トを形成するだめの開孔（１−除き、半導体基体４０の
一方の主表面を被う様に形成する。47 is 810 formed on one main surface of the semiconductor substrate 40
The first dielectric film is made of zM, and the openings (except for 1-, the semiconductor substrate 40 Formed so as to cover one main surface of.
４８は第１の電極（カソード）となるアルミニウムのコ
ンタクト金属でめシ、半導体基体４０の一方の主表面に
於いて、高不純物製置のｎ型の第２の半導体領域４６と
低抵抗接触し、かつ第３図（ｂ）のＤ部及びＥ部に示さ
れる様に第１の誘電体ｊ摸４７を介してｎ［の第１の半
導体領域４１ｔｌ−超えてｐｍの第３の半導体領域４５
上に延在するように形成されている。Reference numeral 48 denotes an aluminum contact metal serving as a first electrode (cathode), which is in low resistance contact with a highly impurity-doped n-type second semiconductor region 46 on one main surface of the semiconductor substrate 40. , and as shown in parts D and E of FIG. 3(b), the first semiconductor region 41 of n
It is formed to extend upward.
４９は第２の電極（アノード）となるアルミニウムのコ
ンタクト全域であシ、半導体基体４０の一方の主表面に
於いてｐ型の第３の半導体領域４５と低抵抗接触するよ
うに形成されている。Reference numeral 49 denotes the entire area of the aluminum contact serving as the second electrode (anode), and is formed to be in low resistance contact with the p-type third semiconductor region 45 on one main surface of the semiconductor substrate 40. .
５０は８１０２膜よシなる第２の誘電体膜であシ、第１
の誘電体膜４７、第１の電極４８、及び第２の′域極４
９を榎うように設けられておシ、第１の電極４８及び第
２の′電極４９の一部を露出する形で、部分的に除去し
である。50 is a second dielectric film such as 8102 film;
dielectric film 47, first electrode 48, and second region pole 4
9, and is partially removed to expose a portion of the first electrode 48 and the second electrode 49.
５１及び５２は、′＃Ｊ１の電極４８及び第２の電極４
９上にそれぞれ設けられたポンディングパッドで銅と金
との２層構造となる。51 and 52 are the electrode 48 of #J1 and the second electrode 4
A two-layer structure of copper and gold is formed by the bonding pads provided on each of the layers 9 and 9.
本実施例になる装置は、例えば特開昭５５−１３３５５
３号公報に示される通常の誘電体分離型半導体装置のプ
ロセスに牧舎を施すことによシ容易に製作できるもので
おる。The apparatus of this embodiment is, for example, disclosed in Japanese Unexamined Patent Publication No. 55-13355.
This device can be easily manufactured by applying a modification to the process of the normal dielectric isolation type semiconductor device shown in Publication No. 3.
不実施例の構成によれば、ｎ型の第１の半導体領域４１
の半導体基体４０の一方の主表面に露出する部分（第３
図（ｂ）のり、Ｅ）は、第１の誘電体膜４７を介して、
尚不純物濃度のｎ型の第２の半導体領域４６と低抵抗接
触する第１の゛−極４８が延在しているので、この部分
の第１の誘電体ｌＮ４７は、第２の半導体領域４６と同
直位となる。According to the configuration of the non-example, the n-type first semiconductor region 41
The portion exposed on one main surface of the semiconductor substrate 40 (the third
In the figure (b), the glue and E) are
Note that since the first electrode 48 that is in low resistance contact with the n-type second semiconductor region 46 having an impurity concentration extends, the first dielectric material 1N47 in this portion is in contact with the second semiconductor region 46. be on the same level as
従って、′電圧が印加された場合、第１の＋ｔＪ電体膜
４７が汚染されていても、貞′番３図（ｂ）のり、Ｅ部
分の望乏層の延びは、第２の半４）体顕域４６の同位に
よって一定に押さえられ、ダイオードの耐圧劣化を防ぎ
、安定な特性が得られる。Therefore, when the 'voltage' is applied, even if the first +tJ electric film 47 is contaminated, the extension of the depletion layer at the part E in Figure 3(b) will be reduced to the second half 47. ) It is held constant by the same level in the optical microscope region 46, preventing deterioration of the diode withstand voltage and providing stable characteristics.
また、不実施例の構造では、誘電体分離型であるので、
近隣するダイオード等の他の素子との絶縁が極めて艮好
となる。In addition, since the structure of the non-example is a dielectric separation type,
Insulation from other elements such as neighboring diodes is extremely good.
さらに、アノード領域となるｐｍの第３の半導体領域４
４．４４’は絶縁膜４２と接して、シリコン単結晶領域
１０の底面部分及び側面部分に設けられ、ｎ型の第１の
半導体領域４１とｐｎ接合を形成するので、ｐｎ接合の
面積が大きくなり、ダイオードの大きさを小さくするこ
とができる。Furthermore, a third semiconductor region 4 of pm which becomes an anode region
4.44' is provided on the bottom and side surfaces of the silicon single crystal region 10 in contact with the insulating film 42, and forms a pn junction with the n-type first semiconductor region 41, so the area of the pn junction is large. Therefore, the size of the diode can be reduced.
例えば、不実施例では、ダイオード１ケ当シの衣曲槓０
．０３２−で、足格ｒｍ電流２０１ｎＡを達成すること
ができる。For example, in a non-implemented example, a diode of 1 pc.
．． 032-, a current of 201 nA can be achieved.
さらに、本実施例に於いては、アノード領域となるｐ型
の第３の半導体領域４５は、第３図（ａ）にオード動作
時の残留キャリアの引き出しが促進され、高速動作が実
現される。Furthermore, in this embodiment, the p-type third semiconductor region 45 serving as the anode region promotes extraction of residual carriers during the ordinal operation as shown in FIG. 3(a), thereby realizing high-speed operation. .
本発明は実施例に挙げたダイオードに限らず、トランジ
スタ、サイリスク等にも通用できるものである。また、
半導体基体についても、誘電体分離型半導体基体に限ら
ず、ｐｎ接合分離型等に於いても適用できる。The present invention is applicable not only to the diodes mentioned in the embodiments but also to transistors, silices, etc. Also,
Regarding the semiconductor substrate, it is applicable not only to a dielectric separation type semiconductor substrate but also to a pn junction separation type and the like.
以上述べた様に、本発明によれば、誘電体膜の汚染によ
る素子の耐圧劣化を防止し得る半導体装置を得ることが
できる。As described above, according to the present invention, it is possible to obtain a semiconductor device that can prevent deterioration of breakdown voltage of an element due to contamination of a dielectric film.
第１図は従来例となるダイオードの平面図及び断面図、
第２図は本発明の一実施例となるダイオードアレイ泉の
概略断面図、第３図は第２図に示すダイオードアレイの
１個のダイオードの平田１図及び断面図である。
４０・・・半導体基体、４１・・・第１の半導体領域、
４４．４４’ 、４５・・・第３の牛尋不狽域、４６・
・・第２の半導体領域、４７・・・第１のｄ電体ＩＮ、
４８・・・第１の′１他、４９・・・第２のｊ払５０・
・・第２のｆＪｊｍ体膜、１０・・・シリコン率結晶狽
域、４３・・・半導体支持領域。
代理人 弁理士 高槁明夫
第３ 図
第５図
１ｊ）
第 ３ 図
（Ｃ）FIG. 1 is a plan view and a cross-sectional view of a conventional diode,
FIG. 2 is a schematic cross-sectional view of a diode array spring according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view of one diode of the diode array shown in FIG. 2. 40... Semiconductor base, 41... First semiconductor region,
44.44', 45...Third Ushijinfu area, 46.
. . . second semiconductor region, 47 . . . first d-electric body IN,
48...first '1, etc., 49...second j payment 50.
. . . second fJjm body film, 10 . . . silicon fraction crystallization region, 43 . . . semiconductor support region. Agent Patent Attorney Akio Takamichi (Figure 3, Figure 5, 1j) Figure 3 (C)
Claims (1)
の主表面に露出する第１導ｉ！型の第１の領域、上記一
方の主表面に露出し上記第１の領域より高不純物載板の
第１噂′に型の第２の領域、上記第１の領域との間に形
成されるｐｎ接会が上記一方の主表面に終端する様に設
けられる第２導電型の第３の領域、を有する半導体基体
と、上記一方の主表面に於いて上記第２の領域と低抵抗
接触し、かつ誘電体膜を介して上記第１の領域金超えて
上記第３の懺域上に延在するように形成される第１の電
極と、上記一方の主表面に於いて上記第３の領域と低抵
抗接触する第２の電極とを具備することを特徴とする半
導体装置。 ２、特許請求の範囲第１項に於いて、上記半導体基体は
、半導体支持領域と、該半導体支持領域に絶縁族を介し
て隣設しかつ上記支持領域の一方の主表面に露出するよ
うに埋設される単結晶領域とから形成され、上記第１．
第２及び躬３領域は上記単結晶領域に設けられることを
特徴とする半導体装１゜ ３、特許請求の範囲第２項に於いて、上記′＃Ｊ３の領
域の少なくとも一部は、上記絶縁膜と接して設けられる
ことを特徴とする半導体装置。[Claims] 1. A first conductor i! which has a pair of main surfaces and is partially exposed to at least one of the main surfaces. A first region of the mold, exposed on the one main surface of the mold, and formed between the second region of the mold and the first region, which is higher in impurity than the first region. a third region of a second conductivity type provided such that a pn junction terminates on the one main surface; and a third region of a second conductivity type that is in low resistance contact with the second region on the one main surface. , and a first electrode formed to extend beyond the first region and onto the third area via a dielectric film, and a first electrode formed on the one main surface of the third area. A semiconductor device comprising a second electrode in low resistance contact with the region. 2. In claim 1, the semiconductor substrate includes a semiconductor support region, and a semiconductor substrate adjacent to the semiconductor support region via an insulating layer and exposed on one main surface of the support region. and a single crystal region to be buried, and the first.
In the semiconductor device 1゜3, characterized in that the second and third regions are provided in the single crystal region, in claim 2, at least a part of the region '#J3 is A semiconductor device characterized in that it is provided in contact with a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17383583A JPS6064481A (en) | 1983-09-19 | 1983-09-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17383583A JPS6064481A (en) | 1983-09-19 | 1983-09-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6064481A true JPS6064481A (en) | 1985-04-13 |
| JPH0516196B2 JPH0516196B2 (en) | 1993-03-03 |
Family
ID=15968035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17383583A Granted JPS6064481A (en) | 1983-09-19 | 1983-09-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6064481A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63126243A (en) * | 1986-11-17 | 1988-05-30 | Toshiba Corp | Integrated circuit element and manufacture thereof |
| JPH04125023A (en) * | 1990-09-14 | 1992-04-24 | Fuji Electric Co Ltd | Short circuit detecting circuit for arm of gto inverter |
| JP2005259775A (en) * | 2004-03-09 | 2005-09-22 | Oki Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49127576A (en) * | 1973-04-05 | 1974-12-06 | ||
| JPS5146880A (en) * | 1974-10-18 | 1976-04-21 | Matsushita Electronics Corp | TORANJISUTA |
| JPS55115340A (en) * | 1979-02-26 | 1980-09-05 | Hitachi Ltd | Semiconductor device |
| JPS56103460A (en) * | 1980-01-21 | 1981-08-18 | Mitsubishi Electric Corp | Semiconductor device |
| JPS56112752A (en) * | 1980-02-12 | 1981-09-05 | Nec Corp | Semiconductor device |
| JPS572567A (en) * | 1980-06-06 | 1982-01-07 | Nec Corp | Semiconductor device |
| JPS577956A (en) * | 1980-06-17 | 1982-01-16 | Mitsubishi Electric Corp | Semiconductor device |
| JPS5720476A (en) * | 1980-07-10 | 1982-02-02 | Mitsubishi Electric Corp | Diode |
| JPS57169273A (en) * | 1981-04-13 | 1982-10-18 | Nippon Denso Co Ltd | Semiconductor device |
| JPS5856352A (en) * | 1981-09-30 | 1983-04-04 | Hitachi Ltd | Semiconductor integrated circuit |
-
1983
- 1983-09-19 JP JP17383583A patent/JPS6064481A/en active Granted
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49127576A (en) * | 1973-04-05 | 1974-12-06 | ||
| JPS5146880A (en) * | 1974-10-18 | 1976-04-21 | Matsushita Electronics Corp | TORANJISUTA |
| JPS55115340A (en) * | 1979-02-26 | 1980-09-05 | Hitachi Ltd | Semiconductor device |
| JPS56103460A (en) * | 1980-01-21 | 1981-08-18 | Mitsubishi Electric Corp | Semiconductor device |
| JPS56112752A (en) * | 1980-02-12 | 1981-09-05 | Nec Corp | Semiconductor device |
| JPS572567A (en) * | 1980-06-06 | 1982-01-07 | Nec Corp | Semiconductor device |
| JPS577956A (en) * | 1980-06-17 | 1982-01-16 | Mitsubishi Electric Corp | Semiconductor device |
| JPS5720476A (en) * | 1980-07-10 | 1982-02-02 | Mitsubishi Electric Corp | Diode |
| JPS57169273A (en) * | 1981-04-13 | 1982-10-18 | Nippon Denso Co Ltd | Semiconductor device |
| JPS5856352A (en) * | 1981-09-30 | 1983-04-04 | Hitachi Ltd | Semiconductor integrated circuit |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63126243A (en) * | 1986-11-17 | 1988-05-30 | Toshiba Corp | Integrated circuit element and manufacture thereof |
| JPH04125023A (en) * | 1990-09-14 | 1992-04-24 | Fuji Electric Co Ltd | Short circuit detecting circuit for arm of gto inverter |
| JP2005259775A (en) * | 2004-03-09 | 2005-09-22 | Oki Electric Ind Co Ltd | Semiconductor device and method of manufacturing the same |
| JP4657614B2 (en) * | 2004-03-09 | 2011-03-23 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor device and manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0516196B2 (en) | 1993-03-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7391093B2 (en) | Semiconductor device with a guard-ring structure and a field plate formed of polycrystalline silicon film embedded in an insulating film | |
| US7772669B2 (en) | Semiconductor device having an improved structure for high withstand voltage | |
| JP5154000B2 (en) | Semiconductor device | |
| JP3275536B2 (en) | Semiconductor device and manufacturing method thereof | |
| US11552016B2 (en) | Semiconductor device with metallization structure on opposite sides of a semiconductor portion | |
| US20200273767A1 (en) | Electronic chip package | |
| JP2878689B2 (en) | High voltage semiconductor device | |
| US4884116A (en) | Double diffused mosfet with potential biases | |
| JP3432708B2 (en) | Semiconductor devices and semiconductor modules | |
| JP4837939B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
| JP3028061B2 (en) | SOI structure semiconductor device and semiconductor gate array | |
| JP2004014707A (en) | Semiconductor device | |
| JPS6064481A (en) | Semiconductor device | |
| EP0596414B1 (en) | Semiconductor integrated circuit device comprising a dielectric isolation structure | |
| JP3311166B2 (en) | Insulated gate semiconductor device | |
| JP4029549B2 (en) | Semiconductor device | |
| JP2005026434A (en) | Semiconductor device | |
| JP2860089B2 (en) | High voltage semiconductor device | |
| US6002158A (en) | High breakdown-voltage diode with electric-field relaxation region | |
| JP3217552B2 (en) | Horizontal high voltage semiconductor device | |
| JPS639670B2 (en) | ||
| JPS6112069A (en) | Semiconductor device | |
| JP2782758B2 (en) | Semiconductor integrated circuit | |
| JP2774220B2 (en) | Semiconductor device | |
| JPH05326844A (en) | Semiconductor integrated circuit |