JPS639670B2 - - Google Patents
Info
- Publication number
- JPS639670B2 JPS639670B2 JP2663880A JP2663880A JPS639670B2 JP S639670 B2 JPS639670 B2 JP S639670B2 JP 2663880 A JP2663880 A JP 2663880A JP 2663880 A JP2663880 A JP 2663880A JP S639670 B2 JPS639670 B2 JP S639670B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- main
- semiconductor substrate
- current collecting
- base layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 23
- 238000002161 passivation Methods 0.000 claims description 23
- 230000000903 blocking effect Effects 0.000 description 20
- 239000012535 impurity Substances 0.000 description 17
- 150000002500 ions Chemical class 0.000 description 17
- 230000005684 electric field Effects 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 230000002093 peripheral effect Effects 0.000 description 7
- 230000006866 deterioration Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 239000007858 starting material Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- -1 water Chemical class 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に係り、特に安定な阻止特
性を有する大電力用高耐圧半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a high-power, high-voltage semiconductor device having stable blocking characteristics.
サイリスタは3個以上のpn接合を有し、電気
的、光学的等のトリガ手段により電流阻止状態か
ら導通状態への切換え、また電気的手段によりそ
の逆の切換えを行うことのできる半導体装置であ
る。 A thyristor is a semiconductor device that has three or more pn junctions and can be switched from a current blocking state to a conducting state by electrical or optical triggering means, and vice versa by electrical means. .
その一典型を図面により説明する。 A typical example will be explained with reference to the drawings.
一般的な製法に習つて出発素材の半導体ウエハ
の導電型をn型としたpnpn構造のサイリスタに
ついて説明する。 A thyristor with a pnpn structure in which the conductivity type of the semiconductor wafer as a starting material is n-type will be explained based on a general manufacturing method.
第1図において、半導体基体10はその一方の
主表面101に露出するp型エミツタpE層1、p
型エミツタ層1に隣接するn型ベースnB層2、n
型ベース層2に隣接しp型ベースpB層3と共に半
導体基体10の他方の主表面102に露出するn
型エミツタnE層4から構成されている。p型エミ
ツタ層1とn型ベース層2との間、n型ベース層
2とp型ベース層3との間およびp型ベース層3
とn型エミツタ層4との間にはそれぞれpn接合
J1,J2,J3が形成され、J1およびJ2は半導体基体
10の側面103に、J3は他の主表面102に終
端している。半導体基体10の一方の主表面10
1上、他方の主表面102上でp型ベース層3の
露出部の一部にはそれぞれ主電極であるアノード
電極5、カソード電極6、および制御電極7が形
成されている。アノード電極5は脆弱な半導体ウ
エハの保護をも兼ねる。さらに、nエミツタ層4
とpベース層3との間のpn接合J3は領域41にお
いて部分的にカソード電極6によつて短絡されて
シヨート・エミツタ構造がとられており、カソー
ド電極6の最外周はpベース層3に短絡されるよ
うに領域42において周辺短絡構造となつてい
る。従つて半導体基体10の端部領域400は
pnp構造となつている。 In FIG. 1, a semiconductor substrate 10 has p-type emitter layers 1 and 1 exposed on one main surface 101 thereof.
n-type base n B layer 2, n adjacent to type emitter layer 1
n adjacent to type base layer 2 and exposed on the other main surface 102 of semiconductor substrate 10 together with p-type base layer 3
It consists of a type emitter n E layer 4. Between the p-type emitter layer 1 and the n-type base layer 2, between the n-type base layer 2 and the p-type base layer 3, and the p-type base layer 3
and the n-type emitter layer 4, there is a p-n junction, respectively.
J 1 , J 2 , and J 3 are formed, with J 1 and J 2 terminating at the side surface 103 of the semiconductor body 10 and J 3 terminating at the other main surface 102 . One main surface 10 of semiconductor substrate 10
An anode electrode 5, a cathode electrode 6, and a control electrode 7, which are main electrodes, are formed on exposed portions of the p-type base layer 3 on the upper and other main surfaces 102, respectively. The anode electrode 5 also serves to protect the fragile semiconductor wafer. Furthermore, the n emitter layer 4
The p-n junction J 3 between the p-base layer 3 and the p-base layer 3 is partially short-circuited by the cathode electrode 6 in a region 41 to have a short-emitter structure, and the outermost periphery of the cathode electrode 6 is connected to the p-base layer 3. A peripheral short-circuit structure is provided in the region 42 so as to be short-circuited. The end region 400 of the semiconductor body 10 is therefore
It has a pnp structure.
シヨート・エミツタ構造および周辺短絡構造は
いずれもサイリスタの阻止特性を向上するための
公知技術である。ここでサイリスタの阻止特性と
は、アノード電極5とカソード電極6との間に電
圧を印加したとき、J1またはJ2接合が逆バイアス
状態(これを阻止状態という。)になり、このと
きどれだけ高い電圧を出来るだけ少ないもれ電流
で阻止できうるかの能力をいう。半導体基体10
の内部で高い電圧を阻止することができても、表
面での阻止能力は内部より劣るのが通常である。
これは表面での電界強度が内部に比べて高くな
り、そのため雪崩破壊がおこるためである。これ
を除去するためには表面電界強度を内部に比べて
低くすることが必要である。表面電界強度を下げ
るためには表面での空乏層のひろがりを大きくす
ることで達成できる。 Short-emitter structures and peripheral short-circuit structures are both known techniques for improving the blocking characteristics of thyristors. Here, the blocking characteristic of a thyristor means that when a voltage is applied between the anode electrode 5 and the cathode electrode 6, the J 1 or J 2 junction becomes a reverse bias state (this is called a blocking state). The ability to block a voltage as high as possible with as little leakage current as possible. Semiconductor substrate 10
Even if it is possible to block high voltages inside, the blocking ability at the surface is usually inferior to that inside.
This is because the electric field strength at the surface is higher than that inside, which causes avalanche destruction. In order to eliminate this, it is necessary to lower the surface electric field strength compared to the inside. Lowering the surface electric field strength can be achieved by increasing the spread of the depletion layer at the surface.
このため従来では、半導体基体10の端部側面
103を例えば、2段ベベル形状、Σ字形状など
各種形状に加工することが行われていた。しか
し、J1,J2接合が端部側面103に露出されてい
るため、外部よりの汚染、不純物イオンなどの付
着を防ぐために表面安定化膜200(以下、これ
をパツシベーシヨン材と呼ぶ。)が塗布されなけ
ればならなかつた。ところが、これまでのサイリ
スタでは以下に述べる問題点がある。 For this reason, conventionally, the end side surface 103 of the semiconductor substrate 10 has been processed into various shapes, such as a two-step bevel shape and a Σ-shape. However, since the J 1 and J 2 junctions are exposed on the end side surface 103, a surface stabilizing film 200 (hereinafter referred to as a passivation material) is used to prevent contamination from the outside and adhesion of impurity ions. It had to be painted. However, conventional thyristors have the following problems.
サイリスタでは高い阻止電圧が印加されその状
態が長時間維持された場合、もれ電流が異常に増
大し阻止特性が著しく劣化し、最悪の事態では熱
暴走してサイリスタが破壊する。 When a high blocking voltage is applied to a thyristor and this state is maintained for a long time, leakage current increases abnormally, the blocking characteristics deteriorate significantly, and in the worst case scenario, thermal runaway occurs and the thyristor is destroyed.
かかる問題点について従来は半導体基体内部の
現象ではなく、パツシベーシヨン材に関連して半
導体10の端部側面に起因する問題として考える
ことが一般に受け入れられている。このため、パ
ツシベーシヨン材の材質自体の検討および端部側
面の化学的処理方法の検討などがなされ、その成
果の一部が提案されている。 Conventionally, it has been generally accepted that such a problem is not a phenomenon inside the semiconductor substrate, but is a problem caused by the side surface of the end portion of the semiconductor 10 in connection with the passivation material. For this reason, studies have been made on the material itself of the passivation material and on chemical treatment methods for the end and side surfaces, and some of the results have been proposed.
しかし、劣化原因の具体的なモデルおよび解決
案については第1図に例示された実装置に近い構
造で詳細に調べて提出されるまでには至らず、し
かもパツシベーシヨン材の材質および製造プロセ
スの観点から離れて構造の面から上記問題点を解
決した半導体装置はこれまで存在しなかつた。 However, a detailed model of the causes of deterioration and a proposed solution have not yet been submitted after detailed investigation using a structure similar to the actual device illustrated in Figure 1. Until now, there has been no semiconductor device that has solved the above problems apart from the structure.
本発明の目的は、上述した従来の欠点を除去
し、具体的に言えば阻止電圧が長期にわたり印加
されても、もれ電流が増大することなく、信頼性
の高い阻止能力を有する半導体装置を提供するこ
とである。 An object of the present invention is to eliminate the above-mentioned conventional drawbacks, and specifically, to provide a semiconductor device that has a highly reliable blocking ability without increasing leakage current even when a blocking voltage is applied for a long period of time. It is to provide.
上記目的を達成する本発明半導体装置の特徴と
するところは、少なくとも1個のpn接合が半導
体基体の側面に露出しており、半導体基体の一方
の主表面に第1の主電極を低抵抗接触させてお
り、上記半導体基体の他方の主表面に第2の主電
極を低抵抗接触させているものにおいて、上記半
導体基体の一方の主表面側に、この主表面の周縁
より突出しかつ上記第1の主電極と電気的に接続
された第1の集電電極を設け、上記半導体基体の
他方の主表面側に、この主表面の周縁より突出し
かつ上記第2の主電極と電気的に接続された第2
の集電電極を設け、上記第1の集電電極から上記
第2の集電電極にかけて上記側面を覆うようにパ
ツシベーシヨン材を設けていることにある。 The semiconductor device of the present invention that achieves the above object is characterized in that at least one pn junction is exposed on the side surface of the semiconductor substrate, and the first main electrode is connected to one main surface of the semiconductor substrate with low resistance. and a second main electrode is in low resistance contact with the other main surface of the semiconductor substrate, the first main electrode protruding from the periphery of this main surface on the one main surface side of the semiconductor substrate. A first current collecting electrode electrically connected to the main electrode is provided on the other main surface side of the semiconductor substrate, protruding from the periphery of this main surface and electrically connected to the second main electrode. second
A current collecting electrode is provided, and a passivation material is provided so as to cover the side surface from the first current collecting electrode to the second current collecting electrode.
上記第1、第2の集電電極を具備することによ
つて、阻止電圧が印加された時、パツシベーシヨ
ン材中に作用する電界によりパツシベーシヨン材
中の不純物イオンが上記第1、第2の集電電極あ
るいは第1、第2の主電極にドリフトされ、半導
体基体の表面に蓄積されることを防ぎ、これらの
不純物イオンを集電電極へ集める新規な構造およ
び効果を具備したことで、半導体層表面の空乏化
又はn型反転に基づくもれ電流の異常増大が解消
され安定かつ信頼性の高い阻止特性を有する半導
体装置が実現できる。 By providing the first and second current collecting electrodes, when a blocking voltage is applied, impurity ions in the passivation material are absorbed by the electric field acting in the passivation material to the first and second current collecting electrodes. By having a new structure and effect that prevents impurity ions from drifting to the electrode or the first and second main electrodes and accumulating on the surface of the semiconductor substrate, and collecting these impurity ions to the current collecting electrode, the semiconductor layer surface The abnormal increase in leakage current due to depletion or n-type inversion is eliminated, and a semiconductor device having stable and reliable blocking characteristics can be realized.
以下本発明を更に詳細に説明する。 The present invention will be explained in more detail below.
本発明の目的は既に前記した如く阻止状態にお
けるもれ電流が変動することなく安定な阻止特性
を有する半導体装置を実現することにある。かか
る目的を達成する為の第1段階として、本発明者
等は阻止特性の劣化現象を第1図に例示した従来
構造のサイリスタについて詳細に検討した。その
結果劣化現象が半導体基体内部の問題ではなく、
その端部側面に塗布されているパツシベーシヨン
材の中に散在する不純物イオンに起因したもので
あることが判つた。つまり、パツシベーシヨン材
中には水分、ナトリウムイオン、電解によつて解
離生成されたイオン等決して除去できない不純物
イオンが微量散在する。阻止電圧が印加されると
パツシベーシヨン材の中に電界が生じる。不純物
イオンはこの電界により移動させられて、電界つ
まり電気力線が終端する領域に多量に蓄積される
様になる。 As described above, an object of the present invention is to realize a semiconductor device having stable blocking characteristics without fluctuations in leakage current in the blocking state. As a first step toward achieving this objective, the present inventors conducted a detailed study on the phenomenon of deterioration of blocking characteristics of a thyristor having a conventional structure as illustrated in FIG. As a result, the deterioration phenomenon is not a problem inside the semiconductor substrate,
It was found that this was caused by impurity ions scattered in the passivation material applied to the side surface of the end. In other words, trace amounts of impurity ions, such as water, sodium ions, and ions dissociated and produced by electrolysis, are scattered in the passivation material, and can never be removed. When a blocking voltage is applied, an electric field is created within the passivation material. The impurity ions are moved by this electric field and are accumulated in large quantities in the region where the electric field, that is, the lines of electric force terminate.
ここで実際のサイリスタについて見られる現象
を具体的にとりあげて説明する。 Here, we will specifically discuss the phenomena observed in actual thyristors.
第2図は上記現象をより詳しく説明するために
第1図に示す従来装置の周辺部分のみ拡大して示
したものである。ただし第1図と同じ部分は同じ
符号で示してある。また、サイリスタは順方向阻
止状態つまりアノード電極5が正に、カソード電
極6が負になる極性で主電極5,6間に電圧が印
加されている状態を示している。 FIG. 2 is an enlarged view of only the peripheral portion of the conventional device shown in FIG. 1 in order to explain the above phenomenon in more detail. However, the same parts as in FIG. 1 are indicated by the same symbols. Further, the thyristor is shown in a forward blocking state, that is, a state in which a voltage is applied between the main electrodes 5 and 6 with the anode electrode 5 being positive and the cathode electrode 6 being negative.
図中のパツシベーシヨン材200中に示した点
線は電気力線30であり、不純物イオンはこの電
気力線に沿つて移動する。この電気力線について
さらに言及すれば、このサイリスタには本発明の
集電電極を設けていないため大部分のものがp型
ベース層3が露出されている端部側面およびその
表面の半導体層に終端する。その結果正の電荷を
有する不純物イオンが多数この表面に蓄積され
る。p型半導体層表面に正の電荷が偏析するとそ
の表面の正孔濃度が下がり空乏化さらにはn型に
反転することは公知である。 The dotted lines shown in the passivation material 200 in the figure are lines of electric force 30, and impurity ions move along these lines of electric force. Regarding these lines of electric force, since this thyristor is not provided with the current collecting electrode of the present invention, most of the lines of electric force are on the side surface of the end where the p-type base layer 3 is exposed and the semiconductor layer on the surface thereof. terminate. As a result, a large number of positively charged impurity ions are accumulated on this surface. It is known that when positive charges are segregated on the surface of a p-type semiconductor layer, the hole concentration on the surface decreases, resulting in depletion and further inversion to n-type.
サイリスタに印加されている阻止電圧が長時間
作用するとかかるp型ベース層3表面に蓄積され
る正電荷も順次その量を増しp型ベース層3表面
の空乏化、もしくはn型反転が進行し、終局的に
はn型エミツタ層4の上に設けられた第2の主電
極であるカソード電極6に到達してしまいこの領
域を通して異常に大きなもれ電流が流れることに
なる。図中のn型ベース層2とp型ベース層3に
示した一点鎖線は空乏層の領域を示したものでp
型ベース層3の表面では既に空乏化が進行してカ
ソード電極6に到達した状態が示されている。 When the blocking voltage applied to the thyristor acts for a long time, the amount of positive charges accumulated on the surface of the p-type base layer 3 gradually increases, and depletion of the surface of the p-type base layer 3 or n-type inversion progresses. Eventually, the leakage current reaches the cathode electrode 6, which is the second main electrode provided on the n-type emitter layer 4, and an abnormally large leakage current flows through this region. The dashed-dotted lines shown in the n-type base layer 2 and p-type base layer 3 in the figure indicate the depletion layer region.
It is shown that depletion has already progressed on the surface of the mold base layer 3 and has reached the cathode electrode 6.
以上の説明で明らかな様にここに従来のサイリ
スタで起る阻止特性の劣化はパツシベーシヨン材
中の不純物イオンが電界により移動してp型ベー
ス層3表面に蓄積され、表面が空乏化又はn型反
転することによつて起る現象であるという新しい
考え方を提示した。 As is clear from the above explanation, the deterioration of the blocking characteristics that occurs in conventional thyristors is caused by impurity ions in the passivation material being moved by the electric field and accumulated on the surface of the p-type base layer 3, causing the surface to become depleted or n-type. We proposed a new way of thinking that this phenomenon is caused by reversal.
この考え方によれば、劣化不良を解決する手段
としてp型ベース層3の表面に集まる不純物イオ
ン量を下げることが不可欠であることがわかる。
この点を達成する手段としては従来使用されてい
るパツシベーシヨン材料を改良もしくは新規なも
のとして不純物イオンの含有量を下げる方法もあ
るが、本発明はこれとは異なる解決手段を提示す
るものである。つまり、従来ではパツシベーシヨ
ン中の電気力線はほとんどp型ベース層3に終端
していた為に不純物イオンの大部分がそこに向つ
て蓄積されていたが、本発明では第4の電極であ
る集電電極を設けることでp型ベース層3表面に
蓄積される不純物イオンを新たな集電電極へ蓄積
させ、実質的にp型ベース層3表面の蓄積電荷量
を下げるので、その為にもれ電流は大幅に低減さ
れる。 According to this concept, it is understood that it is essential to reduce the amount of impurity ions that collect on the surface of the p-type base layer 3 as a means to solve the problem of poor deterioration.
As a means of achieving this point, there is a method of lowering the content of impurity ions by improving or creating a new passivation material that has been used in the past, but the present invention proposes a different solution. In other words, in the past, most of the electric lines of force during passivation terminated at the p-type base layer 3, and most of the impurity ions were accumulated there; By providing a current collecting electrode, the impurity ions accumulated on the surface of the p-type base layer 3 are accumulated in a new current-collecting electrode, and the amount of accumulated charge on the surface of the p-type base layer 3 is substantially lowered, thereby preventing leakage. Current is significantly reduced.
また、本発明の背景には以下に示す実験結果の
解析がある。 Further, the background of the present invention is the analysis of experimental results shown below.
第3図a,bは実験試料の形状であり、第4図
はその結果である。 Figures 3a and 3b show the shapes of experimental samples, and Figure 4 shows the results.
pnp構造の半導体基体10の対向する1対の表
面に主電極5,6を設けている。(a)は一方主電極
6がW板より形成され隣接するp型半導体層より
1.5mm突起した構造で設けられている。(b)は両主
電極5,6ともにアルミニウムを蒸着して形成し
たものである。そして、主電極6は(a)とは逆に、
隣接するp型半導体層より1.5mmだけ退行してい
る。 Main electrodes 5 and 6 are provided on a pair of opposing surfaces of a semiconductor substrate 10 having a pnp structure. In (a), the main electrode 6 is formed from a W plate and is connected to the adjacent p-type semiconductor layer.
It is provided with a 1.5mm protruding structure. In (b), both main electrodes 5 and 6 are formed by vapor-depositing aluminum. And, contrary to (a), the main electrode 6 is
It is regressed by 1.5 mm from the adjacent p-type semiconductor layer.
第4図は第3図に示した極性で3000Vの直流電
圧を印加した時に流れるもれ電流の経時変化であ
る。曲線Aは第3図(a)の測定結果を、また曲線B
は第3図(b)の測定結果を示している。曲線Aは曲
線Bに比べてもれ電流の増加が少ないことがわか
る。 FIG. 4 shows the change over time in the leakage current that flows when a DC voltage of 3000 V is applied with the polarity shown in FIG. 3. Curve A shows the measurement results in Figure 3(a), and curve B
shows the measurement results in Figure 3(b). It can be seen that curve A has a smaller increase in leakage current than curve B.
この実験結果を詳細に検討することにより、(a)
の試料では主電極であるW板6が同時に本発明の
集電電極としての作用を本質的に兼ねそなえたも
のであり、(b)の試料における主電極6にはこの作
用がなく、単なる電極にすぎないものであるとい
うことが理解されよう。 By examining the experimental results in detail, we found that (a)
In the sample shown in (b), the W plate 6, which is the main electrode, essentially also functions as the current collecting electrode of the present invention, whereas the main electrode 6 in the sample shown in (b) does not have this function, and is simply an electrode. It will be understood that it is nothing more than
第5図は本発明の一実施例である。 FIG. 5 shows an embodiment of the present invention.
抵抗率200〜300Ω−cm、厚さ約1mmのn型シリ
コン単結晶を出発素材として公知の拡散技術によ
りガリウム、アルミニウム等のp型不純物を拡散
しp型拡散層を形成する。一方の拡散層の表面を
化学エツチング法により一様に深さ方向に40〜
50μmほど除去し厚さ調整する。エツチング除去
によつて薄くなつたp型層はp型ベース層3とな
り、これと反対側の他方の主表面101に隣接す
る厚いp型層はp型エミツタ層1となり、それら
の間にはさまれたn型層はn型ベース層2であ
る。次いで、例えばPoCl3を拡散源とした燐拡散
技術および化学エツチング技術を用いてp型ベー
ス層3に隣接したn型エミツタ層4を形成する。
ただし、n型エミツタ層4内部の部分的領域では
p型ベース層3が表面102に露出している。相
対向する主表面101,102に隣接してp型エ
ミツタ層1にはアノード電極5が、n型エミツタ
層4にはカソード電極6が、主表面102に露出
したp型ベース層3の一部には制御電極7がそれ
ぞれ形成され、しかも、カソード電極6は部分的
にp型ベース層3とn型エミツタ層4とを図中4
1で示される領域で短絡されたいわゆるシヨー
ト・エミツタ構造である。 Using an n-type silicon single crystal with a resistivity of 200 to 300 Ω-cm and a thickness of about 1 mm as a starting material, a p-type impurity such as gallium or aluminum is diffused using a known diffusion technique to form a p-type diffusion layer. The surface of one diffusion layer is uniformly etched in the depth direction by chemical etching.
Remove about 50μm and adjust the thickness. The p-type layer thinned by etching removal becomes the p-type base layer 3, and the thick p-type layer adjacent to the other main surface 101 on the opposite side becomes the p-type emitter layer 1, sandwiched between them. The removed n-type layer is an n-type base layer 2. Next, an n-type emitter layer 4 adjacent to the p-type base layer 3 is formed using, for example, a phosphorus diffusion technique and a chemical etching technique using PoCl 3 as a diffusion source.
However, in a partial region inside the n-type emitter layer 4, the p-type base layer 3 is exposed to the surface 102. Adjacent to the opposing main surfaces 101 and 102, the p-type emitter layer 1 has an anode electrode 5, the n-type emitter layer 4 has a cathode electrode 6, and a part of the p-type base layer 3 exposed on the main surface 102. A control electrode 7 is formed in each of the regions, and the cathode electrode 6 partially connects the p-type base layer 3 and the n-type emitter layer 4 to 4 in the figure.
This is a so-called short emitter structure in which the region indicated by 1 is short-circuited.
本実施例では、アノード電極5、カソード電極
6、制御電極7は一般に使われているアルミニウ
ムを蒸着して形成した。上記電極が形成された半
導体基体10の両主表面101,102は可滑動
面であり、両面は機械的な圧接により電気的およ
び熱的なコンタクトがとられ、平型パツケージ内
に密封されて組み立てられる。pn接合J1およびJ2
が露出する端部側面103は両pn接合がともに
正ベベルとなるΣ字形状に加工処理されている。
また、半導体基体10の主表面101における端
部領域300ではp型エミツタ層1が表面に露出
しており、半導体基体10の主表面102におけ
る端部領域400ではp型ベース層3が表面に露
出しており、それぞれpnp構造となつている。上
記端部領域300に隣接して本発明の集電電極8
を設け、上記端部領域400に隣接して集電電極
9を設ける。集電電極8,9は両主表面より突出
して全周を覆うリング状のものとし、その材質は
タングステンとした。しかし、タングステンに限
定する必要はなく、以下で記述するパツシベーシ
ヨン材200と化学的に反応せず、腐食すること
のない電気的な良導体であることが大切である。
なお、集電電極8,9は半導体基体10の主表面
101,102の周端より1.0mm以上突出させた。 In this example, the anode electrode 5, cathode electrode 6, and control electrode 7 were formed by vapor-depositing aluminum, which is commonly used. Both main surfaces 101 and 102 of the semiconductor substrate 10 on which the electrodes are formed are sliding surfaces, and both surfaces are electrically and thermally contacted by mechanical pressure welding, and assembled by being sealed in a flat package. It will be done. p-n junction J 1 and J 2
The end side surface 103 where is exposed is processed into a Σ-shape in which both pn junctions have positive bevels.
Further, in an end region 300 on the main surface 101 of the semiconductor substrate 10, the p-type emitter layer 1 is exposed on the surface, and in an end region 400 on the main surface 102 of the semiconductor substrate 10, the p-type base layer 3 is exposed on the surface. Each of them has a pnp structure. The current collecting electrode 8 of the present invention is adjacent to the end region 300.
, and a current collecting electrode 9 is provided adjacent to the end region 400 . The current collecting electrodes 8 and 9 were ring-shaped which protruded from both main surfaces and covered the entire circumference, and were made of tungsten. However, it is not necessary to limit it to tungsten, and it is important that it is a good electrical conductor that does not chemically react with the passivation material 200 described below and does not corrode.
Note that the current collecting electrodes 8 and 9 were made to protrude from the peripheral edges of the main surfaces 101 and 102 of the semiconductor substrate 10 by 1.0 mm or more.
さらに、集電電極8,9はそれぞれアノード電
極5、カソード電極6とほぼ同じ電位となる様に
オーミツクコンタクトが得られている。 Furthermore, ohmic contact is obtained so that the current collecting electrodes 8 and 9 have approximately the same potential as the anode electrode 5 and the cathode electrode 6, respectively.
本発明者等は集電電極8とアノード電極5が、
集電電極9とカソード電極6が、それぞれ接触さ
れているだけの簡単な構造でも充分その効果が達
成されることを確認した。 The present inventors have discovered that the current collecting electrode 8 and the anode electrode 5 are
It has been confirmed that the effect can be sufficiently achieved even with a simple structure in which the current collecting electrode 9 and the cathode electrode 6 are in contact with each other.
端部側面の表面保護を目的としその周辺を囲む
様にパツシベーシヨン材200が厚く塗布されて
いる。本実施例では集電電極8,9は上記パツシ
ベーシヨン材中にほとんど埋設されて設置されて
いるが、設置条件としては少なくとも集電電極
8,9の一部がそれぞれ埋設される点が達成され
ていれば充分である。また、パツシベーシヨン材
200は電力用サイリスタで一般に実用化されて
いるシリコーン・ゴム系の有機材料を用いた。 For the purpose of protecting the surface of the side surface of the end portion, a passivation material 200 is thickly applied to surround the periphery thereof. In this embodiment, the current collecting electrodes 8 and 9 are installed almost completely buried in the above-mentioned passivation material, but the installation condition is such that at least a part of each of the current collecting electrodes 8 and 9 is buried. It is sufficient. Further, as the passivation material 200, a silicone/rubber-based organic material, which is generally put into practical use in power thyristors, is used.
第6図は集電電極8,9の作用を説明するため
の図であり、理解を助けるために第5図に示す半
導体基体10の端部を拡大して示した。但し、半
導体基体の両表面の端部領域に設けられた一対の
集電電極8,9はそれぞれ同じ効果を持つので、
カソード側に設けた集電電極9について説明す
る。アノード側の集電電極8の作用効果は、半導
体基体に印加される電圧の極性が反対である以外
は本質的な差はない。パツシベーシヨン材200
中に点線で示した線は電気力線30を示してい
る。 FIG. 6 is a diagram for explaining the function of the current collecting electrodes 8 and 9, and the end portion of the semiconductor substrate 10 shown in FIG. 5 is shown in an enlarged manner for easier understanding. However, since the pair of current collecting electrodes 8 and 9 provided at the end regions of both surfaces of the semiconductor substrate each have the same effect,
The current collecting electrode 9 provided on the cathode side will be explained. There is no essential difference in the operation and effect of the current collecting electrode 8 on the anode side except that the polarity of the voltage applied to the semiconductor substrate is opposite. Passivation material 200
The dotted lines inside indicate the lines of electric force 30.
図中の極性で電圧を印加すると第2図の従来構
造ではパツシベーシヨン材中を延びる電気力線が
p型ベース層3の表面に集中して終端していたの
に比べて、本実施例に示すサイリスタはp型ベー
ス層3へ集まる電気力線は少なくなり、集電電極
9に終端する電気力線が新たに生じている。こう
した状況ではパツシベーシヨン材200中に散在
する不純物イオンの大部分は集電電極9へ向かう
力を受け、図中に印で示すように集電電極9に
蓄積される。尚、図中の一点鎖線はpn接合J2の両
側の空乏層を示している。 When a voltage is applied with the polarity shown in the figure, the electric lines of force extending through the passivation material are concentrated on the surface of the p-type base layer 3 and terminate in the conventional structure shown in FIG. In the thyristor, fewer lines of electric force are gathered to the p-type base layer 3, and new lines of electric force are generated that terminate at the current collecting electrode 9. In such a situation, most of the impurity ions scattered in the passivation material 200 receive a force directed toward the current collecting electrode 9, and are accumulated on the current collecting electrode 9 as indicated by marks in the figure. Note that the dashed-dotted lines in the figure indicate the depletion layers on both sides of the pn junction J2 .
また、第1図に示されている従来のサイリスタ
では、アノード電極5としてタングクスンまたは
モリブデン板等の金属部材を半導体基体10に接
着させているため、両者の熱膨張係数の違いによ
つて接着時にわん曲が生じてしまう。このわん曲
のために、熱的および電気的コンタクトがとり難
くなり、熱抵抗の増大、順方向電圧降下(FVD
と一般に呼ぶ)の増大という好ましからぬ影響を
与えている。しかし、第5図に示す本実施例にお
いては、アノード電極5としてタングステン板の
様な金属部材を接着して設けるのではなく、カソ
ード電極6と同様に半導体基体10の主表面10
1にアルミニウムを蒸着して形成するだけの構造
となつているので、熱膨張係数の違いによるわん
曲の問題が無くなり、可滑動面での電気的および
熱的コンタクトがとり易くなつている。 In addition, in the conventional thyristor shown in FIG. 1, a metal member such as tungsten or molybdenum plate is bonded to the semiconductor substrate 10 as the anode electrode 5, and therefore, due to the difference in thermal expansion coefficient between the two, there may be problems during bonding. A curve will occur. This curvature makes it difficult to make thermal and electrical contact, increases thermal resistance, and forward voltage drop (FVD).
This has the undesirable effect of increasing the However, in this embodiment shown in FIG. 5, the anode electrode 5 is not provided by adhering a metal member such as a tungsten plate, but instead is provided on the main surface 10 of the semiconductor substrate 10 in the same way as the cathode electrode 6.
Since the structure is formed by simply vapor depositing aluminum on the surface of the surface of the surface, there is no problem of curvature due to differences in thermal expansion coefficients, and it is easy to make electrical and thermal contact on the sliding surface.
第7図は、本発明の他の実施例である。 FIG. 7 shows another embodiment of the invention.
第5図に示す実施例がJ1およびJ2接合ともに正
ベベルとなるΣ字形状を持つのに対して、本実施
例は両pn接合が共に負ベベルとなる凸型形状の
サイリスタについての実施例である。第7図にお
いて第5図と同一符号は同一物、相当物を示して
いる。さらに本発明が適用できる端部形状は、Σ
字形状、凸型形状のものに限定する必要はなく、
如何なる形状に対しても適用できうる。 While the embodiment shown in FIG. 5 has a Σ-shape in which both J 1 and J 2 junctions have positive bevels, this embodiment is a convex-shaped thyristor in which both pn junctions have negative bevels. This is an example. In FIG. 7, the same reference numerals as in FIG. 5 indicate the same or equivalent parts. Furthermore, the end shape to which the present invention can be applied is Σ
There is no need to limit it to a letter-shaped or convex shape.
It can be applied to any shape.
また、両実施例に示したサイリスタばかりでな
くダイオード、トランジスタ、逆導通サイリス
タ、双方向サイリスタなど各積の半導体装置に適
用できうるものである。 Furthermore, the invention can be applied not only to the thyristors shown in both embodiments, but also to semiconductor devices of various types, such as diodes, transistors, reverse conduction thyristors, and bidirectional thyristors.
また、パツシベーシヨン材としては、有機材料
だけでなく、無機材料、例えばガラスなども適用
できうるものである。 In addition, not only organic materials but also inorganic materials such as glass can be used as the passivation material.
本発明によれば、例えば3KVはら6KVという
高い電圧を阻止した状態が長時間持続されても、
半導体層表面へ蓄積される不純物イオン量は少な
く、従つてもれ電流が増加することもなく、極め
て安定な阻止特性を有する新規な集電電極付き半
導体装置を得ることができる。 According to the present invention, even if a state in which a high voltage such as 3KV to 6KV is blocked for a long time,
The amount of impurity ions accumulated on the surface of the semiconductor layer is small, so there is no increase in leakage current, and a novel semiconductor device with a current collecting electrode having extremely stable blocking characteristics can be obtained.
第1図は従来のサイリスタを示す断面図、第2
図は第1図に示すサイリスタの周辺部分を拡大し
た部分断面図、第3図、第4図は本発明を得る過
程で検討した実験の試料とその結果を示す図、第
5図は本発明の一実施例を示すサイリスタの断面
図、第6図は集電電極の作用を説明するための第
5図に示すサイリスタの周辺部分を拡大した部分
断面図、第7図は本発明の他の実施例を示すサイ
リスタの周辺部分を拡大した部分断面図である。
1……p型エミツタ層、2……n型ベース層、
3……p型ベース層、4……n型エミツタ層、5
……アノード電極、6……カソード電極、7……
制御電極、8,9……集電電極、10……半導体
基体、200……パツシベーシヨン材、300,
400……端部領域、30……電気力線。
Figure 1 is a sectional view showing a conventional thyristor, Figure 2 is a sectional view showing a conventional thyristor.
The figure is an enlarged partial sectional view of the peripheral part of the thyristor shown in Figure 1, Figures 3 and 4 are diagrams showing samples and results of experiments studied in the process of obtaining the present invention, and Figure 5 is a diagram showing the invention of the present invention. A cross-sectional view of a thyristor showing one embodiment, FIG. 6 is a partial cross-sectional view enlarging the peripheral part of the thyristor shown in FIG. 5 for explaining the action of the current collecting electrode, and FIG. FIG. 2 is an enlarged partial cross-sectional view of a peripheral portion of a thyristor showing an example. 1... p-type emitter layer, 2... n-type base layer,
3...p-type base layer, 4...n-type emitter layer, 5
... Anode electrode, 6 ... Cathode electrode, 7 ...
Control electrode, 8, 9... Current collecting electrode, 10... Semiconductor substrate, 200... Passivation material, 300,
400... End region, 30... Lines of electric force.
Claims (1)
面に露出しており、半導体基体の一方の主表面に
第1の主電極を低抵抗接触させており、上記半導
体基体の他方の主表面に第2の主電極を低抵抗接
触させているものにおいて、上記半導体基体の一
方の主表面側に、この主表面の周縁より突出しか
つ、上記第1の主電極と電気的に接続された第1
の集電電極を設け、上記半導体基体の他方の主表
面側に、この主表面の周縁より突出しかつ上記第
2の主電極と電気的に接続された第2の集電電極
を設け、上記第1の集電電極から上記第2の集電
電極にかけて上記側面を覆うようにパツシベーシ
ヨン材を設けていることを特徴とする半導体装
置。1 At least one pn junction is exposed on the side surface of the semiconductor substrate, a first main electrode is in low resistance contact with one main surface of the semiconductor substrate, and a second main electrode is in low resistance contact with the other main surface of the semiconductor substrate. in which the main electrodes of the semiconductor substrate are in low-resistance contact, the first main electrode protruding from the periphery of the main surface and electrically connected to the first main electrode on one main surface side of the semiconductor substrate.
A second current collecting electrode is provided on the other main surface side of the semiconductor substrate, protruding from the periphery of this main surface and electrically connected to the second main electrode, A semiconductor device characterized in that a passivation material is provided so as to cover the side surface from the first current collecting electrode to the second current collecting electrode.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2663880A JPS56124263A (en) | 1980-03-05 | 1980-03-05 | Semiconductor device |
US06/164,946 US4388635A (en) | 1979-07-02 | 1980-07-01 | High breakdown voltage semiconductor device |
DE3024939A DE3024939C3 (en) | 1979-07-02 | 1980-07-01 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2663880A JPS56124263A (en) | 1980-03-05 | 1980-03-05 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56124263A JPS56124263A (en) | 1981-09-29 |
JPS639670B2 true JPS639670B2 (en) | 1988-03-01 |
Family
ID=12198982
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2663880A Granted JPS56124263A (en) | 1979-07-02 | 1980-03-05 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56124263A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH076841U (en) * | 1993-06-23 | 1995-01-31 | 株式会社三協精機製作所 | Magnetic / IC dual card reader |
US11114054B2 (en) | 2009-03-26 | 2021-09-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59162354A (en) * | 1983-03-08 | 1984-09-13 | Nissan Motor Co Ltd | Fuel filter |
-
1980
- 1980-03-05 JP JP2663880A patent/JPS56124263A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH076841U (en) * | 1993-06-23 | 1995-01-31 | 株式会社三協精機製作所 | Magnetic / IC dual card reader |
US11114054B2 (en) | 2009-03-26 | 2021-09-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS56124263A (en) | 1981-09-29 |
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