JPS63126243A - Integrated circuit element and manufacture thereof - Google Patents

Abstract

PURPOSE:To dissolved an interelement parasitic effect and to lessen a collector resistance by a method wherein an island region isolated completely by a dielectric is provided on a composite semiconductor substrate and a high-concentration semiconductor layer is provided on the side surfaces and bottom surface of the island region. CONSTITUTION:An oxide layer 2 and an undoped poly Si layer 3 are formed on the surface of a P-type semiconductor substrate 1 and after As ions are implanted, an N-type Si semiconductor substrate 4 is bonded on the poly Si layer 3 to obtain a composite semiconductor substrate 5. Then, after the surface of the N-type substrate 4 is polished, an Si oxide layer 6 and a nitride oxide layer 7 are formed and thereafter, an Si oxide layer 8 is formed by a CVD method. Then, a trench pattern 9 surrounding an element forming region is formed to isolate an island region 10 and an As doped poly Si layer 12 is formed on the outside of the trench 9. Then, the interior of the trench is filled with an oxide film 13 and a poly Si layer 14. A transistor consisting of a base 15, an emitter 17 and so on is formed in the island region 10 formed by isolation in such a way.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to element isolation of integrated circuits, and is particularly suitable for high-speed and high-voltage bipolar integrated circuit elements.

(Prior art) Conventionally, collector junctions of diodes, bipolar transistors, etc., drain junctions of double-diffused MO8FETs, etc. have been used with the PN junction in a reverse bias state, and in order to reduce the series resistance generated at that time. Adopting a laminated structure with an N''' semiconductor substrate based on an N,000 semiconductor substrate, this N
- Semiconductor elements are provided by introducing impurities of opposite conductivity type into a semiconductor substrate, and the underlying semiconductor substrate is sufficiently thick to improve breakdown voltage and mechanical strength. Moreover, the bottom of the PN junction obtained by introducing this impurity and the N
"Reach Through" due to the depletion layer generated during this PN junction operation by keeping a sufficient distance to the semiconductor substrate.
It is common practice to prevent the breakdown phenomenon caused by ``h''.

The so-called epitaxial growth method is used to achieve this layered structure, but if there is a difference in the concentration of impurities contained in the underlying semiconductor substrate, out-diffusion (out-diffusion) of the impurities contained in the underlying semiconductor substrate occurs.
The reality is that strict concentration control not only at the boundary portion cannot be achieved due to Diffusion.

However, a bonding technique has already been developed that integrates these semiconductor substrates regardless of the difference in conductivity type due to the difference in concentration of impurities contained therein. In other words, this is a technique that allows the mirror surfaces of semi-moist semiconductor substrates to be brought into close contact with each other to obtain a composite semiconductor substrate that has sufficient mechanical strength and can be handled as a single semiconductor substrate.

It is assumed that something slightly different from the original (bulk) crystal will be formed on this adhesion surface, but it will not become a thermal or electrical barrier, and the functional element using the PN junction formed at the knee will have the necessary electrical properties. It can be applied to not only silicon semiconductor substrates but also silicon oxide layers and polycrystalline silicon layers.

On the other hand, bipolar type integration times lol! In order to keep the junction capacitance of bipolar transistors low, a bipolar transistor is required to have a structure with an extremely fine depth dimension as well as a planar pattern. In particular, the junction capacitance between the transistor collector and the semiconductor substrate is a major focus, and one way to reduce it is by using trench isolation (which does not rely on PN junctions for isolation between elements).
Trench Isolation) is in the spotlight. Specifically, a deep and narrow groove is provided, the side walls of the groove are oxidized, and polycrystalline silicon is filled into the groove to flatten the groove.

FIG. 2 shows a sectional view of essential parts of a bipolar integrated circuit element. In manufacturing this device, a P-type (100) Si semiconductor substrate 30 is prepared, an n-type buried layer 31 is formed on its surface, an n-epitaxial layer 32 is deposited by a conventional method, and then thermally oxidized by a conventional method. Layer 33 is coated and a further CVD silicon oxide layer 34 is deposited. Next, a small groove penetrating the thermal oxidation layer 33 and the CVD silicon oxide layer 34 located around the location where the integrated circuit element is to be formed is provided by etching, and then a trench groove reaching the P-type semiconductor substrate 30 is formed by the RIE method. 5in2 for separation on its side wall.
35 will be provided. Further, polycrystalline silicon 36 is buried in this groove (a buttering process is performed), and then the thermal oxidation layer 33 and the CVD silicon oxide layer 34 covering the surface of the area where the integrated circuit element is to be formed are removed by an etching process. Next, necessary impurities are introduced to form the internal base 36 and the external base 3.
7.37 and emitter 38 are installed.

Furthermore, a polycrystalline silicon layer is connected to the external base 37 and the emitter layer 38, and the base electrode 39 is coated with A1 alloy.
, an emitter electrode 40 is provided. Although the process order is reversed,
Deep N soil layer 4 reaching polycrystalline silicon embedded RIJ31
1 is provided in advance, and a polycrystalline silicon layer and an A1 alloy are also laminated thereon to provide a collector electrode 42 to complete the integrated circuit element.

(Problem to be Solved by the Invention) By the way, regarding the withstand voltage characteristics, the underlying N-type semiconductor substrate in the above-mentioned vcmit structure has a lower resistance than the N-type semiconductor substrate, and the entire underlying semiconductor substrate can be regarded as an electrode. Moreover, since the end of the PN junction formed on the N-semiconductor substrate is exposed on the surface, the electric field from near this end to the curved part of the PN junction is larger than the electric field to the bottom of the PN junction (the part along the substrate surface). This becomes a factor that prevents the required high voltage resistance.

In this stacked structure obtained by using the epitaxial method, the thickness of the deposited layer is increased in order to avoid the Reach Through phenomenon as described above, and in addition to this, field limiting is applied to extend the depletion layer in the direction along the surface of the deposited layer. A field plate structure in which a junction electrode is extended to an insulating layer covering a structure or a PN junction end is not preferable for improving the degree of integration.

Although high-speed bipolar transistors are still in practical use, the presence of junction capacitance between the buried diffusion layer and the semiconductor substrate causes a delay time in device operation, and the series resistance of the collector must be lowered. Therefore, a deep n0 diffusion layer is required. As a result, miniaturization is limited by lateral diffusion and seepage of the buried layer. Furthermore, if a buried diffusion layer is provided over the entire surface of a semiconductor substrate with the aim of achieving high integration, it is necessary to form trench isolation grooves deep enough to reach the buried layer, and in order to suppress parasitic effects between island regions, The reversal prevention layer must be disposed below the groove, which complicates the process.

The present invention suppresses the junction capacitance between the collector and the semiconductor substrate in order to obtain transistor characteristics that are faster and have higher breakdown voltage than can be obtained by trench element isolation. The purpose is to promote area reduction.

[Structure of the invention]

(Means for Solving the Problem) In order to achieve this object, the present invention utilizes a composite semiconductor substrate employing the above-described bonding technology, and the side and bottom surfaces of the island region having a substantially rectangular parallelepiped cross section are made of dielectric material. Filled with impurity concentration I
Provide n-3 or more semiconductor layers.

A method is adopted in which the semiconductor element electrodes installed in this island region are led out from the surface side of the island region by also utilizing the highly concentrated semiconductor layer installed on the side surface. As a specific method for forming it, a composite semiconductor substrate is obtained by the above-mentioned bonding technique, and a base semiconductor substrate oxide layer, a semiconductor layer with a high concentration, and an island region are provided in this order near the bonding surface, and then the composite semiconductor substrate is A trench groove surrounding this island region is provided in the insulating layer covering the insulator layer, and a high concentration (I
A semiconductor layer (above) is formed.

After that, the trench is filled with an insulating layer and a planarization process is performed to form an impurity region for a semiconductor element in the island region, and an electrode connected to the impurity region is provided on the side wall with a high concentration (I
10111an-3 or higher) is also utilized to complete an integrated circuit device.

(Function) The integrated circuit device according to the present invention is a high-speed, high-voltage device, and for this purpose, the surroundings are completely separated by a dielectric layer, and an island region having a substantially rectangular parallelepiped cross section is provided. In addition, a semiconductor layer with a high impurity concentration of I x 10" an-3 or more is formed on the bottom surface. The electrode for the semiconductor element provided in this island region is formed on the surface of the island region by also utilizing the semiconductor layer with a high impurity concentration formed on the side surface. We have adopted a method to derive it from

It has been found that the collector lead-out resistance of the bipolar transistor formed in this island region can be suppressed to a maximum of 150Ω. If its two-dimensional dimensions are 10 μs×15 μm and the thickness of the semiconductor layer provided on the bottom and side surfaces is 0.37 m, the impurity concentration must be I x 1.011 Icyn-” or more, which is the reason for limitation in the present invention. Moreover, the frequency characteristics are 1501 + Z ~ 2 in terms of cutoff frequency.
0GH2 has been improved, and the intellectual pressure is also 200V -300
V,! : It is clear that the internal level improves.

This is because it has the above-mentioned characteristics compared to conventional elements.
It is assumed that excellent characteristics can be exhibited because the collector capacitance can be reduced and the problems caused by seepage of the buried layer can be eliminated.

In addition to the application of bonding technology to realize this structure, the selectivity with respect to silicon oxide is advantageous in etching by RIE when forming trench grooves on the side surfaces of the island regions.
This bonding technique has the advantage that it can be stopped at the silicon oxide near the bonding surface and that vertical sidewalls can be formed.

(Example) An example according to the present invention will be described in detail with reference to FIGS. Among the silicon semiconductor substrates to which this bonding technology is applied, those that serve as the base are (a) specific resistance 2
5-50Ω- P (100) Si substrate surface with a thickness of 1.0
An undoped polycrystalline film having a thickness of 400 nm after oxidation is provided in the .mu.m region, and As+ is ion-implanted at a dose of 1.times.10@18 cm@-2. Another example (b) is a specific resistance of 25 to 50
Q an (7) P (100) SL substrate O+ ions with a Nitose amount of 10"-19 order are implanted to a thickness of about 0.
5-5jO2 layer is further provided with a dose of I x 1010
A semiconductor substrate in which two layers are formed by ion-implanting 1 Ga'' of As is also applicable, and a semiconductor substrate (c) in which the As+ implantation process of (a) is omitted may also be used.

On the other hand, there are some examples of semiconductor substrates to be bonded corresponding to the underlying semiconductor substrates (a), (b), and (c). For (a) and (b), an N'' (100) Si substrate with a specific resistance of 1.5Ω to 2Ω is used, and its surface and the surface of the polycrystalline silicon layer are bonded, and for (c), Arrow specific resistance 1.5Ω~2Ω N
”(100) Dosage amount I XIO”cm-” on Si substrate
Either As'' is implanted to form an N layer, or an As-doped polycrystalline silicon layer is deposited to provide an N+ layer, and the surface of the oxide layer and this N+ layer are bonded.

Now, in the actual bonding process, the polycrystalline silicon layer oxide surface that will be the bonding surface is polished to form a mirror surface with a roughness of 500 Å or less.
Depending on the surface condition after this polishing step, oils and fats may be removed as a pretreatment. Next, after washing with clean water for several minutes, a dehydration treatment such as a spinner treatment is performed at room temperature to remove excess moisture while leaving the moisture that is assumed to have been adsorbed on the mirror surface as it is. However, avoid heating and drying at temperatures above 100°C, where most of this adsorbed moisture will evaporate.

The Si semiconductor substrates subjected to this treatment are placed in a clean atmosphere of class 1 or lower, for example, and are closely bonded to each other with substantially no foreign matter (dust) interposed between the mirror surfaces to form a composite semiconductor substrate. The bonding strength can be increased by heat-treating this composite semiconductor substrate at 200°C or higher, preferably 1000'C to 1200°C, and the atmosphere during the bonding process can be air, oxygen, or a mixture of both. This atmosphere can also be used to increase bonding strength.

By the way, in this bonding process, polar groups are formed by the water washing process on the mirror surface, and the bonding caused by this causes the Bu
It is assumed that a composite semiconductor substrate can be obtained because a bonding layer different from the lk structure is created. The boundary of this bonding layer may change depending on the applied heat load, so
The bonding layer in the present invention does not only mean clearly demarcating the boundaries of the semiconductor substrates having a stacked structure, regardless of the presence or absence of a difference in conductivity type and impurity concentration, but also includes the above-mentioned fluctuation state.

In forming this composite semiconductor substrate, as shown in FIG.
Next, undoped polycrystalline silicon r3 with a thickness of 400 nm is formed, and As+ is ion-implanted at a dose of 1.times.10@18 cm@-2. On the other hand, N type (100) specific resistance 1.5~
A Si semiconductor substrate 4 with a diameter of 2 Ω is prepared, and its surface and the surface of the polycrystalline silicon layer are integrated by the above-described bonding process to obtain a composite semiconductor substrate.

This Si semiconductor substrate to be bonded, that is, the N-type (100) Si semiconductor substrate 4 is scraped off by mechanical polishing means such as lapping until the thickness reaches a desired value of 1 μs to 5 μs (see FIG. 1A). A silicon oxide layer 6 with a thickness of 1100 nm is deposited on this polished surface by a thermal oxidation method, and then a silicon nitride layer 7 is successively deposited with a thickness of 1100 nm by a low pressure CVD method. Patterning is applied to remove by etching.

Furthermore, a silicon oxide layer 8 is deposited on this surface by the CVD method, and a groove with a width of 1.5 μm is formed through the silicon oxide layer 6 surrounding the area where the element is to be formed and the CVD silicon oxide layer 8. Using the accumulated CVD silicon oxide layer 8 as a mask, a trench pattern 9 having a cross section perpendicular to the N-type Si substrate 4 and the buried polycrystalline silicon layer 3 is formed to separate island regions 10 in which elements will be formed.

This process applies the RIE method, but since it has a selectivity, it can be stopped on the silicon oxide layer 2 formed on the P-type (100) substrate 1, which is the base of the composite semiconductor substrate, and at the same time, it can be stopped on the side walls of the trench with a vertical cross section. 11 can be obtained, which is advantageous for the characteristics of the semi-diaphragm element, which will be described later.

Note that the film thickness of the CVD silicon oxide layer 8 serving as a mask decreases depending on the depth of the trench, but the final film thickness is 1000-2.
The initial film thickness is set to keep it at 000. (1st
(Fig.
After coating to a thickness of 0.00 nm, the entire surface is etched back by RIE to remove the As-doped polycrystalline layer on the outside of the trench and on the bottom surface of the trench, leaving the As-doped polycrystalline silicon layer 12 only on the sidewalls 11 of the trench. (Figure 1 C)
The AS concentration is I x 10111a11-'' or more, which is approximately the same concentration as that of the polycrystalline silicon layer 3 provided on the P-type (100) Si semiconductor substrate 1, and has a mutually continuous shape.

Using the remaining silicon nitride layer 7 as a mask, selective oxidation (LOGO5
) is applied to the trench side wall 11 at the same time.
As is formed in the island region 10 from the s-doped polycrystalline silicon layer 12 and the As-doped polycrystalline silicon layer 3 at the bottom of the island region 10.
A diffusion layer (not shown) is provided, and at the same time, an oxide film 13 with a thickness of about 1 to 2 pm is formed in the trench groove. (
(Fig. 1 2) Since the inside of the trench groove is not completely filled in this oxidation process, an undoped polycrystalline silicon layer 14 of 200 nm is deposited by the LPCVD method, and an undoped polycrystalline silicon layer outside the trench groove is removed by another etch-back process. Remove and completely embed.

After the surface of the buried undoped polycrystalline silicon layer 14 is oxidized to a thickness of 200 nm, a layer corresponding to the thickness of the silicon oxide layer laminated on the remaining silicon nitride layer 7 is removed by isotropic etching over the entire surface. Figure 1 shows E.

Next, using this silicon nitride layer 7 as a mask, LOCO5 oxidation is again added to a thickness of 200 nm, and then the silicon nitride layer 7 and the buffer oxide layer are removed by an etching process. (See Figure 1) By performing the above steps continuously, the cross section becomes almost a rectangular parallelepiped, and the side and bottom surfaces are completely separated by a dielectric (silicon oxide), and the positions adjacent to the side and bottom surfaces are completely separated. An island region having a highly concentrated semiconductor layer can be provided in the semiconductor layer. Various active or passive elements such as bipolar transistors are formed in this island region 2 to complete the integrated circuit element base. In the embodiment, a single island region has been described, but it is natural that a plurality of island regions can be formed at the same time.

Next, an example of installing a bipolar transistor in this island area will be described.

As mentioned above, the N (100) semiconductor substrate 4 having a diffusion layer from the polycrystalline silicon layer functions as the collector layer of this transistor, and its surface is formed with 1014
~” atoms/cc, and this is the internal base layer 1
5 is formed to a surface concentration of 5×101017 ato/cc, and the resulting PN junction end is protected by a field oxide film obtained by LOGOS oxidation.

Next, an external base layer 1.6.16 is provided within this internal base layer with a surface concentration of I.times.101019ato/cc, and an emitter layer 17 is further provided in the middle thereof with a surface concentration of 2.times.1.6.1.
0"atoms/cc. Each region obtained by introducing each impurity has a so-called brainer structure, and this base layer and emitter layer are formed with electrodes 18 and 18, respectively.
1.4] and placed on the side wall 11
2 and LOCO'S oxide film surface oxide film thickness interplane electrode 20
is formed to complete a bipolar integrated circuit device. In addition, as shown in Figure 1H, after the bonding process is completed, sb is introduced over the entire surface of the polishing process, which further shows an N-type property and a resistivity of 1.
．． It is also possible to grow a thin epitaxial layer 21 with a thickness of 5 to 2 Ω and carry out the steps described above. The thickness of the external base layer and the emitter layer is 0.2 to 0.3, and that of the external base layer is 1 μs to 0.5 μm.

〔Effect of the invention〕

The present invention utilizes a composite semiconductor substrate, provides island regions completely separated by a dielectric material, and provides highly concentrated semiconductor layers on the side and bottom surfaces, which eliminates the parasitic effect between satin particles, as well as collector resistance. The cut-off frequency has been reduced to 15-2 compared to the conventional cut-off frequency of 10-146H2.
0GH2, and has the advantage of making it easy to design LSI circuits and patterns, so improvements in system characteristics can be expected. Furthermore, it can be applied not only to high-speed devices but also to high-voltage devices, and 20 to 300 μm can be achieved.

[Brief explanation of the drawing]

FIGS. 1A to 1H are cross-sectional views showing the manufacturing process of an embodiment according to the present invention, and FIG. 2 is a cross-sectional view showing the main parts of a conventional integrated circuit.

Claims (2)

[Claims] (1) A first semiconductor substrate, a plurality of island regions having a substantially rectangular cross section provided from the surface of the semiconductor substrate inward, a dielectric layer disposed between the island regions, and side and bottom portions of the island regions. A semiconductor layer having an impurity concentration of 1×10^1^8 cm^-^3 or more provided in the semiconductor substrate, a bonding layer formed on the surface side of the semiconductor layer located on the opposite side of the semiconductor substrate surface, and a bonding layer fixed to the bonding layer. a second semiconductor substrate;
an insulating layer covering the surface of the semiconductor substrate, a plurality of PN junctions formed by introducing impurities into the island region exposed by removing the insulating layer, and an end of the PN junction covered by the insulating layer; An integrated circuit element comprising: an electrode formed by connecting a semiconductor layer provided on the side of the island region and a surface of the semiconductor substrate; and another electrode arranged in a region surrounded by the PN junction. (2) A step of preparing a semiconductor substrate to be bonded and another semiconductor substrate, a step of forming an oxide layer on the other semiconductor substrate, and a step of forming an oxide layer of 1×10^1^8 on the surface of one of the semiconductor substrates.
a step of forming a semiconductor layer having an impurity concentration of cm^-^3 or more, and a step of bonding the surface of this semiconductor layer to the surface of one of the semiconductor substrates to form a composite semiconductor substrate;
A step of applying a means to reduce the thickness of the exposed surface of the semiconductor substrate to be bonded constituting this composite semiconductor substrate, a step of forming a mask pattern on the composite semiconductor substrate to which the method has been applied, a step of forming a trench groove reaching the semiconductor layer from the surface; a step of forming a semiconductor layer having an impurity concentration of 1×10^1^8 cm^-^3 or more on the side wall of the trench; an oxidation step; filling the trench groove with oxide and then planarizing the surface of the composite semiconductor substrate and removing the excess semiconductor layer;
a step of removing the mask layer and the buffer oxide layer; a step of introducing impurities into the exposed island region; a step of forming an electrode in the region surrounded by the resulting PN junction; A method of manufacturing an integrated circuit device, comprising the step of forming another electrode connecting a semiconductor layer formed on a side wall and a surface of the composite semiconductor substrate.