JPH0561775B2 - - Google Patents

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Publication number
JPH0561775B2
JPH0561775B2 JP57065925A JP6592582A JPH0561775B2 JP H0561775 B2 JPH0561775 B2 JP H0561775B2 JP 57065925 A JP57065925 A JP 57065925A JP 6592582 A JP6592582 A JP 6592582A JP H0561775 B2 JPH0561775 B2 JP H0561775B2
Authority
JP
Japan
Prior art keywords
type
region
base
layer
vertical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57065925A
Other languages
Japanese (ja)
Other versions
JPS58182260A (en
Inventor
Toyoki Takemoto
Tsutomu Fujita
Haruyasu Yamada
Tadanaka Yoneda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57065925A priority Critical patent/JPS58182260A/en
Priority to DE8383103726T priority patent/DE3361832D1/en
Priority to EP83103726A priority patent/EP0093304B1/en
Publication of JPS58182260A publication Critical patent/JPS58182260A/en
Priority to US07/124,423 priority patent/US4826780A/en
Priority to US07/295,380 priority patent/US5066602A/en
Publication of JPH0561775B2 publication Critical patent/JPH0561775B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8228—Complementary devices, e.g. complementary transistors
    • H01L21/82285—Complementary vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H01L27/0244—I2L structures integrated in combination with analog structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H01L27/0826—Combination of vertical complementary transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Description

【発明の詳細な説明】 本発明は半導体集積回路装置に関し、特に高速
のバイポーラトランジスタを含む半導体集積回路
装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a high-speed bipolar transistor.

半導体集積回路装置にはPNPトランジスタ、
NPNトランジスタ等が一体化構成されている。
ここで、一般にNPNトランジスタのスイツチン
グ速度は高速にすることが出来る反面、PNPト
ランジスタは構造が複雑であつたり、横方向形成
されたものは高速にすることが出来ない欠点を有
する。従つて、PNPトランジスタ、NPNトラン
ジスタとを含む半導体集積回路装置はその両トラ
ンジスタの速度的なアンバランスが生じる故に全
体として見た場合、回路的に多くの制限があつ
た。 Semiconductor integrated circuit devices include PNP transistors,
NPN transistor etc. are integrated.
Generally, the switching speed of NPN transistors can be increased, but PNP transistors have a complicated structure or are formed laterally, which has the drawback that high switching speeds cannot be achieved. Therefore, a semiconductor integrated circuit device including a PNP transistor and an NPN transistor has many limitations in terms of circuitry when viewed as a whole due to a speed imbalance between the two transistors.

第１図はPNPトランジスタ、NPNトランジス
タを一体化形成した従来の半導体集積回路装置を
示す。 FIG. 1 shows a conventional semiconductor integrated circuit device in which a PNP transistor and an NPN transistor are integrally formed.

第１図において、１はｐ形基板、Ｚは高濃度ｎ
形埋込み層、３はｎ形エピタキシヤル層、４は予
備分離拡散層を示す。５はエピタキシヤル層３表
面から形成された分離拡散層で、予備分離拡散層
４と途中で接続され、活性領域の分離を行なつて
いる。 In FIG. 1, 1 is a p-type substrate, Z is a high concentration n
3 is an n-type epitaxial layer, and 4 is a preliminary isolation diffusion layer. Reference numeral 5 denotes an isolation diffusion layer formed from the surface of the epitaxial layer 3, which is connected to the preliminary isolation diffusion layer 4 midway to isolate the active region.

６ｅ，６ｃ，７ｄはｐ型拡散層である。ここ
で、NPNトランジスタ部分においては７ｂはベ
ースとなるｐ型領域で、ラテラルPNPトランジ
スタ部分においては６ｅ，６ｃはそれぞれエミツ
タとコレクタを形成している。８ｂはPNPトラ
ンジスタのベース領域用のコンタクト、９ｅは
NPNのトランジスタのエミツタ、９ｃはNPNト
ランジスタのコレクタコンタクトのための高濃度
ｎ形拡散層である。第１図で１体化形成された、
NPN、PNPトランジスタにおいて、PNPの横型
トランジスタはベース巾（領域６ｅと６ｃ間距
離）が平面的、つまりマスクのパターン精度で定
まる。一般に、マスク精度はそれほど正確なもの
でないため、通常短かいもので3μｍ程度である。
従つて、ベース幅の狭い高密度PNPトランジス
タを形成出来ない。また、NPNトランジスタの
ベース領域７ｂにおいては拡散によつて濃度傾斜
がついているため、電界傾斜がベース領域で形成
されるのでキヤリアの加速がなされ高速化が実現
する。しかし、PNPトランジスタのベース領域
３はエピタキシヤル層そのものであり、濃度傾斜
がなく高速化が実現されない。 6e, 6c, and 7d are p-type diffusion layers. Here, in the NPN transistor portion, 7b is a p-type region serving as a base, and in the lateral PNP transistor portion, 6e and 6c form an emitter and a collector, respectively. 8b is the contact for the base region of the PNP transistor, 9e is the contact for the base region of the PNP transistor, and 9e is the contact for the base region of the PNP transistor.
The emitter of the NPN transistor, 9c, is a heavily doped n-type diffusion layer for the collector contact of the NPN transistor. In Figure 1, the unit is formed into one body.
In NPN and PNP transistors, the base width (distance between regions 6e and 6c) of the PNP lateral transistor is determined in a plane, that is, by the pattern accuracy of the mask. Generally, the mask accuracy is not very accurate, and the short one is usually about 3 μm.
Therefore, a high-density PNP transistor with a narrow base width cannot be formed. Furthermore, since the base region 7b of the NPN transistor has a concentration gradient due to diffusion, an electric field gradient is formed in the base region, so carriers are accelerated and high speed is achieved. However, the base region 3 of the PNP transistor is an epitaxial layer itself, and there is no concentration gradient, making it impossible to achieve high speed.

更に、PNPトランジスタのコレクタ領域６ｃ
の濃度がベース領域３よりむしろ高く、ベース巾
を縮少していつた場合、コレクタ、ベース間耐圧
が急速に下がる。 Furthermore, the collector region 6c of the PNP transistor
If the concentration is higher than in the base region 3 and the base width is reduced, the withstand voltage between the collector and the base will drop rapidly.

以上の様に、PNPトランジスタのベースが巾
が広い、拡散プロフアイルにより電界傾斜がつい
ていない、PNPトランジスタのエミツタ、コレ
クタが同一濃度である等の理由により横型PNP
トランジスタは縦型NPNトランジスタに比し著
じるしく特性が劣るのが通常である。従つて、第
１図に示す半導体集積回路装置においては全体と
しての特性が不充分なものとなつていた。 As mentioned above, the horizontal PNP is
Normally, transistors have significantly inferior characteristics compared to vertical NPN transistors. Therefore, the semiconductor integrated circuit device shown in FIG. 1 has insufficient characteristics as a whole.

次に、これを改善した半導体集積回路装置の従
来例を第２図に示す。第２図の場合はPNPトラ
ンジスタを縦型形成したものである。 Next, FIG. 2 shows a conventional example of a semiconductor integrated circuit device that has improved this. In the case of FIG. 2, a PNP transistor is formed vertically.

第２図において、１１はｐ型基板、１２は高濃
度ｎ型埋込み層、１３はｎ型エピタキシヤル層、
１４はｐ型予備分離拡散層で、１５は分離拡散層
である。この分離拡散層１４及び１５により、活
性領域を分離させている。分離領域１２上にイオ
ン注入法等で組作されたｐ型領域で、縦型PNP
のコレクタとなる領域である。１７，１８はそれ
ぞれ分離拡散層１４，１５の領域形成時に同時形
成されるもので、コレクタ領域１２の引出し拡散
層となつている。１９はコレクタウオールであ
る。２０はp+の拡散層で分離拡散層１５と同時
に形成され、縦型PNPトランジスタのベースと
なる領域である。 In FIG. 2, 11 is a p-type substrate, 12 is a high concentration n-type buried layer, 13 is an n-type epitaxial layer,
14 is a p-type preliminary isolation diffusion layer, and 15 is an isolation diffusion layer. The active regions are separated by the isolation diffusion layers 14 and 15. A p-type region assembled on the isolation region 12 by ion implantation, etc., and a vertical PNP
This is the area that serves as the collector. 17 and 18 are formed simultaneously when forming the isolation diffusion layers 14 and 15, respectively, and serve as lead-out diffusion layers for the collector region 12. 19 is the collector all. A p + diffusion layer 20 is formed at the same time as the isolation diffusion layer 15, and is a region that becomes the base of a vertical PNP transistor.

２１は通常のNPNトランジスタのエミツタ層、
２２はベース層、２３はエミツタ２１と同時に形
成されたコレクタ・コンタクト部である。 21 is the emitter layer of a normal NPN transistor,
22 is a base layer, and 23 is a collector contact portion formed at the same time as the emitter 21.

さて、第２図でp+層拡散層２０、ｎ型エピタ
キシヤル層１３、p+型コレクタ層１６によつて
縦型PNPトランジスタが形成される。このPNP
トランジスタは第１図で示した横型PNPと違い、
ベース巾がマスクの寸法及び寸法精度によつて決
定されておらず、エピタキシヤル層１３の厚み及
び、p+層拡散領域１６の深さに依存しているた
め、拡散制御によつてベース巾は狭く出来る利点
がある。しかしこの構造においても多くの欠点が
ある。まず第１にベース巾であるが、これはエピ
タキシヤル層１３の厚みからエミツタ２０の拡散
深さとｐ型領域１６の上方拡散を引いたものによ
つて決定されるので、この拡散パラメータとエピ
タキシヤル層の厚み並びに濃度が必要なため、ベ
ース巾の分布が非常に大きい。 Now, in FIG. 2, a vertical PNP transistor is formed by the p + layer diffusion layer 20, the n type epitaxial layer 13, and the p + type collector layer 16. This PNP
The transistor is different from the horizontal PNP shown in Figure 1,
Since the base width is not determined by the dimensions and dimensional accuracy of the mask, but depends on the thickness of the epitaxial layer 13 and the depth of the p + layer diffusion region 16, the base width can be determined by diffusion control. It has the advantage of being narrow. However, this structure also has many drawbacks. First of all, the base width is determined by the thickness of the epitaxial layer 13 minus the diffusion depth of the emitter 20 and the upward diffusion of the p-type region 16, so this diffusion parameter and the epitaxial Because of the required layer thickness and concentration, the base width distribution is very large.

それに加えるにｐ型拡散層１６の濃度は埋込み
層１２との濃度との加減によつて決まるため、上
方拡散は、ｐ型拡散層１６のドーピング量によつ
て１義的に決まらず、従つて、ベース巾の分布は
ますます大きくなつてしまい、ベース巾がパター
ン精度で制限されないと云うもののベース巾の決
定制御が困難である。 In addition, since the concentration of the p-type diffusion layer 16 is determined by adjusting the concentration of the buried layer 12, upward diffusion is not primarily determined by the doping amount of the p-type diffusion layer 16, and therefore , the distribution of base widths becomes increasingly large, and although the base width is not limited by pattern accuracy, it is difficult to determine and control the base width.

しかも、第１図で示したPNPトランジスタで
みられた欠点であるベース領域での濃度勾配及び
コレクタ１２の濃度が高い問題は改善されていな
い。 Furthermore, the drawbacks of the PNP transistor shown in FIG. 1, such as the concentration gradient in the base region and the high concentration in the collector 12, have not been improved.

本発明は従来の欠点にかんがみなされたもの
で、高速のバイポーラトランジスタを含む半導体
集積回路装置を提供することを目的とする。すな
わち、本発明は横方向バイポーラトランジスタの
低速性と縦型バイポーラトランジスタの制御性を
改善することによつて、高速のバイポーラトラン
ジスタを含む半導体集積回路装置を提供せんとす
るものである。更に、本発明は高速のバイポーラ
トランジスタと高抵抗素子、I2L素子等のデバイ
スを何ら製造工程を増加することなく一体化形成
可能な半導体集積回路装置を提供せんとするもの
である。 The present invention has been made in view of the conventional drawbacks, and an object of the present invention is to provide a semiconductor integrated circuit device including a high-speed bipolar transistor. That is, the present invention aims to provide a semiconductor integrated circuit device including a high-speed bipolar transistor by improving the low speed of the lateral bipolar transistor and the controllability of the vertical bipolar transistor. Furthermore, the present invention aims to provide a semiconductor integrated circuit device in which devices such as a high-speed bipolar transistor, a high resistance element, and an I 2 L element can be integrally formed without any increase in manufacturing steps.

以下、本発明の構成を図面を用いて説明する。
第３図は本発明の半導体集積回路装置の製造方法
を説明するための部分的な断面図である。本実施
例においては縦型のPNPトランジスタと縦型
NPNトランジスタ、高抵抗素子を一体化形成し
たものであり、縦型NPNトランジスタの部分に
改良を加えたものである。第３図において、３１
はｐ型半導体基板、３２はｎ型高濃度埋込領域、
３３は0.5〜1.0Ω程度のｎ型エピタキシヤル層で
３〜4μｍの厚さに成長される。３４はｐ型高濃
度の予備拡散領域で、エピタキシヤル層３３表面
から形成されるｐ型高濃度拡散領域３５と対をな
し、エピタキシヤル層３３の分離を行なつてい
る。この分離領域３４，３５は酸化膜分離によつ
て行なつても本発明の効果は変らない。３６はｐ
型の高濃度領域で、埋込み領域３２の内側に設置
せられ、分離領域３５と同時に形成せられてい
る。しかし、高濃度埋込領域３６の表面濃度は、
基板３１上の埋込領域３２が高濃度のためにかな
り下がつており、そのため上方への拡散は拡散領
域３４ほど高くならない。３７は拡散領域３５と
同時に形成されたp+拡散領域で、コレクタ抵抗
の削減のために設置せられたものである。 Hereinafter, the configuration of the present invention will be explained using the drawings.
FIG. 3 is a partial cross-sectional view for explaining the method of manufacturing a semiconductor integrated circuit device of the present invention. In this example, a vertical PNP transistor and a vertical
It integrates an NPN transistor and a high resistance element, and is an improved version of the vertical NPN transistor. In Figure 3, 31
32 is a p-type semiconductor substrate, 32 is an n-type high concentration buried region,
Reference numeral 33 is an n-type epitaxial layer of about 0.5 to 1.0 Ω and is grown to a thickness of 3 to 4 μm. Reference numeral 34 denotes a p-type high concentration preliminary diffusion region, which forms a pair with a p-type high concentration diffusion region 35 formed from the surface of the epitaxial layer 33 to separate the epitaxial layer 33. Even if these isolation regions 34 and 35 are formed by oxide film isolation, the effects of the present invention will not change. 36 is p
This is a high concentration region of the mold, located inside the buried region 32, and formed at the same time as the isolation region 35. However, the surface concentration of the high concentration buried region 36 is
The buried region 32 on the substrate 31 is quite depressed due to the high concentration, so the upward diffusion will not be as high as the diffusion region 34. A p + diffusion region 37 was formed at the same time as the diffusion region 35, and was provided to reduce collector resistance.

３８はn+の拡散領域で埋込領域３２と接続さ
れる。３９は本発明にかかわる主要拡散部で、低
ドーズのイオン注入法により形成され、シート抵
抗値として通常のベース抵抗の200Ω／□に比し
１桁以上高い2KΩ／□〜4KΩ／□程度のp-領域
である。 38 is an n + diffusion region connected to the buried region 32 . 39 is the main diffusion part related to the present invention, which is formed by a low-dose ion implantation method, and has a sheet resistance value of about 2KΩ/□ to 4KΩ/□, which is more than an order of magnitude higher than the normal base resistance of 200Ω/□. -area .

４０は同時に形成されたp-領域で、ここでは
高抵抗部となつている。４１はｎ型ウエルでp-
領域３９上に形成されPNPトランジスタのベー
スとなる。４２は約200Ω／□程度に形成される
ｐ領域でPNPトランジスタのエミツタであり、
NPNトランジスタのベース領域４３と同時に形
成される。４４は高抵抗部のコンタクト用拡散領
域で、領域４２，４３と同時形成される。４５は
ベース領域４１のコンタクト拡散領域であり、
NPNトランジスタのエミツタ領域４６と同時に
形成される。４７はNPNトランジスタのコレク
タ３３のコンタクト領域である。 Reference numeral 40 denotes a p - region formed at the same time, which here serves as a high resistance portion. 41 is an n-type well with p -
It is formed on region 39 and serves as the base of the PNP transistor. 42 is a p region formed to about 200Ω/□ and is the emitter of the PNP transistor;
The base region 43 of the NPN transistor is formed simultaneously. Reference numeral 44 denotes a contact diffusion region of the high resistance portion, which is formed at the same time as regions 42 and 43. 45 is a contact diffusion region of the base region 41;
The emitter region 46 of the NPN transistor is formed simultaneously. 47 is a contact region of the collector 33 of the NPN transistor.

以上明らかなように、第３図では領域４２，４
１，３９で縦型PNPトランジスタが形成され、
領域４６，４３，３３で縦型NPNトランジスタ
が形成され、領域４０，４４で高抵抗が形成され
ていることがわかる。ここで、縦型PNPトラン
ジスタの特性を次に説明する。従来例で述べて来
た３つの問題点すなわち、ベース巾については、
ベースであるｎ領域４１の形成が、低濃度のp-
領域３９内に形成されており、その濃度の制御及
び深さの制御がp-領域３９上から打込まれるイ
オン注入によつて精度良く定められる。すなわ
ち、ベース巾はｎ領域４１とｐ領域４２の拡散の
みによつて決定されるので制御性が良い。つま
り、第２図の場合は３つのパラメータであつたが
本実施例では２つのパラメータでベース巾が決定
される。また、ｎ領域４１は最終的にはイオン注
入後のドライブインによつて決められるため、上
から下方向に濃度勾配がついており、電界加速が
行なわれる構造になつているのでキヤリアの走行
速度が増大し、高速動作が可能となる。又、コレ
クタとなるｐ領域３９の濃度は従来例と異なり、
p-であるため、耐圧も高い。 As is clear from the above, in FIG.
A vertical PNP transistor is formed at 1,39,
It can be seen that vertical NPN transistors are formed in regions 46, 43, and 33, and high resistance is formed in regions 40 and 44. Here, the characteristics of the vertical PNP transistor will be explained next. Regarding the three problems mentioned in the conventional example, namely, the base width,
The formation of the n region 41, which is the base, is performed using a low concentration p -
It is formed in region 39, and its concentration and depth can be controlled with high precision by ion implantation from above p - region 39. That is, since the base width is determined only by the diffusion of the n region 41 and the p region 42, controllability is good. In other words, the base width is determined by two parameters in this embodiment, whereas in the case of FIG. 2 there were three parameters. In addition, since the n-region 41 is ultimately determined by drive-in after ion implantation, there is a concentration gradient from top to bottom, and the structure is such that electric field acceleration is performed, so the traveling speed of the carrier is This increases the capacity and enables high-speed operation. Moreover, the concentration of the p region 39 which becomes the collector is different from that of the conventional example.
Since it is p - , it has a high breakdown voltage.

以上の様に、第３図に示す半導体集積回路装置
は高耐圧、高速、高密度縦型PNPトランジスタ
と高速の縦型NPNトランジスタと高抵抗を一体
化構成出来るので高速化ICを実現する上で効果
は極めて大きい。 As described above, the semiconductor integrated circuit device shown in Fig. 3 can integrate a high-voltage, high-speed, high-density vertical PNP transistor, a high-speed vertical NPN transistor, and a high resistance, which is useful for realizing a high-speed IC. The effect is extremely large.

次に、第３図における縦型PNPトランジスタ
の深さ方向不純物分布を第４図に示す。 Next, FIG. 4 shows the impurity distribution in the depth direction of the vertical PNP transistor in FIG. 3.

同図において、埋込み領域３２はたとえばAs
（砒素）のような拡散係数の小さいものを使用し、
分離領域３６はボロン等を使用することにより、
基板３１からの上方拡散が図示したようになる。
またエミツタ領域３６、ベース領域４１及びコレ
クタ領域３９は、イオン注入法でそれぞれボロ
ン、リン、ボロン等を打込みその後の熱処理によ
り形成される。同図であきらかなように、ベース
領域４１の濃度傾斜が大きく、ベースに電界傾斜
が得られる。更に、コレクタ領域３９がきわめて
低濃度であるため、ベース領域４１の形成はその
深さも、ベースへの不純物の添加量と、エミツタ
領域４２不純物量の両者により、実質的に定めら
れコレクタ領因３９の不純物濃度に依存すること
ないので、その制御に困難性はない。また、第３
図における構造では、高抵抗部分領域４０と３９
が共通プロセスであり、NPNトランジスタのベ
ース領域４３がPNPトランジスタのエミツタ領
域４２及び高抵抗のコンタクト４４と共通プロセ
スで形成されるため、縦型PNPトランジスタを
形成するために、新たなプロセスとして、単にベ
ースとなるｎ形領域４１を形成するプロセスの追
加にすぎなく非常に簡単な構造となつている。 In the figure, the embedded area 32 is, for example, A s
(arsenic), which has a small diffusion coefficient,
By using boron or the like in the separation region 36,
The upward diffusion from the substrate 31 is as shown.
Further, the emitter region 36, the base region 41, and the collector region 39 are each formed by implanting boron, phosphorus, boron, or the like by an ion implantation method, followed by heat treatment. As is clear from the figure, the concentration gradient in the base region 41 is large, and an electric field gradient is obtained at the base. Furthermore, since the collector region 39 has an extremely low concentration, the depth of the base region 41 is substantially determined by both the amount of impurities added to the base and the amount of impurities in the emitter region 42. Since it does not depend on the impurity concentration, there is no difficulty in controlling it. Also, the third
In the structure shown, high resistance partial regions 40 and 39
is a common process, and since the base region 43 of the NPN transistor is formed in the common process with the emitter region 42 of the PNP transistor and the high resistance contact 44, in order to form the vertical PNP transistor, simply a new process is required. It has a very simple structure as it is simply an addition to the process of forming the n-type region 41 which serves as the base.

次に本発明の他の実施例について説明する。第
５図は本発明の半導体集積回路装置の製造方法を
説明するための部分的な断面図で、第３図と同一
番号は同一部分を示す。 Next, other embodiments of the present invention will be described. FIG. 5 is a partial cross-sectional view for explaining the method of manufacturing a semiconductor integrated circuit device of the present invention, and the same numbers as in FIG. 3 indicate the same parts.

第５図に示すものはPNPトランジスタのベー
ス領域４１がコレクタウオール３８に接続された
ものを示す。本実施例においては、縦型PNPト
ランジスタのベース領域４１はｎ形領域３３にま
たがつて設置されたコレクタウオール３８に接す
るごとく形成されているので抵抗値が減少するこ
ととなり、高周波特性が改善される。 The one shown in FIG. 5 shows a PNP transistor in which the base region 41 is connected to the collector all 38. In this embodiment, the base region 41 of the vertical PNP transistor is formed so as to be in contact with the collector wall 38 installed across the n-type region 33, so that the resistance value is reduced and the high frequency characteristics are improved. Ru.

第６図は本発明の実施例を示すもので、縦型
PNPトランジスタ、縦型NPNトランジスタ、高
抵抗素子、I2Lを一体化した半導体集積回路装置
の構造断面図を示すものである。 FIG. 6 shows an embodiment of the present invention, in which a vertical type
1 shows a structural cross-sectional view of a semiconductor integrated circuit device that integrates a PNP transistor, a vertical NPN transistor, a high resistance element, and I 2 L.

本実施例においては、第３図と同一番号は同一
部分を示し、４８，４９はp-領域で領域３９，
４０と同一工程により形成され同一深さに設置さ
れる。５０，５１は領域４２，４３，４４と同一
工程により形成されたｐ型領域である。この領域
４８と５０は図示したごとく重ね合わされて形成
されているが、これらがそれぞれI2L素子の第一、
第二のインジエクタ領域となつている。領域５１
はI2L素子のゲート領域となつている。領域４９
は上向きのNPNトランジスタのベースとなつて
いる。領域５２はI2L素子での逆方向トランジス
タのコレクタとなつている。本実施例に係るI2L
は領域５０，５１を有するために、I2Lの横型
PNPトランジスタのインジエクタ電流が少なく
なるので、充分にI2L縦型NPNトランジスタに吸
い込みが可能となる。第６図に方法によれば、 (1) IIL素子のNPNトランジスタの活性ベースと
縦型PNPトランジスタのコレクタを低濃度の
深いＰ層（前記第一のＰ型層）形成するので、
縦型PNPトランジスタの高耐圧化、IIL素子の
電流増幅率の向上及び高速化を達成することが
できる。縦型PNPトランジスタの高速化は、
浅いＮ型層をベースに用いることにより達成で
きる。 In this embodiment, the same numbers as in FIG. 3 indicate the same parts, 48 and 49 are p - regions, and regions 39,
It is formed by the same process as 40 and installed at the same depth. 50 and 51 are p-type regions formed in the same process as regions 42, 43, and 44. These regions 48 and 50 are formed overlappingly as shown, and are the first and second regions of the I 2 L element, respectively.
This is the second injector area. area 51
is the gate region of the I 2 L element. area 49
is the base of an upward-facing NPN transistor. Region 52 serves as the collector of the reverse transistor in the I 2 L element. I 2 L according to this example
has regions 50 and 51, so the horizontal type of I 2 L
Since the injector current of the PNP transistor is reduced, sufficient I 2 L can be absorbed into the vertical NPN transistor. According to the method shown in FIG. 6, (1) Since the active base of the NPN transistor of the IIL element and the collector of the vertical PNP transistor are formed with a low concentration deep P layer (the first P-type layer),
It is possible to achieve higher breakdown voltage of vertical PNP transistors, higher current amplification factor, and higher speed of IIL elements. The speedup of vertical PNP transistors is
This can be achieved by using a shallow N-type layer as a base.

(2) IIL素子のNPNトランジスタの活性ベースの
濃度が通常の縦型NPNバイポーラトランジス
タの活性ベースに比べて1/10以下（シート抵抗
が10倍で深い）となるので、IILのベース幅を
広くとることができ、IILの電流増幅率を高く
安定に制御することができる。通常縦型NPN
バイポーラトランジスタのベースは高濃度の浅
いＰ型層で形成されているので高速化が達成で
きる。(2) The concentration of the active base of the NPN transistor in the IIL element is less than 1/10 that of the active base of a normal vertical NPN bipolar transistor (the sheet resistance is 10 times deeper), so the base width of the IIL can be made wider. It is possible to control the IIL current amplification factor highly and stably. Normal vertical NPN
Since the base of the bipolar transistor is formed of a highly doped, shallow P-type layer, high speed operation can be achieved.

(3) IILの活性ベースと同り領域（前記第一のＰ
型層）を抵抗対として用いことにより、縦型
NPNトランジスタのベース（前記第二のＰ型
層）を抵抗体として用いた場合よりも約1/10の
面積で同じ値の高シート抵抗体と形成できる。(3) The same region as the active base of IIL (the first P
By using the vertical type layer) as a resistor pair,
A high sheet resistor having the same value can be formed with about 1/10 the area of the case where the base of the NPN transistor (the second P-type layer) is used as a resistor.

すなわち、本実施例においては特性の優れた
I2Lを何らプロセスを変更することなく一体化形
成出来る効果がある。尚、ここで、縦型PNPト
ランジスタの特性は第３図、第５図で示した場合
と同様に高速性等を満足するものであることは云
うまでもない。 In other words, in this example, the
This has the effect of allowing I 2 L to be integrally formed without any process changes. Here, it goes without saying that the characteristics of the vertical PNP transistor satisfy high speed and the like as in the cases shown in FIGS. 3 and 5.

第７図は本発明の更に別の実施例を示す半導体
集積回路装置の構造断面図であり、第６図に示す
実施例のI2L部分の改良形である。同図において
第６図と同一番号は同一部分を示す。本実施例に
おいてはI2Lのp-領域４９に領域５２をおおう如
く、ｎ型領域５３が形成されていることが特長で
ある。この領域５３は縦型PNPトランジスタの
ベース領域４１と同一工程で形成されたものであ
る。縦つて、本実施例においてはI2Lのp-領域４
９の巾が狭くなるので、I2Lの縦型NPNトランジ
スタのhFEが増加することになる。 FIG. 7 is a structural sectional view of a semiconductor integrated circuit device showing still another embodiment of the present invention, which is an improved version of the I 2 L portion of the embodiment shown in FIG. In this figure, the same numbers as in FIG. 6 indicate the same parts. This embodiment is characterized in that an n-type region 53 is formed in the I 2 L p - region 49 so as to cover the region 52 . This region 53 is formed in the same process as the base region 41 of the vertical PNP transistor. Vertically, in this example, the p - region 4 of I 2 L
Since the width of 9 becomes narrower, the h FE of the I 2 L vertical NPN transistor increases.

以上、本発明によれば従来の様に縦型トランジ
スタのベース巾を定める方法が、たとえばマスク
精度で決まつたり、プロセスの３〜４の拡散プロ
フアイルのからみで定まつたりというように特定
できず、かつ巾もバラツキが大きいため、広めに
設定せねばならない欠点がなく、本発明は実質的
に領域４１，４２の拡散のみでベース巾が決ま
り、制御性が良い。 As described above, according to the present invention, the conventional method of determining the base width of a vertical transistor can be determined by determining the base width of a vertical transistor, for example, by determining it by mask accuracy, or by determining the width of the base by the diffusion profile of 3 or 4 of the process. Moreover, since the width also varies widely, there is no drawback that the base width must be set wide, and in the present invention, the base width is determined substantially only by the diffusion of the regions 41 and 42, and the controllability is good.

又、本発明での縦型トランジスタのコレクタが
領域３９で形成されるので、コレクタの濃度が低
く、ベース長を狭くした場合耐圧劣化をおこす欠
点が生じない。更に、本発明の縦型トランジスタ
はベースは領域４１で形成されるので濃度傾斜が
あり、電界加速され高速化を実現出来る。また、
本発明は、他のNPN素子、I2L、高抵抗素子と
も、同一工程で製作出来しかもこれらの素子特性
に悪影響を与えない利点を有する。 Further, since the collector of the vertical transistor according to the present invention is formed in the region 39, the concentration of the collector is low, and there is no problem of deterioration of breakdown voltage when the base length is narrowed. Furthermore, since the base of the vertical transistor of the present invention is formed in the region 41, there is a concentration gradient, and electric field acceleration can be applied to achieve high speed. Also,
The present invention has the advantage that other NPN elements, I 2 L, and high resistance elements can be manufactured in the same process without adversely affecting the characteristics of these elements.

以上、本発明は簡単な構成により高速化半導体
集積回路装置を実現出来るので工業的価値が高
い。 As described above, the present invention has high industrial value because it can realize a high-speed semiconductor integrated circuit device with a simple configuration.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第２図は従来の半導体集積回路装置
の構造断面図、第３図は縦型PNPトランジスタ、
縦型NPNトランジスタ及び高抵抗素子を一体化
した本発明の部分的な実施例に係る半導体集積回
路装置の構造断面図、第４図は第３図の縦型
PNPトランジスタの不純物分布図、第５図は第
３図における縦型PNPトランジスタを改良した
本発明の他の部分的な実施例を示す構造断面図、
第６図及び第７図は第３図のものにI2Lを一体化
した本発明の実施例に係る構造断面図を示す。 ３６……p+埋込領域、３９……p-コレクタ領
域、４０……p-抵抗領域、４１……ｎ型ベース
領域、４２……ｐ型エミツタ領域、４３……ｐ型
ベース領域、４４……抵抗コンタクト領域、５０
……I2Lインジエクタ領域、５１……I2Lゲート領
域、５２……I2Lコレクタ領域、５３……ｎ型領
域。 Figures 1 and 2 are structural cross-sectional views of conventional semiconductor integrated circuit devices, Figure 3 is a vertical PNP transistor,
A structural cross-sectional view of a semiconductor integrated circuit device according to a partial embodiment of the present invention in which a vertical NPN transistor and a high resistance element are integrated, FIG. 4 is the vertical type shown in FIG. 3.
An impurity distribution diagram of a PNP transistor; FIG. 5 is a structural cross-sectional view showing another partial embodiment of the present invention, which is an improved version of the vertical PNP transistor in FIG. 3;
6 and 7 show structural sectional views of an embodiment of the present invention in which I 2 L is integrated with the structure shown in FIG. 3. 36...p + buried region, 39...p - collector region, 40...p - resistance region, 41...n-type base region, 42...p-type emitter region, 43...p-type base region, 44 ...Resistive contact area, 50
... I2L injector region, 51... I2L gate region, 52... I2L collector region, 53...n-type region.

Claims (1)

【特許請求の範囲】[Claims] １ Ｐ型半導体基板上に縦型PNPトランジスタ
と縦型NPNトランジスタとＰ型高抵抗素子とIIL
素子形成用のＮ型エピタキシヤル層を形成し、前
記エピタキシヤル層内に前記縦型PNPトランジ
スタのＰ型コレクタと前記高抵抗素子のＰ型高抵
抗領域と前記IIL素子のNPNトランジスタのＰ型
活性ベース及び第一のインジエクタ領域とを第一
のＰ型層で同時に形成し、前記縦型PNPトラン
ジスタのベースを第一のＮ型層で形成し、前記縦
型PNPトランジスタのＰ型エミツタと前記縦型
NPNトランジスタのＰ型ベースと前記高抵抗素
子のＰ型コンタクト領域と前記IIL素子のNPNト
ランジスタのＰ型外部ベース及び第二のインジエ
クタ領域とを第二のＰ型層で同時に形成し、前記
縦型PNPトランジスタのＮ型ベースコンタクト
と前記縦型NPNトランジスタのＮ型エミツタと
前記IIL素子のNPNトランジスタのコレクタとを
第二のＮ型層で同時に形成し、前記第一のＰ型層
を前記第二のＰ型層よりも深く且つシート抵抗で
１ケタ以上高く形成し、前記第一のＮ型層を前記
第一のＰ型層よりも高濃度で浅くかつ前記第二の
Ｐ型層よりも低濃度で深く形成し、前記第二のＮ
型層が前記第二のＰ型層よりも高濃度で浅く形成
することを特徴とする半導体集積回路装置の製造
方法。1 Vertical PNP transistor, vertical NPN transistor, P-type high resistance element, and IIL on a P-type semiconductor substrate
An N-type epitaxial layer for device formation is formed, and a P-type collector of the vertical PNP transistor, a P-type high resistance region of the high-resistance element, and a P-type active layer of the NPN transistor of the IIL element are formed in the epitaxial layer. a base and a first injector region are simultaneously formed with a first P-type layer, a base of the vertical PNP transistor is formed with the first N-type layer, a P-type emitter of the vertical PNP transistor and the vertical mold
A P-type base of the NPN transistor, a P-type contact region of the high-resistance element, a P-type external base and a second injector region of the NPN transistor of the IIL element are simultaneously formed with a second P-type layer, and the vertical An N-type base contact of a PNP transistor, an N-type emitter of the vertical NPN transistor, and a collector of the NPN transistor of the IIL element are simultaneously formed with a second N-type layer, and the first P-type layer is formed with the second N-type layer. The first N-type layer has a higher concentration than the first P-type layer, is shallower, and has a sheet resistance higher than that of the second P-type layer. The second N
A method for manufacturing a semiconductor integrated circuit device, characterized in that the mold layer is formed at a higher concentration and shallower than the second P-type layer.
JP57065925A 1982-04-19 1982-04-19 Semiconductor integrated circuit device Granted JPS58182260A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP57065925A JPS58182260A (en) 1982-04-19 1982-04-19 Semiconductor integrated circuit device
DE8383103726T DE3361832D1 (en) 1982-04-19 1983-04-18 Semiconductor ic and method of making the same
EP83103726A EP0093304B1 (en) 1982-04-19 1983-04-18 Semiconductor ic and method of making the same
US07/124,423 US4826780A (en) 1982-04-19 1987-11-23 Method of making bipolar transistors
US07/295,380 US5066602A (en) 1982-04-19 1989-01-10 Method of making semiconductor ic including polar transistors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57065925A JPS58182260A (en) 1982-04-19 1982-04-19 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS58182260A JPS58182260A (en) 1983-10-25
JPH0561775B2 true JPH0561775B2 (en) 1993-09-07

Family

ID=13301030

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57065925A Granted JPS58182260A (en) 1982-04-19 1982-04-19 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS58182260A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2540297B2 (en) * 1985-09-09 1996-10-02 株式会社 リコー Thermal recording material

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS515973A (en) * 1974-07-04 1976-01-19 Nippon Electric Co
JPS52104076A (en) * 1976-02-27 1977-09-01 Sony Corp Semiconductor unit
JPS53134374A (en) * 1977-04-28 1978-11-22 Sony Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS515973A (en) * 1974-07-04 1976-01-19 Nippon Electric Co
JPS52104076A (en) * 1976-02-27 1977-09-01 Sony Corp Semiconductor unit
JPS53134374A (en) * 1977-04-28 1978-11-22 Sony Corp Semiconductor device

Also Published As

Publication number Publication date
JPS58182260A (en) 1983-10-25

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