JPS58182260A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS58182260A JPS58182260A JP57065925A JP6592582A JPS58182260A JP S58182260 A JPS58182260 A JP S58182260A JP 57065925 A JP57065925 A JP 57065925A JP 6592582 A JP6592582 A JP 6592582A JP S58182260 A JPS58182260 A JP S58182260A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 210000002700 urine Anatomy 0.000 claims 1
- 238000003475 lamination Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 36
- 238000000034 method Methods 0.000 description 12
- 238000002955 isolation Methods 0.000 description 10
- 230000005684 electric field Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8228—Complementary devices, e.g. complementary transistors
- H01L21/82285—Complementary vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
- H01L27/0244—I2L structures integrated in combination with analog structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0826—Combination of vertical complementary transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体集積回路装置に関し、特に高速のバイポ
ーラトランジスタを含む半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a high-speed bipolar transistor.
半導体集積回路装置にはＰＮＰ ）ランジスタ。Semiconductor integrated circuit devices include PNP) transistors.
ＮＰＮトランジスタ等が一体化構成されている。NPN transistors and the like are integrated.
ここで、一般にＮＰＮ）ランジスタのスイッチング速度
は高速にすることが出来る反面、ＰＮＰ）ランジスタは
構造が複雑であったり、横方向形成されたものを使用出
来ない等の理由により高速にすることが出来ない欠点を
有する。従って、ＰＮＰトランジスタ、ＮＰＮ）ランジ
スタとを含む半導体集積回路装置はその両トランジスタ
の速度的なアンバランスが生じる故に全体として見た場
合、回路的にも多くの制限があった。Generally speaking, the switching speed of an NPN) transistor can be made high, but on the other hand, a PNP) transistor cannot be made to have a high switching speed due to its complicated structure or the inability to use one formed laterally. Has no drawbacks. Therefore, a semiconductor integrated circuit device including a PNP transistor and an NPN transistor has many limitations in terms of the circuit when viewed as a whole because an imbalance occurs in speed between the two transistors.
第１図はＰＮＰ）ランジスタ、ＮＰＮ）ランジスタを一
体化形成した従来の半導体集積回路装置を示す。FIG. 1 shows a conventional semiconductor integrated circuit device in which a PNP transistor and an NPN transistor are integrally formed.
第１図において、１はｐ形基板、２は高濃度ｎ形埋込み
層、３はｎ形エピタキシャル層、４は予備分離拡散層を
示す。６はエピタキシャル層３表面から形成された分離
拡散層で、予備分離拡散層４と途中で接続され、活性領
域の分離を行なっている。In FIG. 1, 1 is a p-type substrate, 2 is a heavily doped n-type buried layer, 3 is an n-type epitaxial layer, and 4 is a preliminary isolation diffusion layer. Reference numeral 6 denotes an isolation diffusion layer formed from the surface of the epitaxial layer 3, which is connected to the preliminary isolation diffusion layer 4 midway to isolate the active region.
６・、６ｃ 、７ｂはｐ型拡散層である。ここで、ＮＰ
Ｎ）ランジスタ部分においては７ｂはベースとなるｐ型
頭域で、ラテラルＰＮＰ ）ランジスタ部分においては
６ｅ、６ａはそれぞれエミッタとコレクタを形成してい
る。８ｂはＰＮＰ）ランジスタのベース領域用のコンタ
クト、ｅｅはＮＰＮのトランジスタのエミッタ、９Ｃは
ＮＰＮ）ランジスタのコレクタコンタクトのための高濃
度ｎ膨拡散層である。第１図で１体化形成された、ＮＰ
Ｎ。6., 6c, and 7b are p-type diffusion layers. Here, NP
N) In the transistor portion, 7b is a p-type head region serving as a base, and lateral PNP.) In the transistor portion, 6e and 6a form an emitter and a collector, respectively. 8b is a contact for the base region of the PNP transistor, ee is the emitter of the NPN transistor, and 9C is a high concentration n-swelled diffusion layer for the collector contact of the NPN transistor. NP formed integrally in Figure 1
N.
ＰＮＰ）ランジスタにおいて、ＰＮＰの横型トランジス
タはベース巾（領域６ｅと６ａ間距離）が平面的、つま
りマスクのパターン精度で定まる。一般に、マスク精度
はそれほど正確なものでないため、通常短かいもので３
μｍ程度で、ある。従って、高密度ＰＮＰ）ランジスタ
を形成出来ない。また、ＮＰＮ）ランジスタのベース領
域７ｂにおいては拡散によって濃度傾斜がついているた
め、電界傾斜がベース領域で形成されるのでキャリアの
加速がなされ高速化が実現する。しかし、ＰＮＰ）ラン
ジスタのベース領域３はエピタキシャル層ソのものであ
り、濃度傾斜がなく高速化が実現されない。In the PNP transistor, the base width (distance between regions 6e and 6a) of the PNP lateral transistor is determined in a plane, that is, by the pattern accuracy of the mask. In general, the mask accuracy is not very accurate, so a short one is usually 3
It is on the order of μm. Therefore, high-density PNP) transistors cannot be formed. Furthermore, since the base region 7b of the (NPN) transistor has a concentration gradient due to diffusion, an electric field gradient is formed in the base region, so that carriers are accelerated and high speed is achieved. However, the base region 3 of the PNP transistor is made of an epitaxial layer, so there is no concentration gradient and high speed cannot be achieved.
更に、ＰＮＰ）ランジスタのコレクタ領域６Ｃの濃度が
ベース領域３よりむしろ高く、ベース巾を縮少していっ
た場合、コレクタ、ベース間耐圧が急速に下がる。Furthermore, the concentration of the collector region 6C of the PNP transistor is higher than that of the base region 3, and when the base width is reduced, the withstand voltage between the collector and the base decreases rapidly.
以上の様に、ＰＮＰトランジスタのベースが巾が広い、
拡散プロファイルにより電界傾斜がついていない、ＰＮ
Ｐ）ランジスタのエミッタ、コレクタが同一濃度である
等の理由により横型ＰＮＰトランジスタは縦型ＮＰＮ）
７ンジスタに比し著しるしく特性が劣るのが通常である
。従って、第１図に示す半導体集積回路装置においては
全体としての特性が不充分なものとなっていた。As mentioned above, the base of the PNP transistor is wide,
No electric field gradient due to diffusion profile, PN
P) Because the emitter and collector of the transistor have the same concentration, the horizontal PNP transistor becomes a vertical NPN)
Normally, the characteristics are significantly inferior to those of the 7-inch transistor. Therefore, the semiconductor integrated circuit device shown in FIG. 1 has insufficient characteristics as a whole.
次に、これを改善した半導体集積回路装置の従来例を第
２図に示す。第２図の場合はＰＮＰ）ランジスタを縦型
形成したものである。Next, FIG. 2 shows a conventional example of a semiconductor integrated circuit device that has improved this. In the case of FIG. 2, a PNP transistor is formed vertically.
第２図において、１１はｐ型基板、１２は高濃度ｎ型埋
込み層、１３はｎ型エピタキシャル層、１４はｐ型予備
分離拡散層で、１５は分離拡散層である。この分離拡散
層１４及び１５により、活性領域を分離させているｔ）
１６１１離領域１２上にイオン注入法等で製作されたｐ
型頭域で、縦型ＰＮＰのコレクタとなる領域である。、
１７．１８はそれぞれ分離拡散層１４．１５の領域形成
時に同時形成されるもので、コレクタ領域１２の引出し
拡散層となっている。１９はコレクタウオールである。In FIG. 2, 11 is a p-type substrate, 12 is a heavily doped n-type buried layer, 13 is an n-type epitaxial layer, 14 is a p-type preliminary isolation diffusion layer, and 15 is an isolation diffusion layer. The active regions are separated by these isolation diffusion layers 14 and 15.t)
1611 P made on the isolated region 12 by ion implantation method etc.
This is the type head area and is the area that becomes the collector of the vertical PNP. ,
17 and 18 are formed at the same time as the separation diffusion layers 14 and 15, respectively, and serve as lead-out diffusion layers for the collector region 12. 19 is the collector all.
２゜はｐ＋の拡散層で分離拡散層１６と同時に形成され
、縦型ＰＮＰ ）ランジスタのベースとなる領域である
。2° is a p+ diffusion layer formed at the same time as the isolation diffusion layer 16, and is a region that becomes the base of a vertical PNP transistor.
２１は通常のＮＰＮ）ランジスタのエミツタ層、２２は
ベース層、２３はエミッタ２１と同時に形成されたコレ
クタ・コンタクト部である。21 is an emitter layer of a normal NPN transistor, 22 is a base layer, and 23 is a collector contact portion formed at the same time as the emitter 21.
さて、第２図でｐ＋層層数散層２０ｎ型エピタキシャル
層１３、ｐ＋型コレクタ膚１６によって縦ＷＰＮＰトラ
ンジスタが形成される。このＰＮＰトランジスタ第１図
で示した横型ＰＮＰと違い、ペース巾がマスクの寸法及
び寸法精度によって決定されておらず、エピタキシャル
層１３の厚み及び、ｐ＋層被拡散領域１６深さに依存し
ているため、拡散制御によってベース巾は狭く出来る利
点がある。しかしこの構造においても多くの欠点がある
。まず第１にベース巾であるが、これはエピタキシャル
層１３の厚みからエミッタ２０の拡散深さとｐ型頭域１
６の上方拡散を引いたものにようＸ−タ
って決定されるので、三つの拡散バカ二の制御加減のた
め、ベース巾の分布が非常に大きい。Now, in FIG. 2, a vertical WPNP transistor is formed by the p+ layer dispersed layer 20, the n type epitaxial layer 13, and the p+ type collector layer 16. This PNP transistor differs from the horizontal PNP shown in FIG. 1 in that the pace width is not determined by the dimensions and dimensional accuracy of the mask, but depends on the thickness of the epitaxial layer 13 and the depth of the p+ layer diffused region 16. Therefore, there is an advantage that the base width can be narrowed by diffusion control. However, this structure also has many drawbacks. First of all, the base width is determined by the thickness of the epitaxial layer 13, the diffusion depth of the emitter 20, and the p-type head area 1.
6 minus the upward diffusion, the distribution of the base width is very large due to the control of the three diffusion coefficients.
それに加えるにｐ型拡散層１６の濃度は埋込み層１２と
の濃度との加減によって決まるため、上方拡散は、ｐ型
拡散層１６のドーピング量によって１義的に決まらず、
従って、ベース巾の分布はますます大きくなってしまい
、ペース巾がパターン精度で決定されないと云うものの
ベース巾の決定制御が困難である。In addition, since the concentration of the p-type diffusion layer 16 is determined by adjusting the concentration of the buried layer 12, the upward diffusion is not determined primarily by the doping amount of the p-type diffusion layer 16.
Therefore, the distribution of the base width becomes increasingly large, and although the pace width cannot be determined with pattern accuracy, it is difficult to control the base width.
しかも、第１図で示したＰＮＰ ）ランジスタでみレク
タ１２の濃度が高い問題は改善されていない。Furthermore, the problem of the high concentration of the reflector 12 in the PNP transistor shown in FIG. 1 has not been solved.
本発明は従来の欠点にかんがみなされたもので、高速の
バイポーラトランジスタを含む半導体集積回路装置を提
供することを目的とする。すなわち、本発明は横方向バ
イポーラトランジスタの低速性と縦型バイポーラトラン
ジスタの制御性を改善することによって、高速のバイポ
ーラトランジスタを含む半導体集積回路装置を提供せん
とするものである。更に、本発明は高速のバイポーラト
ランジスタと高抵抗素子、ＩＬ素子等のデバイスを何ら
製造工程を増加することなく一体化形成可能な半導体集
積回路装置を提供せんとするものである。The present invention has been made in view of the conventional drawbacks, and an object of the present invention is to provide a semiconductor integrated circuit device including a high-speed bipolar transistor. That is, the present invention aims to provide a semiconductor integrated circuit device including a high-speed bipolar transistor by improving the low speed of the lateral bipolar transistor and the controllability of the vertical bipolar transistor. Furthermore, the present invention aims to provide a semiconductor integrated circuit device in which devices such as a high-speed bipolar transistor, a high resistance element, and an IL element can be integrally formed without any increase in manufacturing steps.
以下、本発明の構成を図面を用いて説明する。Hereinafter, the configuration of the present invention will be explained using the drawings.
第３図は本発明の一実施例に係る半導体集積回路装置の
構造断面図を示すものである。本実施例においては縦型
のＰＮＰ ）ランジスタと横形ＮＰＮトランジスタ、高
抵抗素子を一体化形成したものであり、縦型ＰＮＰ ）
ランジスタの部分に改良を＼加えたものである。第３図
において、３１はｐ型０．６〜１．０Ω程度のｎ型エピ
タキシャル層で３〜４μｍの厚さに成長される。３４は
ｐ型高濃度の予備拡散領域で、エピタキシャル層３３表
面から形成されるｐ型窩濃度拡散領域３５と対をなし、
エピタキシャル層３３の分離を行なっている。この分離
領域３４．３５は酸化膜分離によって行なっても本発明
の効果は変らない。３６はｐ型の高濃度領域で、埋込み
領域３２の内側に設置せられ、分離領域３５と同時に形
成せられている。しかし、高濃度埋込領域３６の表面濃
度は、基板３１上の埋込領域３２が高＃度のためにかな
り下がっており、そのだめ上方への拡散は拡散領域３４
はど高くならない。３７は拡散領域３６と同時に形成さ
れたｐ１拡散領域で、コレクタ抵抗の削減のために設置
せられたものである。FIG. 3 shows a structural sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention. In this example, a vertical PNP transistor, a horizontal NPN transistor, and a high resistance element are integrated.
This is an improvement to the transistor part. In FIG. 3, numeral 31 is a p-type n-type epitaxial layer having a resistance of about 0.6 to 1.0 Ω and is grown to a thickness of 3 to 4 μm. Reference numeral 34 denotes a p-type high concentration preliminary diffusion region, which is paired with a p-type cavity concentration diffusion region 35 formed from the surface of the epitaxial layer 33;
The epitaxial layer 33 is separated. Even if these isolation regions 34 and 35 are formed by oxide film isolation, the effects of the present invention will not change. Reference numeral 36 denotes a p-type high concentration region, which is placed inside the buried region 32 and formed at the same time as the isolation region 35. However, the surface concentration of the high concentration buried region 36 is considerably lowered due to the high concentration of the buried region 32 on the substrate 31, so that the upward diffusion is limited to the diffusion region 34.
Don't get too high. Reference numeral 37 denotes a p1 diffusion region formed at the same time as the diffusion region 36, and is provided to reduce collector resistance.
３８ ハｎ＋の拡散領域でコレクタウオールを形成して
おり、埋込領域３２と接続される。３９は本発明にかか
わる主要拡散部で、低ドーズのイオン注入法により形成
され、シート抵抗値として通常のペース抵抗の２０ｏΩ
んに比し１桁以上高い２ＫＩＪ、７３〜４にΩ／口程度
のｐ−″領域である。38 A collector wall is formed by the Hn+ diffusion region, and is connected to the buried region 32. 39 is the main diffusion part related to the present invention, which is formed by a low-dose ion implantation method, and has a sheet resistance value of 20oΩ, which is the usual pace resistance.
2KIJ is more than an order of magnitude higher than that of 73 to 4, and is in the p-'' region of about Ω/mouth.
４０は同時に形成されたｐ−領域で、ここでは高抵抗部
となっている。４１はｎ型ウェルでｐ−領域３９上に形
成されＰＮＰ）ランジスタのペースとなる。Reference numeral 40 denotes a p- region formed at the same time, which here serves as a high resistance portion. Reference numeral 41 denotes an n-type well formed on the p- region 39 and serving as a base for a PNP transistor.
４２は約２００Ωん程度に形成されるｐ領域でＰ Ｎ
Ｐトランジスタのエミッタであり、ＮＰＮトランジスタ
のペース領域４３と同時に形成される。42 is a p region formed to about 200Ω, P N
It is the emitter of the P transistor and is formed simultaneously with the space region 43 of the NPN transistor.
４４は高抵抗部のコンタクト用拡散領域で、領域４２．
４３と同時形成される。４６はベース領域４１のコンタ
クト拡散領域であり、ＮＰＮトランジスタのエミッタ領
域４６と同時に形成される。Reference numeral 44 denotes a contact diffusion region of the high resistance portion, and the region 42.
Formed at the same time as 43. 46 is a contact diffusion region of the base region 41, which is formed simultaneously with the emitter region 46 of the NPN transistor.
４７はＮＰＮ）ランジスタのコレクタ３３のコンタクト
領域である。47 is a contact region of the collector 33 of the NPN transistor.
以上の明らかなように、本実施例では領域４２゜４１．
３９で縦型ＰＮＰ）ランジスタが形成され、領域４６．
４３．３３で横型ＮＰＮ）ランジスタが形成され、領域
４０．４４で高抵抗が形成されていることかわかる。こ
こで、縦型Ｐｔ’ＪＰ ）ランジスタの特性を次に説明
する。従来例で述べて来た３つの問題点すなわち、ベー
ス巾については、ペースであるｎ領域４１の形成が、低
濃度のｐ−領域３９内に形成されており、その濃度の制
御及び深さの制御がｐ−領域３９上から打込まれるイオ
ン注入によって精度良く定められる。すなわち、ベース
巾はｎ領域４１とｐ領域４２の拡散のみによって決定さ
れるので制御性が良い。つまり、第２図の場合は３つの
パラメータであったが本実施例では２つのパラメータで
ベース巾が決定される。As is clear from the above, in this embodiment, the area 42°41.
A vertical PNP) transistor is formed in region 46 .
It can be seen that a horizontal NPN transistor is formed in the region 43.33, and a high resistance is formed in the region 40.44. Here, the characteristics of the vertical type Pt'JP transistor will be explained next. Regarding the three problems mentioned in the conventional example, that is, regarding the base width, the n-region 41, which is the pace, is formed in the low-concentration p-region 39, and it is difficult to control the concentration and the depth. Control is precisely determined by ion implantation from above p- region 39. That is, since the base width is determined only by the diffusion of the n region 41 and the p region 42, controllability is good. In other words, the base width is determined by two parameters in this embodiment, whereas in the case of FIG. 2 there are three parameters.
また、ｎ領域４１は最終的にはイオン注入後のドライブ
インによって決められるため、上から下方向に濃度勾配
がついており、電界加速が行なわれる構造になっている
のでキャリアの走行速度が増大し、高速動作が可能とな
る。又、コレクタ表なるｐ領域３９の＃度は従来例と異
なり、ｐ−であるため、耐圧も高い。Furthermore, since the n-region 41 is ultimately determined by drive-in after ion implantation, it has a concentration gradient from top to bottom, and has a structure in which electric field acceleration is performed, so that the traveling speed of carriers increases. , high-speed operation is possible. Further, since the # degree of the p region 39 on the collector surface is p-, unlike the conventional example, the withstand voltage is also high.
以上の様に、本実施例に係る半導体集積回路装置は高耐
圧、高速、高密度縦型ＰＮＰトランジスタと高速の横型
ＮＰＮ）ランジスタと高抵抗を一体化構成出来るので高
速化ＩＣを実現する上で効果は極めて大きい。As described above, the semiconductor integrated circuit device according to this embodiment can integrate a high-voltage, high-speed, high-density vertical PNP transistor, a high-speed horizontal NPN) transistor, and a high resistance, which is useful for realizing a high-speed IC. The effect is extremely large.
次に、本実施例に係る縦型ＰＮＰ）ランジスタの深さ方
向不純物分布を第４図に示す。Next, FIG. 4 shows the impurity distribution in the depth direction of the vertical PNP transistor according to this example.
同図において、埋込み領域３２はたとえばＡ、（砒素）
のような拡散係数の小さいものを使用し、分離領域３６
はボロン等を使用することによシ、基板３１からの上方
拡散が図示したようになる。またエミッタ領域３６．ベ
ース領域４１及びコレクタ領域３９は、イオン注入法で
それぞれボロン。In the figure, the embedded region 32 is, for example, A, (arsenic)
Use a material with a small diffusion coefficient such as
By using boron or the like, upward diffusion from the substrate 31 occurs as shown in the figure. Also, the emitter region 36. The base region 41 and collector region 39 are each made of boron by ion implantation.
リン、ポロ７等を打込みその後の熱処理によシ形成され
る。同図であきらかなように、ベース領域４１の濃度傾
斜が大きく、ペースに電界傾斜が得られる。更に、コレ
クタ領域３９がきわめて低濃度であるため、ベース領域
４１の形成はその深さも、ペースへの不純物の添加像と
、エミッタ領域４２不純物量の両者により、実質的に定
められコレクタ領域３９の不純物濃度に依存することな
いので、その制御に困難性はない。また、本実施例に係
る構造では、高抵抗部分領□域４０と３９が共通プロセ
スであり、ＮＰＮ）ランジスタのベース領域４３がＰＮ
Ｐ）ランジスタのエミッタ領域４２及び高抵抗の抵抗領
域４０と共通プロセスで形成されるため、縦型ＰＮＰ）
ランジスタを形成するために、新たなプロセスとして、
単にベースとなるｎ影領域４１を形成するプロセスの追
加にすぎなく非常に簡便な構造となっている。It is formed by implanting phosphorus, PORO 7, etc. and subsequent heat treatment. As is clear from the figure, the concentration gradient in the base region 41 is large, and an electric field gradient is obtained at the pace. Furthermore, since the collector region 39 has an extremely low concentration, the depth of the base region 41 is substantially determined by both the amount of impurities added to the paste and the amount of impurities in the emitter region 42. Since it does not depend on impurity concentration, there is no difficulty in controlling it. In addition, in the structure according to this embodiment, the high resistance partial regions 40 and 39 have a common process, and the base region 43 of the NPN transistor is
P) Since it is formed in a common process with the transistor emitter region 42 and the high resistance resistance region 40, it is a vertical PNP)
As a new process to form transistors,
This is a very simple structure as it is simply an addition of the process of forming the n-shaded area 41 which is the base.
次に本発明の他の実施例について説明する。Next, other embodiments of the present invention will be described.
第５図は本発明の他の実施例を示す半導体回路装置の構
造断面図で、第３図と同一番号は同一部分を示す。FIG. 5 is a structural sectional view of a semiconductor circuit device showing another embodiment of the present invention, in which the same numbers as in FIG. 3 indicate the same parts.
第６図に示す実施例のものはＰＮＰ）ランジスタのベー
ス領域４１がコレクタウオール３８に接続されたものを
示す。本実施例においては、縦型ＰＮＰ ）ランジスタ
のベース領域４１はｎ影領域３３にまたがって設置され
コレクタウオール３８に接するごとく形成されているの
で抵抗値が減少することとなり、高周波特性が改善され
る。In the embodiment shown in FIG. 6, the base region 41 of a PNP transistor is connected to the collector wall 38. In this embodiment, the base region 41 of the vertical PNP transistor is installed across the n-shaded region 33 and is formed so as to be in contact with the collector all 38, so that the resistance value is reduced and the high frequency characteristics are improved. .
第６図は本発明の別の実施例を示すもので、縦型ＰＮＰ
）ランジスタ、横型ＮＰＮ）ランジスタ。FIG. 6 shows another embodiment of the present invention, in which a vertical PNP
) transistor, horizontal NPN) transistor.
高抵抗素子、ＩＬを一体化した半導体集積回路装置の構
造断面図を示すものである。1 is a structural cross-sectional view of a semiconductor integrated circuit device that integrates a high resistance element and an IL.
本実施例においては、第３図と同一番号は同一部分を示
し、４８，４９はｐ−領域で領域３９．４０と同一工程
により形成され同−深さに設置される。In this embodiment, the same numbers as in FIG. 3 indicate the same parts, and 48 and 49 are p-regions, which are formed by the same process as the regions 39 and 40 and are placed at the same depth.
５０．５１は領域４２，４３．４４と同一工程により形
成されたｐ型頭域である。この領域４８と６０は図示し
たごとく重ね合わされて形成されているが、これがＩＬ
素子のインジェクターとなっている。領域５１１Ｌ素子
のゲート領域となっている。領域４９は上向きのＮＰＮ
）ランジスタのベースとなっている。領域５２は！ Ｌ
素子での逆方向トランジスタのコレクタとなっている。50.51 is a p-type head region formed by the same process as regions 42, 43.44. These regions 48 and 60 are formed overlapping each other as shown, and this is the IL
It serves as an injector for the element. Region 511L serves as the gate region of the element. Region 49 is an upward NPN
) is the base of the transistor. Area 52 is! L
It serves as the collector of the reverse direction transistor in the device.
本実施例に係るＩＬは領域５０．５１を有するために、
１２Ｌの横型ＰＮＰ）ランジスタのインジェクタ電流が
少なくなるので、充分にＩ Ｌ縦型ＮＰＮ）ランジス
タに吸い込みが可能となる。Since the IL according to this embodiment has a region 50.51,
Since the injector current of the 12L horizontal PNP transistor is reduced, it is possible to draw sufficient current into the IL vertical NPN transistor.
すなわち、本実施例においては特性の優れたＩＬを何ら
プロセスを変更することなく一体化形成出来る効果があ
る。尚、ここで、縦型ＰＮＰ）ランジスダの特性は第３
図、第５図で示した場合と同様に高速性等を満足するも
のであることは云うまでもない。That is, this embodiment has the advantage that an IL with excellent characteristics can be integrally formed without changing the process. In addition, here, the characteristics of vertical PNP) Langisuda are the third
It goes without saying that the system satisfies the high-speed performance and the like as in the case shown in FIGS.
第７図は本発明の更に別の実施例を示す半導体集積回路
装置の構造断面図であり、第６図に示す実施例のＩ２Ｌ
部分の改良形である。同図において第６図と同一番号は
同一部分を示す。本実施例においては１２Ｌのｐ−領域
４９に領ｊｌｌＪ５２をおおう如く、ｎ型領域５３が形
成されていることが特長である。この領域６３は縦型Ｐ
ＮＰ ）ランジスタのベース領域４１と同一工程で形成
されたものである。縦って、本実施例においてはＩＬの
ｐ−領域４９の巾が狭くなるので、ＩＬの縦型ＮＰＮ
トランジスタのｈＦＥが増加することにナル。FIG. 7 is a structural cross-sectional view of a semiconductor integrated circuit device showing still another embodiment of the present invention, and the I2L of the embodiment shown in FIG.
This is an improved version of the part. In this figure, the same numbers as in FIG. 6 indicate the same parts. This embodiment is characterized in that an n-type region 53 is formed in the p- region 49 of 12L so as to cover the region jllJ52. This area 63 is vertical P
NP) is formed in the same process as the base region 41 of the transistor. Vertically, in this embodiment, the width of the p-region 49 of the IL is narrower, so that the vertical NPN of the IL is narrower.
Null that the hFE of the transistor increases.
以上、本発明によれば従来の様に縦型トランジスタのベ
ース中を定める方法が、たとえばマスク精度で決まった
り、プロセスの３〜４の拡散プロファイルのからみで定
まったりというように特定できず、かつ巾もバラツキが
大きいため、広めに設定せねばならない欠点がなく、本
発明は実質的に領域４１．４２の拡散のみでベース中が
決まり、制御性が良い。As described above, according to the present invention, the conventional method of determining the inside of the base of a vertical transistor cannot be determined, for example, because it is determined by mask accuracy, or it is determined by the diffusion profile of 3 or 4 of the process, and Since the width also varies widely, there is no disadvantage that it must be set wide, and in the present invention, the base is substantially determined only by the diffusion of the regions 41 and 42, and the controllability is good.
父、本発明での縦型トランジスタのコレクタカ領域３９
で形成されるので、コレクタの濃度が高く、ベース長を
狭くした場合耐圧劣化をおこす欠点が生じない。更に、
本発明の縦型トランジスタはベースは領域４１で形成さ
れるので濃度傾Ｒがあり、電界加速され高速化を実現出
来る。また、本発明は、他のＮＰＮ素子、Ｉ２Ｌ・、高
抵抗素子とも、同一工程で製作出来しかもこれらの素子
特性に悪影響を与えない利点を有する。Father, collector region 39 of vertical transistor in the present invention
Since the collector has a high concentration, there is no drawback that breakdown voltage deterioration occurs when the base length is narrowed. Furthermore,
Since the base of the vertical transistor of the present invention is formed in the region 41, there is a concentration gradient R, and electric field acceleration can be achieved to achieve high speed. Further, the present invention has the advantage that other NPN elements, I2L, and high resistance elements can be manufactured in the same process without adversely affecting the characteristics of these elements.
以上、本発明は簡単な構成により高速化半導体集積回路
装置を実現出来るので工業的価値が高い。As described above, the present invention has high industrial value because it can realize a high-speed semiconductor integrated circuit device with a simple configuration.
第１図及び第２図は従来の半導体集積回路装置の構造断
面図、第３図は縦型ＰＮＰ ）ランジスタ、横型ＮＰＮ
）ランジスタ及び高抵抗素子を一体化した本発明の実施
例に係る半導体集積回路装置の構造断面図、第４図は第
３図の縦型ＰＮＰ ）ラン゛ ジスタの不純物分布図、
第６図は第３図における縦型ＰＮＰ ）ランジスタを改
良した本発明の他の実施例を示す構造断面図、第６図及
び第７図は第３図のものに１２Ｌを一体化した本発明の
別の実施例に係る構造断面図を示す。
３６・−・・・・ｐ＋埋込領域、３９・・・・・・ｐ−
コレクタ領域、４ｏ−・・・・・ｐ−抵抗領域、４１・
・・・・・ｎ型ベース領域、４２・・・・・・ｐ型エミ
ッタ領域、４３・・・・−・ｐ型ベース領域、４４・・
・・・・抵抗コンタクト領域、５０・・・・・・Ｉ２Ｌ
インジェクタ領域、５１・・・・・・１２Ｌゲート領域
、５２・・・・・・ＩＬコレクタ領域、６３・・・・・
・ｎ型領域。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第２
図Figures 1 and 2 are structural cross-sectional views of conventional semiconductor integrated circuit devices, and Figure 3 is a vertical PNP transistor, a horizontal NPN transistor, and a horizontal NPN transistor.
) A structural sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention in which a transistor and a high resistance element are integrated, FIG. 4 is a vertical PNP shown in FIG. 3.) Impurity distribution diagram of a transistor,
FIG. 6 is a structural sectional view showing another embodiment of the present invention which is an improved version of the vertical PNP transistor shown in FIG. FIG. 5 shows a structural cross-sectional view according to another embodiment of the invention. 36...p+ embedded area, 39...p-
Collector region, 4o-...p-resistance region, 41.
...N type base region, 42...P type emitter region, 43...P type base region, 44...
...Resistive contact area, 50...I2L
Injector area, 51...12L gate area, 52...IL collector area, 63...
・N-type region. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
figure
Claims (1)
型の半導体層と、前記半導体基板と前記半導体層界面に
形成さ扛た他方導電型筒１の埋込領域と、前記第１の埋
込領域上に形成された一方導電型高濃度第２の埋込領域
と、前記半導体層表面から前記第２の埋込領域に達する
様に形成さ扛た一方導電型低濃度コレクタ領域と、前記
コレクタ領域表面から形成さｎた他方導電型ベース領域
と、前記ベース領域内に形成さｎた一方導電型エミッタ
領域とを備え、前記エミッタ、ベース、コレクタ領域に
より縦型トランジスタが構成さすることを特徴とする半
導体集積回路装置。 （２）一方導電型の半導体基板上に形成さｎ互いに分離
さｎた他方導電型の第１．第２．第３の領域と、前記第
１．第２の領域表面からそｎぞｎ同時形成さｎだ一方導
電型の低濃度第４ν第６の領域と、前記第４の領域表面
から形成さ扛た他方導電型の第６の領域と、前記第６２
第６゜第３の領域表面からそｎぞｎ同時形成さ扛た一方
導電型の第７．第８．第９の領域と、前記第６、第９の
領域表面からそ扛ぞｎ同時形成さｒた他方導電型の第１
０．第１１の領域とを備え、前記第４．第６を第７の領
域で縦型トランジスタを、前記第５．第８の領域で抵抗
を、前記第３、第９を第１１の領域で横型トランジスタ
を構成したことを特徴とする半導体集積回路装置。 （′４ 第１の領域と半導体基板界面に他方導電型の第
１２の領域が形成さｎており、前記第１の領域表面から
前記第１２の領域に達する如く他方導電型の第１３の領
域が形成さｎていることを特徴とする特許請求の範囲第
２項に記載の半導体集積回路装置。 （４）第６の領域と第１３の領域とが接続されているこ
とを特徴とする特許請求の範囲第３項に記載の半導体集
積回路装置。 （６）一方導電型の半導体基板上に形成さｎ互いに分離
さ扛た他方導電型の第１．第２．゛第３．第４の領域と
、前記第１．第２の領域表面からそｎぞｎ同時形成さ扛
た一方導電型の低濃度第６゜第６の領域と、前記第３の
領域表面から前記第６、第６の領域と同時形成さｎ一方
導電型の低濃度第７．第８の領域と、前記第６の領域表
面から形成さｎた他方導電型の第ｉ域と、前記第９．第
６．第７．第８．第４の領域表面がらそｎぞｎ同時形成
・さｎた一方導電型の第１０゜第１１．第１２．第″Ｆ
−３．第１４の領域と、前記第９．第８．第１４の領域
表面からそｎぞれ同時形成さｎた他方導電型の第１６．
第１６゜第１７の領域とを備え、前記第１．第２．第３
゜第４の領域内にそｎぞｎ縦型トランジスタ、抵抗、注
入論理回路、横型トランジスタが構成さｎることを特徴
とする半導体集積回路装置。 （６）第１２．第１３の領域が対向位置において第３の
領域に突出形成さｎていることを特徴とする特許請求の
範囲第６項に記載の半導体集積回路装置。 Ｃ７） 第８の領域には第９の領域と同時形成さｎた
他方導電型の第１８の領域があり、前記第１８の領域内
に第１６の領域が形成さ扛ていることを特徴とする特許
請求の範囲第６項又は第６項に記載の半導体集積回路装
置。 （尿下俊白）[Scope of Claims] (1) A semiconductor layer of the other conductivity type formed on a semiconductor substrate of one conductivity type, and embedding of a cylinder 1 of the other conductivity type formed at the interface between the semiconductor substrate and the semiconductor layer. a high concentration second buried region of one conductivity type formed on the first buried region; and one conductive region formed on the semiconductor layer surface to reach the second buried region. a low concentration type collector region, a base region of the other conductivity type formed from the surface of the collector region, and an emitter region of the one conductivity type formed within the base region; 1. A semiconductor integrated circuit device comprising a type transistor. (2) first semiconductor substrates of one conductivity type formed on a semiconductor substrate of the other conductivity type and separated from each other; Second. a third area; and the first area. a low concentration 4v sixth region of one conductivity type formed simultaneously from the surface of the second region, and a sixth region of the other conductivity type formed from the surface of the fourth region; Said 62nd
The 7th conductivity type is simultaneously formed from the surface of the 6th and 3rd regions. 8th. a ninth region and a first conductivity type of the other conductivity formed simultaneously from the surfaces of the sixth and ninth regions;
0. an eleventh region; The sixth and seventh regions are vertical transistors; A semiconductor integrated circuit device characterized in that an eighth region constitutes a resistor, and the third, ninth and eleventh regions constitute a lateral transistor. ('4) A twelfth region of the other conductivity type is formed at the interface between the first region and the semiconductor substrate, and a thirteenth region of the other conductivity type extends from the surface of the first region to the twelfth region. (4) A patent characterized in that the sixth region and the thirteenth region are connected. Semiconductor integrated circuit device according to claim 3. (6) First, second, third and fourth semiconductor substrates of one conductivity type formed on a semiconductor substrate of the other conductivity type and separated from each other. A low concentration 6th region of one conductivity type formed simultaneously from the surface of the first and second regions; a sixth region of a low concentration of one conductivity type; a low concentration seventh and eighth region of one conductivity type formed simultaneously with the region, an i-th region of the other conductivity type formed from the surface of the sixth region, and the ninth, sixth and eighth regions formed from the surface of the sixth region. 7. 8th. The surface of the 4th region is simultaneously formed with conductivity type 10°, 11th, 12th, "F".
-3. the 14th area; and the 9th area. 8th. A 16th region of the other conductivity type was simultaneously formed from the surface of the 14th region.
a 16th and a 17th area; Second. Third
゜A semiconductor integrated circuit device characterized in that a vertical transistor, a resistor, an injection logic circuit, and a horizontal transistor are respectively configured in a fourth region. (6) 12th. 7. The semiconductor integrated circuit device according to claim 6, wherein the thirteenth region protrudes from the third region at an opposing position. C7) The eighth region has an 18th region of the other conductivity type formed simultaneously with the 9th region, and the 16th region is formed within the 18th region. A semiconductor integrated circuit device according to claim 6 or 6. (Urine Shita Shunpaku)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57065925A JPS58182260A (en) | 1982-04-19 | 1982-04-19 | Semiconductor integrated circuit device |
| DE8383103726T DE3361832D1 (en) | 1982-04-19 | 1983-04-18 | Semiconductor ic and method of making the same |
| EP83103726A EP0093304B1 (en) | 1982-04-19 | 1983-04-18 | Semiconductor ic and method of making the same |
| US07/124,423 US4826780A (en) | 1982-04-19 | 1987-11-23 | Method of making bipolar transistors |
| US07/295,380 US5066602A (en) | 1982-04-19 | 1989-01-10 | Method of making semiconductor ic including polar transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57065925A JPS58182260A (en) | 1982-04-19 | 1982-04-19 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58182260A true JPS58182260A (en) | 1983-10-25 |
| JPH0561775B2 JPH0561775B2 (en) | 1993-09-07 |
Family
ID=13301030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57065925A Granted JPS58182260A (en) | 1982-04-19 | 1982-04-19 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58182260A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6259081A (en) * | 1985-09-09 | 1987-03-14 | Ricoh Co Ltd | Thermal recording material |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS515973A (en) * | 1974-07-04 | 1976-01-19 | Nippon Electric Co | |
| JPS52104076A (en) * | 1976-02-27 | 1977-09-01 | Sony Corp | Semiconductor unit |
| JPS53134374A (en) * | 1977-04-28 | 1978-11-22 | Sony Corp | Semiconductor device |
-
1982
- 1982-04-19 JP JP57065925A patent/JPS58182260A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS515973A (en) * | 1974-07-04 | 1976-01-19 | Nippon Electric Co | |
| JPS52104076A (en) * | 1976-02-27 | 1977-09-01 | Sony Corp | Semiconductor unit |
| JPS53134374A (en) * | 1977-04-28 | 1978-11-22 | Sony Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6259081A (en) * | 1985-09-09 | 1987-03-14 | Ricoh Co Ltd | Thermal recording material |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0561775B2 (en) | 1993-09-07 |
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