JPS63179564A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten the process of manufacturing, by making the structure of a bipolar element in the vicinity of an emitter similar to the structure of an N-channel MOS part in the vicinity of a gate. CONSTITUTION:A polysilicon film 202 is provided on an emitter region 15 of a bipolar type transistor. An insulator film is provided on the side part of the polysilicon film 202. A silicide film 16 is provided on a base region 11 of the bipolar transistor. A polysilicon film 201 is formed on the gate of an N- channel MOS at the same time as the polysilicon film 202. A side wall 17 of the insulating film is formed on the side part of the polysilicon film 201. The silicide films 16 are provided on the polysilicon film 201 of the gate and on the upper parts of the polysilicon film 202 of the emitter and source and drain regions 6, 7, 9 and 10. Since the N-channel MOS and the bipolar transistor have the approximately same structure, the manufacturing process can be shortened.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device consisting of a p-channel MOS element and an n-channel MOS element.
The present invention relates to a so-called Bi-CMOS integrated circuit device in which a MOS element and a bipolar element are formed on the same chip.

[Conventional technology]

In general, bipolar elements have a large drive capacity per occupied chip area and have high accuracy in processing analog quantities, but have drawbacks such as a low degree of integration and high power consumption. On the other hand, CMOS elements have the characteristics of low power consumption and high degree of integration. Therefore, it is effective to incorporate a CMOS element that compensates for the above-mentioned drawbacks of bipolar elements on a chip mainly composed of bipolar elements.A typical example is a memory cell section composed of a CMOS element, a sense amplifier, and a CMOS element. Static RAM (Random Access Memories) whose input/output circuits are composed of bipolar elements
ry)) has already been commercialized, and gate array LSIs using Bi-0MOS are also on sale.

Among such conventional Bi-CMOS integrated device devices, a method of manufacturing one using an npn transistor as a bipolar device will be described with reference to FIG.

First, as shown in FIG. 3(A), a p-type silicon substrate 1
After forming an n-type buried layer 2 with a high impurity concentration thereon, an epitaxial layer 3 with an n-minimum impurity concentration is grown.

Next, selective oxidation is performed using an oxidation-resistant film (not shown) as a mask to form a thick oxide film 101 for electrically isolating the element forming portions in the epitaxial layer 3. Here, a case will be described in which an oxide film isolation method is used, but the same can be said of other isolation methods such as a pn junction isolation method. Furthermore, a p-type impurity is diffused into the epitaxial layer 3 of the MOS transistor forming part to form a p-type impurity.
- After forming the well layer 4 and growing the gate oxide film 102, an n-type high impurity concentration polycrystalline silicon film 201 which will become the gate electrode is formed. Here, as the gate electrode,
In addition to polycrystalline silicon films, silicide films (MoSi
t, WS iz ) and their composite membranes may also be used.

Next, as shown in FIG. 3B, using the resist film 301 and the gate electrode 201 as a mask, a high n-type impurity concentration is implanted into the source layer 6 of the n-channel MOS. A drain layer 7 and a collector electrode extraction layer 5 are formed.

Next, as shown in FIG. 3(C), a new resist film 3 is formed.
02 and the gate electrode 201 as a mask, a p-type impurity concentration is implanted to form the source layer 9.02 of the p-channel MOS. A drain layer 10 and an external base layer 8 are formed.

Next, as shown in FIG. 3(D), a new resist Jl! (not shown) is used as a mask to implant a P-type paper impurity concentration, and a vaporization film 401 such as a phosphorus glass film is implanted.
is deposited, and annealing is performed to bake and tighten the passivation 401, thereby forming the active base layer 11a. Through this annealing, each source layer, drain layer, external base layer,
The collector electrode extraction layers are simultaneously activated to form respective diffusion layers. Here, although each may be annealed individually, it is generally performed all at once to simplify the process.

Next, as shown in FIG. 3(E), an n-channel MOS
Contacts for taking out the electrodes of the source layer 6a and drain layer 7a are formed, and the n-highest impurity layer 12.1 is formed here.
3 is formed by diffusion.

This is because it is desirable to form the source/drain layer as shallow as possible in order to improve the performance of the n-channel MOS transistor, and the impurity used is arsenic (As) with a small diffusion coefficient. If it becomes too shallow, abnormal diffusion of the electrode material due to distortion of the thick oxide film 101 in the feed section or the edge of the contact hole will cause a short circuit with the substrate across the junction.
This is to form a deep electrode extraction layer by further injecting and diffusing an impurity such as phosphorus (P) having a large diffusion coefficient into the contact portion at a hole concentration.

Next, as shown in FIG. 3(F), a window is opened in the passivation film 401 at least for the purpose of forming an emitter layer, and an n-type hole impurity concentration (As) is introduced. This will be the contact window for This is because the emitter layer 15 needs to be shallow and narrow in order to improve the performance of the bipolar transistor. On the other hand, in order to ensure driving force and reduce base resistance, the length of the emitter is slightly longer, and the emitter generally has an elongated rectangular planar pattern. Further, in order to reduce the influence of strain on the thick oxide film 101, the emitter layer is formed away from the oxide film. Furthermore, M.O.
S) A high degree of integration is required for transistors, and the source/drain contacts have a minimum pattern of squares and have almost no distance from the thick oxide film.

Finally, as shown in FIG. 3(G), at least the source contact, drain contact, base contact, and gate contact (not shown) of the p-channel MOS are opened and a low-resistance metal wiring, such as aluminum (A f ) by electrodes in n-channel MOS (source 501 of n-channel MOS. drain 502 of n-channel O8. base 503. emitter 5504, collector 50B, source 506 of p++7-channel MoS. drain 507 of p-channel MOS)
form.

[Problem that the invention seeks to solve]

Even if it were possible to standardize some of the processes for conventional Bi-CMOS integrated circuit devices, the construction period would be longer because it includes many bipolar and 0MOS processes, which would ultimately lead to lower yields. It has problems that lead to

Furthermore, as mentioned above, in transistors, especially bipolar transistors, the junctions become deep because they are formed using methods such as direct ion implantation into impurities.
This makes high-speed operation unsuitable. Also, 0M
Even in OS transistors, it is possible to further increase the speed by lowering the resistance between the gate electrode and the source/drain electrodes.

The present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor integrated circuit device that can shorten process steps and operate at high speed.

[Means for solving problems]

In the semiconductor integrated circuit device according to the present invention, the structure near the emitter of the bipolar element and the structure near the gate of the n-channel MOS section are made similar, thereby making most of the manufacturing steps common. In addition, the structure is a polysilicon emitter, LDD (Liyht
ly Doped Drain), and by using silicide to lower the resistance or make the cell finer, it is possible to perform microfabrication and shallow junctions, which are necessary for high-speed operation and high integration of elements. .

[Effect]

In the semiconductor integrated device according to the present invention, the emitter of the bipolar part is formed by diffusion from polysilicon, and by forming a side wall with, for example, a silicon oxide film on the side wall and further forming silicide, the emitter resistance and The base resistance can be reduced. In particular, the emitter and base are insulated only by the sidewalls of silicon oxide film, but such a state cannot be obtained using lithography, and the base resistance can only be achieved by adopting such a configuration. will be reduced.

Further, this structure is similar to the structure of the gate electrode portion of an n-channel MOSI transistor, and the only difference between the two is the presence or absence of a gate oxide film. Therefore, in a bipolar transistor, if the silicon oxide film is removed only in the bipolar region before forming polysilicon for base diffusion layer formation and emitter diffusion, the n
A channel MOS and a bipolar transistor can be formed, which greatly contributes to shortening the process. In addition, in the MOS transistor part, the source/drain part is silicided using sidewalls, so the distance between the gate and the source/drain is substantially shortened, and accordingly, the source/drain diffusion layer This means that a low concentration is sufficient, and as a result, when miniaturization progresses, short channel effects are less likely to occur.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In the embodiment, a case will be described in which an npn type bipolar transistor is used. In FIG. 1, 1 is a semiconductor substrate, 2 is an n highest concentration impurity layer formed on one surface of the semiconductor substrate, 3 is an epitaxial layer, 4 is a p-type well layer,
5 is the collector diffusion layer of the bipolar transistor, 6 is the n
Drain diffusion layer of channel MOS, 7 is source diffusion layer of n-channel MOS, 9 is drain diffusion layer of p-channel MOS, 10 is source diffusion layer of p-channel MOS, 11 is base diffusion layer of bipolar transistor, 15
is an emitter layer of a bipolar transistor, 16 is a metal silicide layer, 101 is a thick silicon oxide film for insulation, 1
02 is a silicon oxide film, 201 is a polysilicon used for the gate of MOS, 202 is polysilicon for emitter diffusion of a bipolar transistor, 401 is a silicon oxide film for connecting the transistor and wiring, 501 is an n-channel MOS A drain electrode, 502 a source electrode of an n-channel MOS, 503 a base electrode of a bipolar transistor, 504 an emitter electrode of the bipolar transistor, and 505 a collector electrode of the bipolar transistor.

Next, an example of a method for manufacturing a semiconductor integrated circuit device having the above configuration will be described with reference to the drawings. In FIG. 2(A), the process up to the device isolation process of the Bi-CMOS device is performed using a known manufacturing method, a silicon oxide film 102 that will become the gate oxide film is formed by thermal oxidation, and a region that will become the base of the bipolar device is formed. The resist 601 is patterned to form holes, and boron is implanted. Next, in order to diffuse this boron, driving is performed to form a base diffusion layer 11.

Next, a part of the bipolar transistor (corresponding to 103) is removed by lithography, and the silicon oxide film 10 is removed.
Remove 2. However, in this case, the silicon oxide film becomes the gate oxide film, so it should not be removed in the n-channel and p-channel MOS parts (see Figure 2 (B)).
). Subsequently, polysilicon 200 is deposited on the front surface. Furthermore, in order to make the polysilicon resistive in the gate part of the n-channel MOS and to introduce impurities for forming an emitter into the polysilicon in advance, arsenic ions are implanted using the resist 602 that hides the p-channel part as a mask. Figure 2 (C)).

Furthermore, in order to form the source and drain of the n-channel MOS, resist patterns 603 and 60 are formed that hide the base part of the bipolar transistor and the p-channel MOS part.
4 as a mask, perform arsenic ion implantation (Fig. 2 (
D)). After that, driving is performed, thereby causing the collector diffusion layer 5 of the bipolar transistor. Emitter diffusion layer 1
5. Drain diffusion layer of n-channel MOS6. A source diffusion layer 7 is formed. Next, in order to form the source and drain of the p-channel MOS section, a resist pattern 605 that hides the bipolar transistor and the n-channel MOS section is formed.
Using the mask as a mask, boron ion implantation is performed (Figure 2 (
E). After that, driving is performed to form the drain diffusion layer 11 and source diffusion layer 10 of the p-channel MOS, and a silicon oxide film is deposited on the entire surface by CVD.
As a result, side walls of the silicon oxide film 17 are left on the sides of the emitter polysilicon 202 and on the sides of the gate polysilicon 201 in the n-channel MOS and p-channel MOS (FIG. 2(F)).

Subsequently, after depositing a high melting point metal (Ti, Mo, W, Pt, etc.), heat treatment is performed in an inert atmosphere to convert the high melting point metal into silicide. In this case, silicide 16 is formed because silicide is not formed in the thick silicon oxide film 101 for element insulation or in the silicon oxide film 103 for insulation between the base and collector of the bipolar transistor section. The parts can be easily etched selectively. Next, when the unreacted high melting point metal is removed, silicide 16 remains at the electrode portion of each transistor (FIG. 2(G)). Further, a silicon oxide film 401 is deposited by CVD or the like in order to insulate the wiring from being formed later (FIG. 2(H)). After that, contact holes are formed, aluminum wiring is applied, and the Bi-CMO
Complete the S element.

Note that in the above embodiment, the oxide film separation type B i
Although the -CMOS device is taken as an example, the present invention is not limited thereto, and similar effects can be obtained even when applied to a Bi-CMOS device using PN isolation.

〔Effect of the invention〕

As explained above, according to the semiconductor integrated circuit device according to the present invention, since the n-channel MOS and the bipolar transistor have almost the same structure, the manufacturing process can be shortened, and the construction period can be shortened accordingly. At the same time, the yield of devices will also improve as the construction period is shortened.

In addition, by using silicide, the distance between the base and emitter of a bipolar transistor and the distance between the gate and source and drain of a MOS can be substantially shortened without narrowing the wiring spacing. This has the effect of making it possible to respond to miniaturization and microfabrication.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS. Process diagrams, FIGS. 3(A) to 3(art) are process diagrams showing the manufacturing process of a conventional semiconductor integrated circuit device. 1 is a semiconductor substrate, 6 is a drain diffusion layer of an n-channel MOS, 7 is a source diffusion layer of an n-channel MOS, and 9 is a p
A channel MOS drain diffusion layer, 10 a p-channel MOS source diffusion layer, 15 an emitter diffusion layer, 16
is a silicide film, 17 is an insulating film sidewall, 20
1.202 is a polysilicon film. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] (1) In a semiconductor device including at least a bipolar transistor and an n-channel MOS transistor on the same semiconductor substrate, a polysilicon film provided on the emitter region of the bipolar transistor, and a polysilicon film provided on the emitter region of the bipolar transistor; an insulating film provided on the side of the bipolar transistor, a silicide film provided on the base region of the bipolar transistor, and a polysilicon film provided on the emitter region of the bipolar transistor on the gate of the n-channel MOS at the same time. a polysilicon film formed on the polysilicon film, a sidewall of an insulating film formed on the side of the polysilicon film, a silicide film provided on the polysilicon of the gate, the polysilicon of the emitter, and the source/drain region. A semiconductor integrated circuit device comprising: (2) The semiconductor integrated circuit device according to claim 1, wherein the insulating film is a silicon oxide film. (3) The semiconductor integrated circuit device according to claim 1, wherein the silicide film is a titanium silicide film. (4) The semiconductor integrated circuit device according to claim 1, wherein the silicide film is a molybdenum silicide film.