JPH04206660A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the number of manufacturing steps of an element isolating region of a semiconductor substrate by forming the element isolating region only from an impurity diffused layer. CONSTITUTION:A P-well 11 is formed on a partial region of an N-type substrate 10 having a complementary insulating gate type field effect transistor (CMOS FET), and a first conductivity type, such as a first conductivity type impurity diffused layer 12 of an element region by P-type impurity diffusing... and a first conductivity type impurity diffused layer 15... and 15' for an element isolating region are simultaneously formed on the surface layer of a substrate. Then, a second conductivity type such as a second conductivity type impurity diffused layer 14 of an element region by N-type impurity diffusing... a second conductivity type impurity diffused layer 13... and 13' for an element isolating region are simultaneously formed. The element isolating regions are fixed to a power source or a ground potential. Thus, the element isolating region is formed of the impurity diffused layer thereby to reduce the number of manufacturing steps and to prevent generation of a latchup.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to an element isolation region of a semiconductor device suitable for low voltage driving and a method for forming the same. .

(Prior Art) FIG. 3 shows a cross-sectional structure of a part of an example of a semiconductor integrated circuit having a conventional CMO3FET (complementary insulated gate field effect transistor), where 30 is an N
type semiconductor substrate, 31 is a P well provided in a part of the N type substrate, 32... is a field oxide film for an element isolation region selectively formed on the surface layer of the substrate, 33... is a An impurity diffusion layer for preventing inversion is formed under the bottom surface of the field oxide film, and 34 is a P1 type impurity diffusion layer for the source and drain of a P channel transistor, which is selectively formed on the surface layer of the N type substrate. , 35... are N" type impurity diffusion layers for the source and drain of the N-channel transistor selectively formed on the surface layer of the P-well, 36 is a gate insulating film on the substrate surface, and 37... 0 MO5FET polysilicon gate electrode, 38 interlayer insulating film, 39...
is the source wiring or drain wiring of the 0MO5FET.

As mentioned above, the element isolation region of a conventional semiconductor device is
Usually, a field oxide film 32 and an impurity diffusion layer 33 for preventing inversion formed under the bottom surface of the field oxide film 32 are used.

However, the device isolation region with such a structure is difficult to obtain using LOCO, which performs patterning and field oxidation of the device isolation region.
5 (selective oxidation technology), there is a drawback that the number of manufacturing steps is large.

Further, in general, as a peculiar phenomenon in a semiconductor device in which a CMOS FET is formed, if current flows into the substrate for some reason, the substrate potential floats, resulting in latch-up.

(Problems to be Solved by the Invention) As described above, the conventional semiconductor device has a problem in that the number of manufacturing steps for the element isolation region is large, and when a CMO3FET is formed, a latch-up phenomenon is likely to occur.

The present invention has been made to solve the above-mentioned problems, and its purpose is to reduce the number of manufacturing steps for element isolation regions.
It is an object of the present invention to provide a semiconductor device suitable for driving with a low power supply voltage that is lower than the electrical breakdown voltage of the junction between an impurity diffusion layer in an element region and an impurity diffusion layer for an element isolation region.

Another object of the present invention is to provide a semiconductor device that can prevent the latch-up phenomenon of an 0MO5FET, and a manufacturing method that requires an extremely small number of manufacturing steps.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor device of the present invention includes an impurity diffusion layer in an element region formed in a surface layer of a semiconductor substrate, and a substrate surface layer in at least a part of a region on a semiconductor chip. an impurity diffusion layer for an element isolation region, which is formed adjacent to the impurity diffusion layer of the element region, is of a conductivity type opposite to that of the impurity diffusion layer of the element region, and has an impurity concentration equivalent to that of the impurity diffusion layer; The impurity diffusion layer for the element isolation region is fixed to a power supply potential or a ground potential.

(Function) Since the element isolation region consists of an impurity diffusion layer, the number of manufacturing steps for the element isolation region can be reduced. In addition, the impurity diffusion layer for the element isolation region is formed adjacent to the impurity diffusion layer in the element region, has a conductivity type opposite to that of the impurity diffusion layer in the element region, and has an impurity concentration equivalent to that of this impurity diffusion layer. and is fixed at the power supply potential or ground potential, so the low power supply voltage is lower than the electrical withstand voltage (for example, 5 to 6 V) at the junction between the impurity diffusion layer in the element region and the impurity diffusion layer for the element isolation region. (For example, it is suitable for a semiconductor device driven at 5 .ANG. or 3.3 .ANG. or less).

In particular, in a semiconductor device having 0MO5FET,
The first conductivity type impurity diffusion layer in the element region and the first conductivity type impurity diffusion layer for the element isolation region can be simultaneously formed by the first conductivity type impurity diffusion, and the second conductivity type impurity diffusion layer can form the first conductivity type impurity diffusion layer in the element region at the same time. Since the two-conductivity type impurity diffusion layer and the second-conductivity type impurity diffusion layer for the element isolation region can be formed at the same time,
The number of manufacturing steps for the element isolation region is extremely small. In addition, they are formed in large numbers distributed in the element isolation region or the surface layer of the substrate, and each is fixed to the power supply potential or ground potential, so even if current flows into the substrate for some reason, the substrate potential remains stable and launches. This prevents the occurrence of the "up" phenomenon.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a cross-sectional structure of a part of a semiconductor integrated circuit having a CMOS FET, in which 10 is an N-type semiconductor substrate, 11 is a P-well (
(substrate for N-channel transistor). 12...
13... are P'-type impurity diffusion layers for the source and drain of P-channel transistors selectively formed on the surface layer of the N-type substrate, and 13... are the P-type impurity diffusion layers between the P-channel transistors (that is, between the device regions). This is an N" type impurity diffusion layer for an element isolation region formed on the surface layer of the substrate, and is formed adjacent to the P+ type impurity diffusion layer 12 for the source/drain of the P channel transistor. .

13゛ is an element isolation layer formed on a part of the surface layer of the N-type substrate.
This is an N+ type impurity diffusion layer for the substrate electrode, and is formed adjacent to the P' type impurity diffusion layer 12 for the source/drain of some P channel transistors. 14... are N-type impurity diffusion layers for the sources and drains of N-channel transistors selectively formed in the surface layer of the P-well, and 15... are N-type impurity diffusion layers between N-channel transistors (that is, between element regions). ) is a P'' type impurity diffusion layer for an element isolation region formed on the surface layer of the substrate, and is formed adjacent to the N'' type impurity diffusion layer 14 for the source/drain of the N channel transistor. Been (Aru)

15゛ is an element isolation area formed in a part of the P-well surface layer.
This is a P゛ type impurity diffusion layer for substrate electrodes, and is formed adjacent to the N+ type impurity diffusion layer 14 for sources and drains of some N channel transistors, as well as for the element isolation and substrate electrodes. It is formed adjacent to the N+ type impurity diffusion layer 13°.

And an N+ type impurity diffusion layer 1 for the element isolation region.
3... and 13'' are each fixed to the power supply potential Vcc, and P+ type impurity diffusion layers 15... and 15° for element isolation regions are each fixed to the ground potential VSS.

In addition, 17 is a gate insulating film on the substrate surface, 18... is a polysilicon gate electrode of CMOS FjT, for example,
19 is an interlayer insulating film, and 20 . . . are source wirings or drain wirings of CMOSFETs or element isolation region potential supply wirings.

When manufacturing an integrated circuit having a CMOS FET as described above, a P well (N
A substrate 11 for channel transistors is formed, and impurities of the first conductivity type (for example, P type) are diffused into the surface layer of the semiconductor substrate to form source/drain regions 12 of the P channel transistors and for element isolation regions. a step of simultaneously forming P+ type impurity diffusion layers 15... and 15゛;
A second conductivity type (for example, N type) impurity is diffused into the surface layer of the semiconductor substrate to form the source of the N channel transistor.
and a step of simultaneously forming drain regions 14... and N+ type impurity diffusion layers 13... and 13' for element isolation regions, in a surface layer portion of at least a part of the semiconductor substrate, P-channel transistor source and drain regions 12.

and adjacent element isolation regions 13 . . . , 13° made of N-type impurity diffusion layers, and source/drain regions 142 .・Element isolation region 1 consisting of and an adjacent P” type impurity diffusion layer
5..., 15' are formed.

The impurity concentration of the source/drain regions 12 of the P channel transistors and the P+ type impurity diffusion layers 15, 15' for element isolation regions is, for example, approximately 5.
.times.10@15 cm@-3, and the impurity concentration in the source/drain regions 14 of the N-channel transistors and the N'' type impurity diffusion layers 13 for element isolation regions 13 DEG is approximately 5.times.10@15 cm@-3.

In the semiconductor integrated circuit having the above structure, since the element isolation region is made of an impurity diffusion layer, the number of manufacturing steps for the element isolation region can be reduced. In particular, in a semiconductor integrated circuit having a CMOS FET, impurity diffusion layers 12 of the first conductivity type (for example, P type) in the element region are diffused by impurity diffusion of the first conductivity type (for example, P type).
- and first conductivity type impurity diffusion layer 15 for element isolation region.
... and 15' can be formed at the same time, and by diffusing the second conductivity type (for example, N type) impurity, the second conductivity type impurity diffusion layer 14 in the element region and the second conductivity type impurity for the element isolation region can be formed. Since the diffusion layers 13... and 13' can be formed at the same time, the number of manufacturing steps for the element isolation region can be extremely reduced.

Further, in the semiconductor integrated circuit having the above configuration, the impurity diffusion layer for the element isolation region is formed adjacent to the impurity diffusion layer in the element region, and is of a conductivity type opposite to that of the impurity diffusion layer in the element region. Since it has the same impurity concentration as the diffusion layer and is fixed to the power supply potential VCC or the ground potential VSS, the electrical withstand voltage ( It is suitable for driving with a low power supply voltage (for example, 5V or 3.3V or less) below (eg, 5V to 6V).

Furthermore, since the semiconductor integrated circuits having the above structure are formed in large numbers in a distributed manner in the element isolation region or the surface layer of the substrate, and are each fixed to the power supply potential VCC or the ground potential VSS, current may flow to the substrate for some reason. Even if the current flows in, the substrate potential remains stable, and the latch-up phenomenon of the CMOS FET is prevented from occurring.

In the semiconductor integrated circuit of the above embodiment, the impurity diffusion layer for the element isolation region is formed adjacent to the impurity diffusion layer of the element region. In this case, it is not necessary to form an impurity diffusion layer for the element isolation region.

In addition, when high breakdown voltage characteristics are required in the input or output circuits of a semiconductor integrated circuit, high breakdown voltage characteristics can be achieved by increasing the distance between the impurity diffusion layer for the element isolation region and the impurity diffusion layer in the element region. can be easily achieved. In other words, as shown in FIG. 2, a part of the impurity diffusion layer for the element isolation region may be formed apart from the impurity diffusion layer of the element region, and in FIG. The same reference numerals are given to the parts.

[Effects of the Invention] As described above, according to the present invention, the number of manufacturing steps for the element isolation region is reduced, and the electrical breakdown voltage of the junction between the impurity diffusion layer of the element region and the impurity diffusion layer for the element isolation region is reduced. A semiconductor device suitable for driving with the following low power supply voltage can be realized.

Further, according to the present invention, it is possible to realize a semiconductor device that can prevent the latch-up phenomenon of a CMO5FET and a manufacturing method that requires an extremely small number of manufacturing steps.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention;
FIG. 2 is a sectional view showing another embodiment, and FIG. 3 is a sectional view showing a conventional semiconductor device. 10...N type semiconductor substrate, 11...P well, 1
2...P+ type impurity diffusion layer for source/drain of P channel transistor, 13...N" type impurity diffusion layer for element isolation region, 13゛...N+ for element isolation/substrate electrode type impurity diffusion layer, 14... N-type impurity diffusion layer for the source and drain of the N-channel transistor, 15'... P-type impurity diffusion layer for the element isolation region, 15°. ...P+ type impurity diffusion layer for device isolation and substrate electrodes. Applicant's agent: Takehiko Suzue, patent attorney

Claims (3)

[Claims] (1) an impurity diffusion layer in an element region formed in a surface layer of a semiconductor substrate; The impurity diffusion layer for the element isolation region has a conductivity type opposite to that of the impurity diffusion layer for the element isolation region and has the same impurity concentration as this impurity diffusion layer. A semiconductor device characterized in that it is fixed to a ground potential. (2) The semiconductor device according to claim 1, further comprising complementary insulated gate field effect transistors. (3) When manufacturing a semiconductor device having a complementary insulated gate field effect transistor, impurities of the first conductivity type are diffused into the surface layer of the semiconductor substrate to separate the source/drain regions of the MOS transistor of the first conductivity type and element isolation. simultaneously forming a first conductivity type impurity diffusion layer for the region;
a step of diffusing a second conductivity type impurity into the surface layer of the semiconductor substrate to simultaneously form a second conductivity type impurity diffusion layer for a source/drain region of a second conductivity type MOS transistor and an element isolation region; an element isolation region comprising an impurity diffusion layer of a second conductivity type adjacent to a source/drain region of a MOS transistor of a first conductivity type in a surface layer portion of at least a part of the semiconductor substrate; 1. A method of manufacturing a semiconductor device, comprising forming an element isolation region made of an impurity diffusion layer of a first conductivity type adjacent to a source/drain region of a MOS transistor.