JPH01280358A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To suppress a short channel effect without lowering the operation reliability due to a drop in the breakdown strength of a drain, an increase in a hot carrier effect or the like by forming a first semiconductor region and a second semiconductor region whose conductivity type is identical to that of a substrate, whose concentration is higher than that of the substrate and which are specified individually inside the substrate of a MIS type field-effect transistor. CONSTITUTION:In a MIS type field-effect transistor formed on a semiconductor substrate 1 of a first conductivity type the following are formed: a first semiconductor region 7, of a first conductivity type, which is adjacent to at least one out of a source and a drain 4, 4 of the transistor and whose concentration is higher than that of the substrate 1; a second semiconductor region 8, of the first conductivity type, which is adjacent to the first semiconductor region 7, which is inner to the substrate from the first semiconductor region 7 and whose concentration is higher than that of the first semiconductor region 7. When the MIS type field-effect transistor is manufactured, an impurity whose conductivity type is identical to that of the substrate 1 is ion-implanted into the substrate 1; the first semiconductor region 7 is formed; the second semiconductor region 8, of the first conductivity type, is formed on the substrate 1 which is inner from the first semiconductor region 7 by an ion implantation method at energy and in an implantation quantity which are higher than those for the first semiconductor region 7.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and is particularly suitable for suppressing the short channel effect of an MIS field effect transistor and is excellent in improving source-drain breakdown voltage. Regarding effect transistors.

[Conventional technology]

As a measure to prevent the short channel effect of conventional MIS transistors, a punch-through stopper layer is provided inside the substrate, and a high concentration layer is formed on the entire surface as described in Japanese Patent Application No. 58-124713, or an eye-concentration layer is formed on the entire surface.・E・
DM, Technical Digest (1985), pages 230 to 233 (IEDM, Techni
cal Digest pp230-233 (1985
Source as discussed in )).

Examples include those that form a highly concentrated layer around the drain. The former is shown in FIG.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, the latter has a high concentration layer for punch-through stopper around the source and drain, so it is certainly effective in suppressing the short channel effect, but it also reduces the drain breakdown voltage or increases the hot carrier effect. This results in decreased reliability.

In addition, in the method of burying the highly doped layer 8 as shown in FIG. 2, the impurity concentration near the substrate surface does not change, so the influence on the hot carrier effect is small; however, in order to suppress the short channel effect, it is necessary to must be made shallow, which also causes a decrease in drain breakdown voltage. This will be explained in the case of a single drain structure n-channel MO8FET. FIG. 3a shows the substrate impurity concentration distributions 30a to 34a in the depth direction and the distribution 34 of the source and drain diffusion layers. 318 to 33a are distributions having a high concentration buried layer, the peak positions of which have been changed, and 30a is a normal distribution without a buried layer. Threshold voltage V indicating the degree of short channel effect of devices with these substrate impurity distributions
The TR vs. effective channel length Le1□1 (VTR-L.0) characteristic is shown in FIG. 3, and the minimum drain breakdown voltage BVos, stn vs. ezn (BVos, +++n Lezz) characteristic is shown in FIG. 3C. The VTHLszz characteristic is improved by providing a buried layer, and the degree of improvement is better as the peak position of the buried layer is shallower. Here, 30b to 33b correspond to elements having a distribution of 30a to 33a, respectively. On the other hand, BVos and atn are determined by a balance between a mechanism in which parasitic bipolar is less likely to occur due to the formation of a low resistance layer in the substrate, which improves it, and a mechanism in which it decreases due to an increase in substrate current, which is the source of the parasitic bipolar effect. Therefore, the shallower the buried layer, the more the latter becomes dominant and the withstand voltage decreases, as shown in FIG. 3C. Here, 30c to 33c is 30
This corresponds to an element having a distribution of a to 33a.

Therefore, in the buried layer method, if the degree of suppression of the short channel effect is improved, the drain breakdown voltage will be reduced.

An object of the present invention is to suppress the short channel effect without impairing operational reliability such as a decrease in the drain breakdown voltage or an increase in the hot carrier effect.

[Means for deciding issues]

The above purpose is to form an impurity region with a higher concentration than the shallow first substrate of the same conductivity type as the substrate for the punch-through stopper inside the substrate of the MIS field effect transistor, and a first impurity region deeper in the substrate than the first impurity region. The first
This is achieved by providing a second impurity region that has a higher concentration than the impurity region and has the same conductivity type as the substrate.

[Effect]

The first high concentration impurity region is for suppressing the short channel effect, such as a punch-through stopper, as described above. Since the substrate surface concentration itself does not change, the increase in the hot carrier effect is small.

In addition, since the second high concentration impurity region is located deeper in the substrate than the first high concentration impurity region, it does not contribute to improving the short channel effect such as a punch-through stopper, but it forms a low resistance layer inside the substrate. It becomes an efficient current collector, making parasitic bipolar effects even less likely to occur. As a result, the drain breakdown voltage is further improved.

〔Example〕

<Example 1> A first example of the present invention will be described below with reference to FIGS. 1.3.4.

1 and 4 show one typical example of the present invention. The second high-concentration buried layer has a single drain structure n
This is formed in a channel MOS transistor. a
is the impurity distribution in the depth direction, 34 is the source/drain diffusion layer, and 40a is the impurity distribution in the substrate according to the present invention. For comparison, a conventional impurity distribution in which the first high concentration layer 7 has the same concentration is shown in 32a.

VTII of devices each having two substrate impurity distributions
Lett characteristics and minimum drain breakdown voltage B Vos
+mtn Lets characteristics are shown in FIGS. 3a and 3b.

V TRL e ti characteristics are 32 b
There is almost no difference between the two. This is because the first high concentration buried layer 7 working as a punch-through stopper is the same, and the second high concentration 'aJ! The influence of the 1-buried layer 8 is small, whereas the minimum drain breakdown voltage is improved by more than 1 V from 32c to 40c. This is because the substrate current increased in the first buried layer 7 is absorbed by the second buried layer 8, which has a lower resistance, causing a parasitic bipolar effect.

This makes it possible to suppress the short channel effect and improve the drain breakdown voltage at the same time, and is very effective for submicron MOSFETs, particularly MOSFETs with gate lengths of 0.5 μm or less.

<Example 2> Next, another example of the structure of the present invention will be shown using FIGS. 5 and 6.

The one shown in FIG. 5(a) has the same buried layers 7 and 8 as in the first embodiment, and the source/drain structure is a lightly doped drain (LDD).
ain), thereby achieving suppression of the short channel effect and improvement of the drain breakdown voltage as in the first embodiment, and further improving the ultimate operational reliability seen in the Hola 1-carrier effect. I can do it. In addition, Fig. 5 (b
) In the above LDD sweep, the upper portions of the low-concentration source and drain are all gates? Since it is covered with tt poles, the reliability is further improved than the above-mentioned LDD.

Further, in the embodiments shown in FIGS. 6(a), (b), and (c), the shape of the first high concentration impurity region 7 for the punch-through stopper is changed. (a) has the same basic characteristics as the first embodiment.

Since the lower portions of the source and drain are not in direct contact with the high concentration layer, the junction capacitance can be reduced. In (b), since there is no high concentration impurity layer at the bottom of the channel, the effect of reducing short channel effects such as punch-through suppression is somewhat inferior to that of the first embodiment, but because there is no high concentration layer at the shallow part of the substrate below the channel. Fluctuations in threshold voltage due to substrate effects are small.

3(c) shows a structure in which a first high concentration layer 7 for a punch-through stopper is provided around the low concentration layer of the LDD structure, and a second high concentration layer 8 is provided below the first high concentration layer 7. In this structure, the drain breakdown voltage tends to decrease, but the high concentration layer 8 prevents this.

As described above, in the present invention, the shape of the first high-concentration buried layer for short channel effect suppression may be arbitrary depending on the purpose of the device, and the second high-concentration buried layer for suppressing short channel effects may be formed inside the substrate rather than the first high-concentration layer. It is necessary that the concentration buried layer exists at least in the vicinity of the drain and below the channel.

<Example 3> Next, an example of a manufacturing method for manufacturing a typical structure of the present invention will be described using FIG. 7.

First, as shown in Figure 7(a), p-type silicon (specific resistance 1
0Ω) After forming a thermal oxide film 11 of 20 to 30 nm on the substrate 1, a silicon oxide film 1o of 500 to 700 nm for element isolation is selectively formed. Next, as shown in FIG. 7(b), boron is first implanted with an energy of 300 to 500 K e
V, implantation amount I x 10” ~ 3 x 1018
The second high concentration impurity region 8 is implanted into the entire surface.
followed by implantation energy of 100 to 200 KeV,
A first high concentration impurity region 7 is formed by implanting into the entire surface with an implantation amount of 1×10 12 to I X 10 ”Ql−2. Here, the first high concentration impurity region 7 serves as a punch-through stopper for suppressing the short channel effect. The second high concentration impurity region 8 is a low resistance layer for improving drain breakdown voltage.

After that, as shown in FIG. 7(c), the gate oxide film 2 is
25 nm thick and 1011 boron 9 for threshold voltage setting.
Drive approximately 1013m-2. Subsequently, phosphorus-doped polycrystalline silicon is formed to a thickness of 200 to 300 nm and patterned by photoetching to form the gate electrode 3. Finally, using the gate electrode 3 as a mask, add 5x10" arsenic.
High concentration source and drain 4 are formed by δGW-2 implantation. As a result, the structure of the first embodiment shown in FIG. 4 can be realized by adding two ion implantation steps without increasing the number of masks. Further, in this embodiment, the high concentration buried layers 7 and 8 are formed over the entire surface.

The channel stopper under the element isolation oxide film 10 can be formed by the buried layers 7 and 8 without being specially formed.

<Example 4> Finally, another example of the manufacturing method for forming the structure of the present invention will be shown using FIGS. 8 and 9.

In the embodiment shown in FIGS. 8(a) to 8(C), the high concentration buried layers 7 and 8 are formed by ion implantation over the entire surface after the gate electrode 3 is formed. In this case, the buried layers 7, 8
is formed inside the substrate under the gate, using higher energy ion implantation than in the third embodiment. As a result, the heavily doped buried layers 7 and 8 are not in direct contact with the lower part of the source/drain diffusion layer 4, thereby preventing an increase in parasitic capacitance.

Further, the embodiment shown in FIG. 9 is a combination of the manufacturing methods shown in FIGS. 7 and 8. In other words, in the manufacturing method of the present invention, the first high-concentration buried layer 7 and the second high-concentration buried layer 8 for the punch-through stopper are
It may be formed at any time during the manufacturing process of forming an IS type field effect transistor. Further, the structure of the present invention and its manufacturing method can be easily applied to the CMOS process that has become mainstream in LSI in recent years.

〔Effect of the invention〕

According to the present invention, it is possible to prevent a decrease in drain breakdown voltage that occurs in a conventional MIS type field effect transistor having a buried layer type punch-through stopper layer, and at the same time, it is possible to suppress short channel effects. Therefore, the gate length is 0.5pm.
The following U L S I (UltraLarge 5c
It is effective as a basic device for Ale Integration.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a structure showing a typical example of the present invention, Fig. 2 is a cross-sectional view of a conventional structure, Fig. 3 is a view showing the main electrical characteristics of the conventional structure, and Fig. 4 is a cross-sectional view of a structure of the present invention. Figures showing representative examples and their impurity profiles; Figure 5.6 is a sectional view of a structure showing another embodiment of the present invention; Figure 7.8.9 shows a typical manufacturing method of the present invention. FIG. 1... Semiconductor substrate, 2... Gate insulating film, 3...
Gate electrode, 4...high concentration source, drain, 5...
-Low concentration source, drain, 6... side wall spacer, 7... first high concentration buried layer, 8... second high concentration buried layer. 2\ ■3 Fig. (b) (C) Leaf (pysu construction 4 Fig. (e) (b) 7.8 buried 4Q 婁V 32L ft1J/lt riha-komi J14 Burihiru 4θ6
5th figure (missing) (bn3 j-)+ in August Ha, Komi fishing) 9ji 8' 2nd
ri ・ /θ 11 Bodhisattva seven chi de one call S1θ2,3 capture “620 222] Kuji 21 Rita '? Kiri J Swords kL

Claims (1)

[Claims] 1. In a MIS field effect transistor formed on a first conductivity type semiconductor substrate, the source of the transistor;
a first semiconductor region that is in contact with at least one of the drains and has a higher concentration than the substrate and has a first conductivity type; A semiconductor device comprising a second semiconductor region of a first conductivity type. 2. In the semiconductor device according to claim 1,
A semiconductor device, wherein at least one of the first semiconductor region and the second semiconductor region is present on the entire lower part of the channel portion of the transistor. 3. In the method for manufacturing an MIS field effect transistor, the first semiconductor region is formed by ion implanting impurities of the same conductivity type as the substrate into the substrate, and the first semiconductor region is implanted at a higher energy and higher level than the first semiconductor region. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming the second semiconductor region of the first conductivity type inside the substrate rather than the first semiconductor region by ion implantation of a large amount.