JP3123140B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor.

[0002]

2. Description of the Related Art Metal-insulator-semiconductor field effect transistors (Metal-Insulator-Semico)
nductor Field Effect Tran
A MISFET is a main active element constituting an integrated circuit (IC). The processing speed and function of integrated circuits can be significantly improved by reducing the size of FETs used therein and increasing the density of the circuits.
The miniaturization of ET has been promoted, and in recent years, an extremely fine one having a gate length (length of a gate electrode) of 0.5 μm or less has been put to practical use.

[0003] As the miniaturization of FETs is advanced, it has become increasingly difficult to suppress the short channel effect (the phenomenon that the FET is less likely to be turned off when the channel length becomes shorter). To suppress the short-channel effect, it is necessary to increase the impurity concentration of the substrate and reduce the thickness of the gate insulating film.
With the progress of miniaturization of T, the threshold voltage of the device becomes too high in the first method, and it becomes difficult to secure the reliability of the gate insulating film in the second method. In addition, although the channel length varies in manufacturing, the fact that the size of the variation cannot be ignored compared to the design channel length of the element due to miniaturization also makes it difficult to suppress the short channel effect.

To cope with the above difficulties, it has been proposed to form a source and a drain usually formed inside a semiconductor substrate in a semiconductor region deposited on the substrate.
As a presentation on the trial production of such a device, for example,
International Electronic Device Conference of 984 (International
al Electron DevicesMeetin
g.) (S. Wang, et al., Proceedings of the Conference p. 634), and the presentation of T. Yamada, et al. at the 1988 International Electron Devices Conference (P. 35). There is.

An example of the source / drain lift type FET according to the above proposal will be described with reference to FIG. FIG. 2A is a cross-sectional view of the source / drain lift-up type FET. For comparison, a low-concentration source / drain (Lightl) having no raised structure, which is generally used, is used.
y Doped source and Drain;
An FET having an LDD) region is shown in FIG. In the drawings of the present application, parts that are not essentially related to the present invention, such as an interlayer insulating film and wiring, are omitted. In the source / drain lift type FET, a high concentration source 10 and a drain 11 usually formed inside the substrate are formed to be raised above a surface 75 of the substrate 70. The impurities of the source 10 and the drain 11 also spread in the substrate during the manufacturing process, and there are regions 10b and 11b where the source and the drain spread in the substrate. In this structure, the depth of the source 10b in the substrate and the drain 11b in the substrate from the substrate surface and the lateral spread thereof can be reduced in manufacturing. That is, when impurities are introduced into the source 10 and the drain 11 by ion implantation, the depths of the regions 10b and 11b are reduced by the thickness of the regions 10a and 11a, and
And doping the impurity into the drain region 11 with the regions 10a and 11
When the deposition is performed at the same time as the deposition of a, the regions 10b and 11b are formed by solid-phase diffusion of impurities from the regions 10a and 11a, so that the depth is suppressed as compared with a device having a conventional structure in which direct ion implantation is performed. Therefore, in the structure of FIG. 2A, the short channel effect is suppressed as compared with the device having the conventional structure of FIG. 2B. The LDD regions 32 and 33 are
Although originally introduced to alleviate the concentration of the electric field and suppress the long-term deterioration of the device due to the generation of hot carriers, in FIG. 2A, the channel region immediately below the gate insulating film 42, the source 10 and It has a function of electrically connecting the drain 11. In the figure, 40 is a gate side surface insulating film, 43 is a cap insulating film, and 60 is LOCOS.
It is an oxide film.

[0006]

The structure shown in FIG. 2A in which the source and the drain are raised above the substrate surface can reduce the short channel effect to some extent. However, this structure essentially only makes the high-concentration source and drain shallower, and the channel length of the device does not become longer than the gate length, and its effect is limited.

[0007]

[0008]

According to the present invention, there is provided a field effect transistor comprising: a semiconductor substrate; a gate insulating film formed on the upper surface of the substrate; a gate electrode formed on the upper surface of the gate insulating film; A side surface insulating film covering all or a part of the side surface; a semiconductor region A in contact with a side surface of the side surface insulating film and an upper surface of the semiconductor substrate;
A in contact with the semiconductor region B, and the semiconductor region B
Function as a source or drain electrode, and the semiconductor region A has a conductivity type different from that of the semiconductor region B.

[0009]

The field effect transistor according to the present invention has an LDD
It has a structure in which a region or a channel region is extended not only in the substrate but also upward along the side surface of the gate electrode. Therefore, as compared with a fixed gate length, the substantial element length can be made longer than that of a conventional planar transistor and a transistor in which only a high concentration source and drain are raised. Further, by selecting the thickness of the semiconductor region on the side of the gate electrode, the amount of expansion of the LDD region or the channel region, that is, the magnitude of the effect of suppressing the short channel effect, can be freely set.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a reference example of the present invention will be described with reference to FIG. The difference from the conventional lift-up transistor shown in FIG.
1 and the silicon substrate 70, the source 10 has the same conductivity type as the source / drain (n-type for an n-channel device, p-type for a p-channel device) and the net impurity concentration.
And the semiconductor region lower than the drain 11, that is, the raised LDD regions 20 and 21 are inserted. LD
The D region has an effect of suppressing the short channel effect, and the effect is larger as the LDD region is longer. In this embodiment, a longer LDD region length than that of the related art can be obtained with the same gate electrode length, so that the short channel effect can be effectively suppressed. As typical value of each region heavily doped source 10, drain 11 Concentration 10 ^{2 0} cm ^{- 3,} elevated LDD region 2
0 and 21 have a concentration of 3 × 10 ¹⁸ cm ⁻³ and a thickness of 100 n.
m, the thickness of the side insulating film 40 is 75 nm, the length of the bottom surface of the gate electrode is 0.25 μm, and the raised portion-channel connection region 3 is formed.
The concentration of 0, 31 is 3 × 10 ¹⁸ cm ⁻³ .

Lift-to-channel connection regions 30 and 3
Reference numeral 1 denotes a substrate region into which impurities are introduced so as to have the same conductivity type as the source / drain. These function to electrically connect the lifted LDD regions 20 and 22 and the channel portion immediately below the gate, similarly to the LDD regions 32 and 33 in FIG. When the gate side insulating film 40 is sufficiently thin and an inversion layer is formed on the substrate surface below the side insulating film 40 by an electric field from the gate electrode, the connection regions 30 and 3
1 may not be provided.

In the above, an example in which the source side and the drain side have the same structure has been described. However, an asymmetric structure or one of the source side and the drain side may have a conventional structure.

An embodiment of the present invention will be described with reference to FIG. In the present embodiment, a conductive type (n
A p-type or intrinsic semiconductor region for a channel element and an n-type or intrinsic semiconductor region for a p-channel element, ie, elevated channel regions 22 and 23 are inserted. In this embodiment, an inversion layer needs to be formed at the interface between the lift-up channel regions 22 and 23 and the gate side surface insulating film 40 when a voltage is applied to the gate electrode 50. So area 2
The impurity concentrations of 2 and 23 and the thickness and material of the side surface insulating film 40 are appropriately selected by the same method as that for designing the channel portion of the normal MISFET. In this embodiment, by extending the channel region along the side surface of the gate electrode, the channel length can be freely extended with the same gate size, and the short channel effect can be avoided. A typical value of the raised channel regions 22 and 23 is 1 × 1
0 ¹⁶ cm ⁻³ , thickness 100 nm, the side insulating film 40 at this time is 30 nm thick when SiO ₂ is used, and the values of other regions are the same as those of the reference example . The reason for providing the raised portions and the inter-channel connection regions 30 and 31 is the same as that of the reference example . It is also possible that the regions 30 and 31 are not provided. It is also possible to make the structure on the source side and the drain side asymmetric, and to make one of the source side and the drain side a conventional structure.

[0014] The present invention is SOI (S emicondu
It can also be used for ctor o n I nsulator) MISFET.

[0015]

As described above, in the transistor according to the present invention, the LDD region or the channel region extends upward along the side surface of the gate electrode. Gate length) to suppress the short channel effect. Therefore, the area occupied by the transistor can be reduced while avoiding the side effect of suppressing the short-channel effect such that the threshold voltage becomes too high and the gate insulating film becomes too thin.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining an embodiment of the present invention.

FIG. 2 shows a conventional source / drain lift type MISFE.
FIG. 4 is a cross-sectional view of T and a normal LDD MISFET for comparison.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 high-concentration source 11 high-concentration drain 20, 21 raised LDD region 22, 23 raised channel region 30, 31 raised portion-channel connection region 32, 33 LDD region 40 gate side insulating film 42 gate insulating film 43 cap insulating Film 50 gate electrode 60 element isolation insulating film 70 semiconductor substrate 75 semiconductor substrate surface

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-255970 (JP, A) JP-A-63-93150 (JP, A) JP-A-63-107170 (JP, A) JP-A-63-107170 115376 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 29/78

Claims (1)

(57) [Claims] A gate insulating film formed on an upper surface of the semiconductor; a gate electrode formed on the upper surface of the gate insulating film;
A side surface insulating film covering all or a part of a side surface of the gate electrode, a semiconductor region A in contact with the side surface of the side surface insulating film and the semiconductor upper surface, and a semiconductor region B in contact with the semiconductor region A ; the semiconductor region B serves as a source or drain electrode, said field effect transistor, wherein the semiconductor region a is different from the conduction type of the semiconductor region B.