JP2557876B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a semiconductor device formed by integrating MOSFETs and a method for manufacturing the same, and in particular to the parasitic resistance in the source and drain diffusion regions. The present invention relates to a semiconductor device that is effective in reducing the noise and a method for manufacturing the semiconductor device.

(Prior Art) The structure of a conventional MOSFET will be described with reference to FIG. P
Type silicon substrate 1 (here N-channel MOSFET
Will be explained. In the case of the P channel, the opposite conductivity type may be considered), and the gate electrode 2 is formed via the gate oxide film 5. The source 3 and the drain 4 are of N type because they contain impurities of anti-conductivity type of the substrate. The impurity distribution of the source and drain is generally uniform, or the structure is usually thinned at the end away from the surface. Alternatively, there is also a structure having a low-concentration source region 33 and a low-concentration drain region 44 as shown in FIG. 3 in order to avoid the hot electron problem caused by the internal strong electric field effect due to miniaturization.

Further, the source 3 and the drain 4 are connected to an electrode 8 usually made of aluminum. The above structure is widely known.

In both cases shown in FIG. 2 and FIG.
A region 10 in which a channel current flows as a MOS inversion region is very thin and is localized near the substrate surface near the gate oxide film between the source and drain. Or, it is limited to the thin area inside. Therefore, when the current flow path in the source is written (in the case of the drain, the arrow should be reversed), it becomes like the arrow in FIG. 4, and there is a phenomenon in which the currents are crowded in the channel adjacent portion. If the currents are crowded, that is, the current density is large, and the voltage drop due to the resistance in that portion becomes large, the deterioration of the characteristics of the MOSFET, that is, the reduction of the current driving force becomes remarkable.

The resistance of the source and drain regions is smaller than that of the channel resistance and has not been a problem until recently.However, the resistance of the source and drain regions has become relatively small because the channel resistance has become relatively small due to the miniaturization of MOSFET which is an LSI element. FE
The effect of defining the current of T came out. In particular, the deterioration of FET characteristics due to the above-mentioned current crowding has become noticeable.

(Problems to be Solved by the Invention) There has been a problem that the current density becomes high in the source and drain regions adjacent to the channel region, and the voltage drop at that portion is large. In order to avoid this situation, it is necessary to reduce the resistance of a part of the source and drain regions adjacent to the channel.

[Structure of Invention]

(Means for Solving the Problems) As shown in FIG. 1A, high-concentration N type regions 13 and 14 are formed by a part of the source 3 and drain 4 regions adjacent to the channel region.

(Function) It is widely known that the high-concentration region has a lower specific resistance than the low-concentration region. Therefore, the voltage drop in FIG. 1-a 13 or 14 is reduced. This is to reduce the voltage drop mainly occurring in the current crowding portion at the source and drain. Therefore, the deterioration of the MOSFET characteristics can be avoided.

It is an unfavorable structure to make the source and drain of high concentration all over because it increases the parasitic capacitance between the source and the drain and reduces the operation speed of the LSI.

(Embodiment) In the structure of the present invention, a part of the source and drain adjacent to the channel shown in FIG. 1 is a high concentration region. The structure for avoiding the hot electron problem described in FIG. 3 of the prior art has 33,44 regions of low concentration, and LDD (Lighly
This is called Doped / Source), but the present invention is HDD (Highly Dop)
ed Drain / Source) is a structure that should also be called.

Examples of the manufacturing method will be described below. As shown in FIG. 1-c, the gate electrode 2 is formed on the P-type silicon substrate 1 in a region isolated by the device isolation oxide film 6 through the gate oxide film 5 according to a conventionally known method. N-type source 3 and drain 4 by ion implantation of arsenic
To form. Then, a CVDSiO ₂ film containing phosphorus or arsenic is deposited and well-known anisotropic etching is performed to leave the CVDSiO ₂ 15 film on the side wall of the gate as shown in FIG. 1-d. If the CVD SiO ₂ film remaining on the side wall is used as a diffusion source, the high concentration regions 13 and 14 shown in FIG. 1A can be easily formed. After that, MOFSET is manufactured according to the normal process.

〔The invention's effect〕

The current density is high because the source and drain partial regions near the channel have a high concentration and a low resistance, so the voltage drop that was noticeable in this part is alleviated and the characteristic deterioration due to the parasitic resistance effect is reduced. A high quality MOSFET is realized. The effect is particularly remarkable in miniaturized MOSFETs.

[Brief description of drawings]

FIG. 1 (a) is a cross-sectional view of a MOSFET showing the present invention, FIG. 1 (b) is a plan view, and FIGS. 1 (c) and 1 (d) are views for explaining an embodiment of a manufacturing method. 2, FIG. 2 is a structural diagram of a conventional MOSFET, FIG. 3 is a diagram of a conventional example which copes with a hot carrier problem, and FIG. 4 is a diagram showing a current flow path of a source in the conventional example. In the figure, 1 ... Substrate, 2 ... Gate electrode, 3 ... Source, 4 ...
Drain, 5 ... Gate oxide film, 6 ... Element isolation oxide film, 7 ... Insulating film, 8 ... Aluminum wiring, 9 ... Contact part, 13 ... High concentration source region, 14 ... High concentration drain region , 33 …… low concentration source region, 44 …… low concentration drain region.

Claims (2)

(57) [Claims] 1. A semiconductor device in which a plurality of MOSFETs are integrated, wherein the source and drain of the FET are adjacent to the channel, and the source is at least the same conductivity type as the drain.
A semiconductor device having a higher concentration region than a drain. 2. A step of forming a diffusion region of anti-conductivity type with the substrate as source and drain regions using the gate electrode as a mask after forming the gate electrode, and impurities of anti-conductivity type with the substrate self-aligned with the side wall of the gate electrode. Forming a CVD SiO ₂ film containing, and doping impurities on the channel side of the source and drain regions from this CVD SiO ₂ film,
A method of manufacturing a semiconductor device, comprising the step of forming a diffusion region having a higher concentration than the diffusion region, the diffusion region overlapping the source and drain diffusion regions.