JP2001007331A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain the roll-off of a threshold voltage due to a short channel effect and to enhance a current drive capability, by a method wherein a pocket region of a conductivity in which carrier concentration is lower than that of a channel region is provided and a gate electrode which is formed on the channel region via an insulating film is provided. SOLUTION: A pocket region 34, in which conductivity is identical to the conductivity of a channel region 32 and whose impurity concentration is higher than the impurity concentration of the channel region 32, is formed between a source region 26 and the channel region 32. On the other hand, a pocket region 36, that the conductivity is identical to the conductivity of the channel region 32 and whose impurity concentration is lower than that of the central part of the channel region 32 and that of the pocket region 34, is formed between a drain region 30 and the channel region 32. In this manner, this semiconductor device which comprises the pocket regions is constituted in such a way that the impurity concentration of the pocket region 36 on the side of a drain is lower than that of the central part of the channel region 32 and that of the pocket region 34.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a structure of a semiconductor device capable of suppressing a short channel effect without impairing current driving capability and a method of manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor integrated circuit devices are required to have higher integration and higher speed in order to improve their performance. In order to achieve such an object, miniaturization of each constituent element is indispensable. Not only the development of fine processing technology, but also various structures and manufacturing methods for achieving high-speed operation of the element are being studied.

[0003] MOSFET (Metal Oxide Semiconducto)
In (r Field Effect Transistor), the element is miniaturized mainly by shortening the gate length. However, when the MOSFET is miniaturized, the effect of the drain electric field on the electric field in the channel region cannot be ignored, and a phenomenon called the so-called short channel effect, in which the threshold voltage rapidly changes with respect to the gate length, becomes a problem. . The generation of the short channel effect is caused by the extremely fine MOSFE
This causes a variation in the threshold value of T and significantly reduces the margin in circuit design. Therefore, how to suppress the short channel effect accompanying the miniaturization of elements is extremely important in developing future elements.

[0004] As shown in FIG.
The so-called drain-induced barrier reduction (DIBL) in which the height of the barrier to carriers in the channel region is reduced by the electric field applied to the drain region.
ier Lowering) phenomenon is one of the factors.
Therefore, it can be said that reducing the DIBL phenomenon is an effective means of suppressing the short channel effect.

As a structure of a conventional semiconductor device capable of reducing the DIBL phenomenon, a pocket structure in which a so-called pocket region is provided at a boundary between a source region and a channel region and a boundary between a drain region and a channel region is known. Are known.

A conventional semiconductor device having a pocket structure will be described with reference to FIG.

A gate electrode 104 is formed on a silicon substrate 100 with a gate insulating film 102 interposed. On the side wall of the gate electrode 104, the side wall insulating film 10
6 are formed.

The silicon substrate 1 on both sides of the gate electrode 104
The source region 116 includes a source extension 108 formed by self-alignment with the gate electrode 104 and a diffusion layer 112 formed by self-alignment with the gate electrode 104 and the sidewall insulating film 106. A drain extension 110 formed by self-alignment and a source region 118 including a diffusion layer 114 formed by self-alignment on the gate electrode 104 and the sidewall insulating film 106 are formed. The channel region 1 is located between the source region 116 and the drain region 118.
It will be 20.

Source region 116 and channel region 120
Between the drain region 118 and the channel region 120, pocket regions 122 and 124 having the same conductivity type as that of the channel region and an impurity concentration higher than the impurity concentration of the channel region 120 are formed, respectively. ing.

Thus, a conventional semiconductor device having a pocket structure has been constructed.

Thus, the pocket regions 122, 12
4 is formed, the source region 11 is formed as shown in FIG.
At the boundary between the channel region 120 and the drain region 118 and the boundary between the drain region 118 and the channel region 120, the barrier height against carriers flowing through the channel region 120 is increased. Thus, the influence of the drain electric field on the barrier height can be suppressed. For example, even when the drain voltage Vd is set to 1.5 V, the barrier height near the source region due to the drain electric field does not decrease.

Therefore, according to the semiconductor device having the pocket structure shown in FIG. 18, it is possible to suppress the influence of the drain electric field on the height of the barrier against carriers, thereby suppressing the short channel effect.

[0013]

However, FIG.
The semiconductor device having the above-mentioned conventional pocket structure has the advantage that the barrier height for carriers at the boundary between the source region 116 and the channel region 120 and at the boundary between the drain region 118 and the channel region 120 can be increased. On the other hand, there is a disadvantage that the current driving capability of the MOS transistor is reduced.

That is, in the conventional pocket structure, the barrier height is increased by increasing the substrate impurity concentration in the channel region. As a result, the current driving capability of the MOS transistor is reduced, and the operation speed is reduced. Had become.

An object of the present invention is to provide a structure of a semiconductor device capable of improving a current driving capability while suppressing a threshold voltage roll-off due to a short channel effect, and a method of manufacturing the same.

[0016]

An object of the present invention is to provide a channel region of a first conductivity type formed on a semiconductor substrate and a source region of a second conductivity type formed on the semiconductor substrate and separated from each other by the channel region. And a first pocket region of the first conductivity type formed in the semiconductor substrate between the channel region and the source region and having a higher carrier concentration than the channel region; A second pocket region of the first conductivity type formed on the semiconductor substrate between the drain region and having a lower carrier concentration than the channel region; and a gate electrode formed on the channel region via an insulating film. This is achieved by a semiconductor device having:

In the above-described semiconductor device, the source region may include a first diffusion layer of a second conductivity type provided adjacent to the first pocket region, and an adjacent region adjacent to the first diffusion layer. A second diffusion layer having a higher impurity concentration and a deeper impurity concentration than the first diffusion layer, and the drain region is provided with a second diffusion region provided adjacent to the second pocket region.
A third diffusion layer of a conductivity type and a fourth diffusion layer provided adjacent to the third diffusion layer and having a higher impurity concentration than the third diffusion layer and deeper than the third diffusion layer may be provided.

In the above semiconductor device, the semiconductor substrate is an SOI substrate, and the channel region, the source region, the drain region, the first pocket region, and the second pocket region are formed on the SOI substrate. S
It may be formed in the OI layer.

Further, the above object is to form a first conductivity type channel region by introducing a first conductivity type first impurity into a semiconductor substrate, and to form a first conductivity type channel region on the semiconductor substrate via an insulating film. Forming a gate electrode; and forming a second conductive type second electrode of the first conductivity type in the semiconductor substrate on one side of the gate electrode.
Forming a first pocket region of the first conductivity type having a higher carrier concentration than that of the channel region, and forming a second conductivity type in the semiconductor substrate on the other side of the gate electrode. Of the first conductivity type having a lower carrier concentration than the channel region.
Forming a pocket region, and introducing a fourth impurity of the second conductivity type into the semiconductor substrate on both sides of the gate electrode, and adjoining the channel layer via the first pocket region. Forming a source region of two conductivity type and a drain region of second conductivity type adjacent to the channel layer with the second pocket region interposed therebetween. Achieved.

Further, the above object is to form a first conductivity type channel region by introducing a first impurity of a first conductivity type into a semiconductor substrate, and to form a first conductivity type channel region on the semiconductor substrate via an insulating film. Forming a gate electrode, introducing a second impurity of a second conductivity type into the semiconductor substrate using the gate electrode as a mask, and separating the source region and the drain of the second conductivity type from each other by the channel region Forming a region, introducing a third impurity of the first conductivity type into a region between the source region and the channel region, and forming a third impurity of the first conductivity type having a higher carrier concentration than the channel region. Forming a first pocket region and introducing a fourth impurity of the second conductivity type into a region between the drain region and the channel region, the carrier concentration being lower than that of the channel region. Also achieved by a method of manufacturing a semiconductor device characterized by a step of forming a second pocket region of the first conductivity type.

In the method of manufacturing a semiconductor device, in the step of forming the first pocket region, the third impurity is introduced from a direction inclined toward the source region using the gate electrode as a mask. Thereby, the first pocket region may be formed.

In the method of manufacturing a semiconductor device, in the step of forming the second pocket region, the fourth impurity is introduced from the direction inclined toward the drain region using the gate electrode as a mask. By doing
The second pocket region may be formed.

[0023]

[First Embodiment] A semiconductor device according to a first embodiment of the present invention and a method for fabricating the same will be described with reference to FIG.
This will be described with reference to FIGS.

FIG. 1 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment, FIG. 2 is a graph showing the impurity concentration distribution along the channel direction in the semiconductor device according to the present embodiment, and FIG. FIG. 4 is a graph showing the impurity concentration distribution along the channel direction, FIG. 4 is a graph showing a result of device simulation for a potential distribution on the interface between the gate insulating film and the silicon substrate in the semiconductor device according to the present embodiment, and FIG. FIG. 6 is a graph showing the results obtained by device simulation of the gate length dependence of the current by device simulation. FIG. 6 is a graph showing the results obtained by device simulation of the drain voltage dependence of the threshold voltage. FIG. FIG. 8 is a graph showing the obtained results, and FIG. 9 is a graph showing the results obtained by device simulation of the carrier drift speed in FIG. 9, FIG. 9 is a graph showing the results obtained by device simulation of the dependence of the drain current on the drain voltage, and FIGS. 10 to 12 are diagrams of the semiconductor device according to this embodiment. It is a process sectional view showing a manufacturing method.

First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS.

A gate insulating film 1 is formed on a silicon substrate 10.
The gate electrode 16 is formed via the gate electrode 4. A side wall insulating film 18 is formed on the side wall of the gate electrode 16.

The silicon substrate 10 on both sides of the gate electrode 16
The source region 28 includes a source extension 20 formed by self-alignment with the gate electrode 16 and a diffusion layer 24 formed by self-alignment with the gate electrode 16 and the sidewall insulating film 18. A source region 30 including a drain extension 22 formed by matching and a diffusion layer 26 formed by self-alignment with the gate electrode 16 and the sidewall insulating film 18 is formed. Note that a region between the source region 28 and the drain region 30 becomes a channel region 32.

Between the source region 26 and the channel region 32, a pocket region 34 having the same conductivity type as that of the channel region 32 and having an impurity concentration higher than that of the channel region 32 is formed.

On the other hand, between the drain region 30 and the channel region 32, a pocket region having the same conductivity type as that of the channel region 32 and having a lower impurity concentration than the central portion of the channel region 32 and the pocket region 34. 36 are formed.

On the source region 28 and the drain region 30, a silicide electrode 38 is formed.

As described above, in the semiconductor device according to the present embodiment, in the semiconductor device having the pocket region, the impurity concentration of the pocket region 36 on the drain side is lower than that of the central portion of the channel region 32 and the pocket region 34. It is characterized by being structured.

That is, as shown in FIG. 2, the impurity concentration distribution along the channel direction in the semiconductor device according to the present embodiment is highest near the interface with the source region and decreases toward the drain side. In contrast, the conventional semiconductor device having no pocket structure has a substantially uniform impurity concentration over the entire channel region (see FIG. 3A), and the conventional semiconductor device shown in FIG. It has a peak concentration in the vicinity of the interface between the channel region and the drain region, and near the interface between the drain region and the channel region (see FIG. 3B).

The fluctuation of the threshold voltage (threshold voltage roll-off) when the gate length is shortened is caused by the remarkable DIBL phenomenon in which the potential peak near the gate insulating film is reduced by the potential on the drain side.

In the conventional semiconductor device shown in FIG.
The pocket region 122 on the source side has an effect of not only increasing the potential peak but also shifting the position to the source side, and the amount of change in the peak value can be suppressed even when the drain voltage is applied (see FIG. 19). ). On the other hand, the pocket region 124 on the drain side has the effect of suppressing the potential peak located on the source side from being depressed by the drain voltage.
The effect is small compared to the effect of suppressing the IBL phenomenon. Therefore, in the conventional semiconductor device shown in FIG. 18, even if the pocket region 124 on the drain side is replaced with a pocket region having a lower effective doping concentration without DIBL suppression effect, if the pocket region is on the source side, the short channel effect can be reduced. It is possible to sufficiently deter.

On the other hand, in the saturation region, if a high concentration layer of the same conductivity type as the channel region is formed near the drain,
The lateral electric field increases only in the vicinity of the drain, and the electric field does not increase on the source side. Therefore, the pocket region 12 in the conventional semiconductor device shown in FIG.
If there is 4, it is considered that the carrier speed does not increase in the channel formed on the source side, and the saturation current value decreases.

Therefore, in the semiconductor device according to the present embodiment, in the semiconductor device having the pocket structure, the drain-side pocket region 36 is configured to have a lower impurity concentration than the central portion of the channel region 32 and the pocket region 34. ing. The concentration of the pocket region 36 on the drain side is adjusted to the central portion of the channel region 32 and the pocket region 34.
If it is set lower, the lateral electric field near the drain is suppressed, so that the lateral electric field on the source side of the channel region 32 is increased. As a result, the carrier velocity increases and the saturation current increases.

The source-side pocket region 34 also has the effect of increasing the vertical electric field of the channel region 32 and deteriorating the mobility, but its contribution is small. Therefore, in the semiconductor device according to the present embodiment, the conventional semiconductor device shown in FIG.
The saturation current value can be increased as compared with the SFET.

Therefore, by configuring the semiconductor device according to the present embodiment, it is possible to suppress the threshold voltage roll-off and to improve the current driving capability.

FIG. 4 is a graph showing a result obtained by device simulation of a potential distribution on an interface between the gate insulating film and the silicon substrate in the semiconductor device according to the present embodiment.

In the conventional semiconductor device having no pocket structure, as described above, the gate voltage Vg is set to 0 [V], and the drain voltage Vd is changed from 0 [V] to 0.5, 1.0,
As the potential peak value increases to 1.5 [V], the potential peak value on the source side (left side of the graph) decreases with the decrease in the potential peak value on the drain side (right side of the graph), and the barrier height for carriers decreases. This causes the threshold voltage roll-off to increase (FIG. 17).

However, in the semiconductor device according to the present embodiment, the gate voltage Vg is set to 0 [V], and the drain voltage Vd is increased from 0 [V] to 0.5, 1.0, 1.5 [V]. Then, the potential peak value on the drain side (right side of the graph) gradually decreases, but the potential peak value on the source side (left side of the graph) hardly changes (see FIG. 4). That is, it has been clarified that the threshold voltage roll-off can be suppressed by employing the pocket structure according to the present embodiment.

FIG. 5 shows that the drain voltage Vd is 1.5
7 is a graph showing the results obtained by device simulation on the gate length dependence of off-state current when [V] and the gate voltage Vg are 0 [V]. In the figure, the solid line indicates the characteristics of the semiconductor device according to the present embodiment, the dotted line indicates the characteristics of the conventional semiconductor device shown in FIG. 18, and the dashed line indicates the characteristics of the conventional semiconductor device having no pocket structure. .

As shown in FIG. 5, in a semiconductor device having a pocket structure (solid line and dotted line), an increase in off-current on the short channel side is largely suppressed. Since the semiconductor device according to the present embodiment does not have a potential peak on the drain side, the off-current value is slightly larger than that of the conventional semiconductor device shown in FIG. 18, but the conventional semiconductor device having no pocket structure (dashed line) ), The effect of reducing the off-state current is sufficiently obtained.

FIG. 6 is a graph showing the result of determining the drain voltage dependency of the threshold voltage Vth by device simulation. In the figure, the solid line indicates the characteristics of the semiconductor device according to the present embodiment, the dotted line indicates the characteristics of the conventional semiconductor device shown in FIG. 18, and the dashed line indicates the characteristics of the conventional semiconductor device having no pocket structure. . Note that the threshold voltage Vth is equal to the drain voltage Vd.
5 [V], the drain current Id is 1 × 10 ⁻⁸ A / μ.
The value was defined as the value of the gate voltage Vg when it reached m. The measurement of the dependence of the threshold voltage Vth on the drain voltage Vd is performed using DIB
It is often used for evaluation of the L phenomenon, and indicates that the steeper the slope of the graph, the more remarkable the DIBL phenomenon.

As shown in FIG. 6, the semiconductor device having the pocket structure (solid line, dotted line) has a drain voltage V higher than that of the semiconductor device without the pocket structure (dashed line).
The change amount of the threshold voltage Vth with respect to the change of d is small. This indicates that the short channel effect is sufficiently suppressed in the semiconductor device having the pocket structure. When the semiconductor device according to the present embodiment (solid line) and the conventional semiconductor device (dotted line) shown in FIG. 18 are compared, their inclinations are almost equal, and the short channel effect characteristics of both are almost equal.

FIG. 7 shows that the gate voltage Vg is 1.5 [V],
10 is a graph showing a result obtained by device simulation of a lateral electric field in a channel when a drain voltage Vd is set to 1.5 V. FIG. 8 shows that the gate voltage Vg
13 is a graph showing the results obtained by device simulation of the drift velocity of carriers in a channel region when the drain voltage Vd is 1.5 V and the drain voltage Vd is 1.5 V. In the figure, the solid line indicates the characteristics of the semiconductor device according to the present embodiment, the dotted line indicates the characteristics of the conventional semiconductor device shown in FIG. 18, and the dashed line indicates the characteristics of the conventional semiconductor device having no pocket structure. .

As shown in FIG. 7, the pocket region 124 on the drain side in the conventional semiconductor device shown in FIG. 18 acts in a direction to increase the lateral electric field, whereas the pocket region 124 on the drain side in the semiconductor device according to the present embodiment. The region 36 acts in a direction to weaken the lateral electric field. On the other hand, due to this effect, the lateral electric field is weakened in the source-side pocket region 122 in the conventional semiconductor device shown in FIG. 18, and the source-side pocket region 3 in the semiconductor device according to the present embodiment.
The lateral electric field at 4 is strengthened.

As a result, as shown in FIG. 8, the semiconductor device according to the present embodiment can increase the carrier drift speed on the source side as compared with the conventional semiconductor device. As a result, the saturation current value can be increased.

FIG. 9 shows the result of determining the drain voltage dependency of the drain current by device simulation. In the figure, the solid line indicates the characteristics of the semiconductor device according to the present embodiment, the dotted line indicates the characteristics of the conventional semiconductor device shown in FIG. 18, and the dashed line indicates the characteristics of the conventional semiconductor device having no pocket structure. .

As shown in the figure, the saturation current value of the conventional semiconductor device shown in FIG. 18 is smaller than that of the conventional semiconductor device having no pocket structure. The saturation current value is higher than that. That is, according to the structure of the semiconductor device according to the present embodiment, the current driving capability can be increased as compared with any device. The reason why the semiconductor device according to the present embodiment can increase the saturation current value over the conventional semiconductor device having no pocket structure is that the pocket formed by ion-implanting the impurity of the opposite conductivity type as described above. Area 3
By forming 6, the effective doping concentration of the drain-side channel is lower than that of the uniform channel structure, and the electric field tends to increase on the source side.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

First, the LOCOS
(LOCal Oxidation of Silicon) method and STI (Shallow T
An element isolation region (not shown) for isolating elements formed on the silicon substrate 10 is formed by an element isolation technique such as a trench isolation method.

Next, if necessary, a well of a predetermined conductivity type is formed in a predetermined region. In the present embodiment, it is assumed that a P well 12 having a predetermined impurity concentration is formed in a region illustrated.

Next, a gate insulating film 14 having a thickness of about 3 nm is formed on the surface of the silicon substrate 10 by, for example, a thermal oxidation method.

Next, in the silicon substrate 10, for example, the acceleration energy is 30 keV and the dose is 2 × 10 ¹² cm.
^{As -2} , boron (B) ions are implanted to form a channel region 32 (FIG. 10A). The channel region 32 may be formed continuously with the formation of the P well 12, or the P well 12 and the channel region 32 may be formed after the formation of the gate insulating film 14.

Next, a phosphorus-doped polysilicon film having a thickness of about 50 nm is deposited on the entire surface by, eg, CVD.

Next, the polysilicon film is patterned by using the usual lithography technique and etching technique to form a gate electrode 16 made of the polysilicon film and having a gate length of 0.13 μm (FIG. 10B).

Next, using the gate electrode 16 as a mask, the acceleration energy is 5 keV and the dose is 1 × 10 ¹⁴
Arsenic (As) ions are implanted at cm ⁻² to form a source extension 20 and a drain extension 22 in the silicon substrate 10 (FIG. 10).
(C)).

Next, boron ions were implanted under the conditions of an acceleration energy of 10 keV and a dose of 6 × 10 ¹² cm ⁻² , with an angle of 45 ° inclined to the source side with respect to the surface of the silicon substrate 10 as an incident angle. An area 34 is formed. The pocket region 34 is formed only on the source side by the shadow effect of the gate electrode 16 (FIG. 11).
(A)).

Next, arsenic ions were implanted under the conditions of an acceleration energy of 5 keV and a dose of 1 × 10 ¹² cm ⁻² with an angle of 45 ° inclined to the drain side with respect to the surface of the silicon substrate 10 as an incident angle. A region 36 is formed (FIG. 11B). The pocket region 36 is formed only on the drain side due to the shadow effect of the gate electrode 16. Since the implanted arsenic ions compensate for the acceptor ions in the pocket region 36, the carrier concentration in the pocket region 36 is
2 has a relatively lower concentration than the central portion and the pocket region 34.

The effective carrier concentration of the pocket region 36 is desirably 1 × 10 ¹⁶ cm ⁻³ or more. It is desirable that the upper limit of the carrier concentration is appropriately adjusted in consideration of the above-described lateral electric field and drift speed, depending on a device structure to be manufactured, a scale, and the like.

Next, for example, a short annealing at 850 ° C. for 5 seconds is performed to activate the implanted impurities.

Next, a silicon oxide film is deposited on the entire surface by, for example, a CVD method and etched back to form a gate electrode 1.
The sidewall insulating film 18 is formed on the side wall of FIG.
1 (c)).

Next, using the gate electrode 16 and the side wall insulating film 18 as a mask,
Arsenic ions are implanted at a keV and a dose of 2 × 10 ¹⁵ cm ⁻² to form diffusion layers 24 and 26.

Thus, a source region 28 composed of the source extension 20 and the diffusion layer 24 and a drain region 30 composed of the drain extension 22 and the diffusion layer 26 are formed (FIG. 12A).

Next, for example, a short annealing at 950 ° C. for 10 seconds is performed to activate the implanted impurities.

Next, for example, a silicide electrode 38 made of a TiSi ₂ film is formed on the gate electrode 16, the source region 28, and the drain region 30 by a normal salicide process (FIG. 12B).

Thus, the pocket region 36 on the drain side is formed.
Is the central portion of the channel region 32 and the pocket region 34
A semiconductor device having a pocket structure with a lower impurity concentration than the above can be manufactured.

As described above, according to the present embodiment, since the pocket region 36 on the drain side forms a pocket structure having a lower impurity concentration than the central portion of the channel region 32 and the pocket region 34, the threshold voltage roll-off is reduced. In addition to suppressing the current, the current driving capability can be improved.

[Second Embodiment] The semiconductor device and the method for fabricating the same according to a second embodiment of the present invention will be explained with reference to FIGS. The same components as those of the semiconductor device according to the first embodiment and the method of manufacturing the same are denoted by the same reference numerals, and description thereof will be omitted or simplified.

FIG. 13 is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 14 to 16 are process sectional views showing the method for fabricating the semiconductor device according to the present embodiment.

This embodiment shows an example in which the present invention is applied to a MOSFET formed on an SOI substrate. S
A semiconductor device formed on an OI substrate can easily improve element isolation characteristics and reduce junction capacitance as compared with a semiconductor device formed on a bulk substrate. Therefore,
The use of the SOI substrate is expected to contribute to the improvement of characteristics in a future semiconductor device which is further miniaturized in combination with the effect of the present invention.

First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

A buried insulating film 42 is formed on the silicon substrate 10. On the buried insulating film 42, S
An OI layer 44 is formed. The gate electrode 16 is formed on the SOI layer 44 with the gate insulating film 14 interposed therebetween. A side wall insulating film 18 is formed on the side wall of the gate electrode 16.

The silicon substrate 10 on both sides of the gate electrode 16
Inside, a source region 28 composed of the source extension 20 and the diffusion layer 24 and a drain extension 2
2 and a diffusion layer 26 are formed.

Between the source region 26 and the channel region 32, a pocket region 34 having the same conductivity type as that of the channel region 32 and having an impurity concentration higher than that of the channel region 32 is formed. On the other hand, between the drain region 30 and the channel region 32, the same conductivity type as that of the channel region 32 and the channel region 3
2 and a pocket region 36 having a lower impurity concentration than the pocket region 34 is formed.

As described above, in the semiconductor device according to the present embodiment, in the SOI layer 44 formed on the silicon substrate 10 with the buried insulating film 42 interposed therebetween, the pocket region 36 on the drain side is formed in the central portion of the channel region 32. Having a pocket structure having an impurity concentration lower than that of pocket region 34.
The feature is that an OSFET is formed.

By configuring the semiconductor device in this manner, the advantages of using an SOI substrate, such as improvement of element isolation characteristics and reduction of junction capacitance, can be obtained, and current drive capability can be improved while suppressing threshold voltage roll-off. can do.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

First, for example, SIMOX (Separation by
The buried insulating film 42 is formed in the silicon substrate 10 by the IMplanted OXygen method, and the SOI layer 44 insulated from other regions of the silicon substrate 10 via the buried insulating film 42 is formed. In this manner, the SOI layer 44 in which the SOI layer 44 is formed on the silicon substrate 10 via the buried insulating film 42
An I substrate is prepared (FIG. 14A). In addition, SIMOX
The SOI substrate may be formed not only by the method but also by a bonded SOI technique or another technique.

Next, the gate insulating film 14 and the channel region 32 are formed on the SOI layer 44 in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS.
(FIG. 14B), the gate electrode 16 (FIG. 14C),
Source / drain extensions 20, 22 (FIG. 15)
(A)), pocket region 34 (FIG. 15 (b)), pocket region 36 (FIG. 15 (c)), sidewall insulating film 1
8 (FIG. 16A), diffusion layers 24 and 26 (FIG.
(B)), the silicide electrode 38 (FIG. 16 (c)) and the like are sequentially formed to form the pocket region 36 on the drain side.
Is the central portion of the channel region 32 and the pocket region 34
A semiconductor device having a pocket structure with a lower impurity concentration than the above is formed.

As described above, according to the present embodiment, the SOI
Since the present invention is applied to a MOSFET formed on a substrate, the advantages of using an SOI substrate, such as improvement of element isolation characteristics and reduction of junction capacitance, are obtained, and current drive capability is improved while suppressing threshold voltage roll-off. can do.

[Modified Embodiment] The present invention is not limited to the above-described embodiment, and various modifications can be made.

For example, in the above embodiment, the case where the present invention is applied to a MOSFET having a source / drain diffusion layer having a so-called extension S / D structure has been described. Semiconductor device with LDD (Lightly Doped
The present invention can be similarly applied to a semiconductor device having a drain structure and other semiconductor devices having a diffusion layer structure. That is, in the above-described method for manufacturing a semiconductor device, the step of forming the source / drain extensions may be omitted or the dose may be reduced.

In the above embodiment, the n-type MOSFET
Although the case of (1) has been described as an example, the present invention can be similarly applied to a p-type MOSFET.

[0086]

As described above, according to the present invention, a channel region of the first conductivity type formed on a semiconductor substrate, a source region and a drain region of a second conductivity type separated from each other by the channel region, A first region formed between the region and the source region and having a higher carrier concentration than the channel region;
A second pocket region of the first conductivity type formed between the first pocket region of the conductivity type, the channel region and the drain region and having a lower carrier concentration than the channel region, and an insulating film on the channel region; Since the MOSFET having the gate electrode formed by the above method is formed, the threshold voltage roll-off can be suppressed by the first pocket region, and the current driving capability can be improved by the second pocket region. Therefore, the short channel effect can be suppressed without sacrificing the current driving capability of the MOSFET.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a graph showing an impurity concentration distribution along a channel direction in the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a graph showing an impurity concentration distribution along a channel direction in a conventional semiconductor device.

FIG. 4 is a graph showing a result of a potential distribution on an interface between a gate insulating film and a silicon substrate obtained by device simulation.

FIG. 5 is a graph showing the result of determining the gate length dependence of off-state current by device simulation.

FIG. 6 is a graph showing the result of determining the drain voltage dependence of the threshold voltage by device simulation.

FIG. 7 is a graph showing a result of obtaining a lateral electric field in a channel by device simulation.

FIG. 8 is a graph showing a result obtained by calculating a drift speed of carriers in a channel region by device simulation.

FIG. 9 is a graph showing the result of determining the drain voltage dependence of the drain current by device simulation.

FIG. 10 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 11 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 13 is a schematic sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 14 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 15 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 16 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 17 is a graph showing a result obtained by device simulation of a potential distribution on an interface between a gate insulating film and a silicon substrate in a conventional semiconductor device having no pocket structure.

FIG. 18 is a schematic sectional view showing the structure of a conventional semiconductor device having a pocket structure.

FIG. 19 is a graph showing a result obtained by device simulation of a potential distribution on an interface between a gate insulating film and a silicon substrate in a conventional semiconductor device having a pocket structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12 ... P-type well 14 ... Gate insulating film 16 ... Gate electrode 18 ... Side wall insulating film 20 ... Source extension 22 ... Drain extension 24 ... Diffusion layer 26 ... Diffusion layer 28 ... Source region 30 ... Drain region 32 ... Channel region 34 pocket region (source side) 36 pocket region (drain side) 38 silicide electrode 42 embedded insulating film 44 SOI layer 100 silicon substrate 102 gate insulating film 104 gate electrode 106 sidewall insulating film 108 ... source extension 110 ... drain extension 112 ... diffusion layer 114 ... diffusion layer 116 ... source region 118 ... drain region 120 ... channel region 122 ... pocket region 124 ... pocket region

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F040 DA12 DA18 EB12 EC07 EE05 EF02 EH02 EM01 EM02 EM03 FA04 FA19 FC13 5F110 AA02 CC02 DD05 DD24 EE09 EE32 FF02 GG02 GG34 GG36 GG52 HJ13 HM15

Claims (7)

[Claims] A first conductivity type channel region formed on a semiconductor substrate; a second conductivity type source region and a drain region formed on the semiconductor substrate and separated from each other by the channel region; A first pocket region of the first conductivity type, which is formed on the semiconductor substrate and has a higher carrier concentration than the channel region, between the channel region and the drain region. A second pocket region of the first conductivity type formed on the substrate and having a lower carrier concentration than the channel region; and a gate electrode formed on the channel region via an insulating film. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the source region includes a first diffusion layer of a second conductivity type provided adjacent to the first pocket region, and the first diffusion layer. A second diffusion layer having a higher impurity concentration than the first diffusion layer and a deeper diffusion layer, the second drain region being provided adjacent to the second pocket region. A semiconductor, comprising: a third diffusion layer of a conductivity type; and a fourth diffusion layer provided adjacent to the third diffusion layer and having a higher impurity concentration and a higher depth than the third diffusion layer. apparatus. 3. The semiconductor device according to claim 1, wherein the semiconductor substrate is an SOI substrate, and the channel region, the source region, the drain region, the first pocket region, and the second pocket region. Is the SOI
A semiconductor device formed in an SOI layer of a substrate. 4. A step of introducing a first impurity of a first conductivity type into a semiconductor substrate to form a channel region of the first conductivity type, and forming a gate electrode on the semiconductor substrate via an insulating film. And introducing a second impurity of the first conductivity type into the semiconductor substrate on one side of the gate electrode, and the first impurity of the first conductivity type having a higher carrier concentration than the channel region. Forming a pocket region; and forming a second region in the semiconductor substrate on the other side of the gate electrode.
Introducing a third impurity of the conductivity type to form a second pocket region of the first conductivity type having a lower carrier concentration than the channel region; and forming the second pocket region in the semiconductor substrate on both sides of the gate electrode. A second conductivity type fourth impurity is introduced, and a second conductivity type source region adjacent to the channel layer via the first pocket region; and a channel region adjacent to the channel layer via the second pocket region. Forming a second conductivity type drain region. 5. A step of introducing a first impurity of a first conductivity type into a semiconductor substrate to form a channel region of the first conductivity type, and forming a gate electrode on the semiconductor substrate via an insulating film. And a second step in the semiconductor substrate using the gate electrode as a mask.
Introducing a second impurity of a conductivity type to form a source region and a drain region of the second conductivity type separated from each other by the channel region; and forming a source region and a drain region of the second conductivity type in a region between the source region and the channel region. A step of introducing a third impurity of a first conductivity type to form a first pocket region of the first conductivity type having a carrier concentration higher than that of the channel region; and forming a first pocket region of the first conductivity type between the drain region and the channel region. Introducing a fourth impurity of the second conductivity type into a region to form a second pocket region of the first conductivity type having a lower carrier concentration than the channel region. Manufacturing method. 6. The method for manufacturing a semiconductor device according to claim 4, wherein, in the step of forming the first pocket region, the third pocket region is formed in a direction inclined toward the source region using the gate electrode as a mask. Forming the first pocket region by introducing an impurity of (1). 7. The method for manufacturing a semiconductor device according to claim 4, wherein in the step of forming the second pocket region, the gate electrode is used as a mask to tilt toward the drain region. Forming the second pocket region by introducing the fourth impurity from a predetermined direction.