KR100257709B1 - Method for manufacturing transistor soi device - Google Patents

Abstract

PURPOSE: A method for manufacturing a transistor of an SOI(silicon on insulator) device is provided to remove a lateral conduction by increasing a threshold voltage of a side channel. CONSTITUTION: A buried oxide layer(13) is formed on a semiconductor substrate(11). An upper silicon layer(15) is formed on the buried oxide layer(13), thereby forming an SOI substrate. A pad oxide layer and a nitride layer are formed on the SOI substrate. A photoresist film pattern is formed on the nitride layer by performing an etching process. Then, the photoresist film pattern is removed, and a field oxide layer(23) is formed in a thickness of 2500 to 3500Å by oxidizing the upper silicon layer(15). After removing the pad insulating layer pattern, a gate electrode is formed.

Description

S. Oh. Method of manufacturing transistor of device

The present invention is S. O. I. The present invention relates to a method of manufacturing a transistor of a device, and in particular, by eliminating side conduction of a transistor so that the transistor can operate stably, a peripheral circuit of a memory device, a high-speed low voltage circuit, a pin-shaped semiconductor device and an M.M.L. (merged memory logic, hereinafter referred to as MML). A technique for forming a semiconductor.

The SOI device is a method of forming a silicon oxide film that insulates a semiconductor substrate, an actual semiconductor substrate, for example, a single crystal silicon layer is formed on the semiconductor substrate, and a semiconductor device on top of the single crystal silicon layer. The separation technology is easy and the electrical characteristics of the device are excellent, and it has been widely studied.

In general, the SOI device is bonded by two wafers and then thinned by one wafer (Bond & Etch, BE hereafter), and then buried by heat treatment after oxygen implant (oxigen implasted) on the semiconductor substrate. The Separation By IMplated Oxygen (hereinafter referred to as SIMOX) method of forming a buried oxide and a silicon film is used.

In the SOI structure MOSFET, a bulk MOS field effect transistor (hereinafter referred to as MOSFET) is a four-terminal structure of a gate, a source, a drain, and a semiconductor substrate. Since there is no need for contacts to and associated wiring, the three-terminal structure of the gate, source, and drain can be used to reduce the size of the chip.

In addition, CMOS does not form a well, and since the active regions of each MOSFET are isolated from each other, latch-up can be prevented.

In the SOI device fabricated in the thin silicon thin film, since the source / drain junction is formed over the entire film thickness, there is almost no area junction capacitance of the source / drain, and only the junction capacitance by the perimeter exist. Thus, SOI devices have high speed and low power characteristics compared to bulk MOSFETs.

In addition, the SOI element is an overall IC. Reduces the capacitive coupling between the circuit elements of the IC and the latch-up of the CMOS circuit, and reduces chip size and increases packing density to increase overall circuit operating speed and increase parasitic capacitance and parasitic capacitance. It has the property of reducing chip size.

In addition, the SOI device has advantages such as reducing the hot electron effect, reducing the short channel effect, and the like.

However, in the SOI device, the thickness of the upper silicon layer of the SOI wafer must be as thin as 100 nm or less for the single crystal silicon device to have the above advantages. As described above, transistors fabricated using an SOI wafer with a thickness of the upper silicon layer may cause side-effects in terms of the side conduction from the user's point of view.

1 is a plan view showing a plan view of a transistor, and FIGS. 2A and 2B are cross-sectional views taken along line ⓐ-ⓐ and ⓑ-ⓑ of FIG. 1.

FIG. 1 illustrates that a gate electrode 100 is provided in an active region, and source / drain electrodes 300 and 200 are formed at left and right sides of the gate electrode 100.

FIG. 2A is a cross-sectional view illustrating a cross section taken along the cutting line ⓐ-ⓐ of FIG. 1, wherein the buried oxide film 35 is formed on the semiconductor substrate 31, and the upper silicon is formed on the buried oxide film 35. Form layer 35.

A pad oxide film (not shown) and a nitride film (not shown) are respectively formed on the upper silicon layer 35 at predetermined thicknesses.

Subsequently, the upper silicon layer 35 is exposed by the etching process using the device isolation mask, and the exposed upper silicon layer 35 is thermally oxidized to form the device isolation insulating layer 41.

Then, the nitride layer and the pad oxide layer are removed, and the gate oxide layer 43 and the polysilicon layer 45 are deposited to a predetermined thickness in the active region of the upper silicon layer 35. Then, the etching process using the gate electrode mask is performed. The polysilicon layer 45 and the gate oxide layer 43 are etched to form a gate electrode.

Next, source / drain junction regions 39 and 37 are formed by implanting a high concentration of impurity ions into the upper silicon layer 45 using the gate electrode and the device isolation insulating film 41 as a mask. (FIG. 2A)

FIG. 2B is a cross-sectional view taken along line ⓑ-ⓑ of FIG. 1, and is formed by the process of FIG. 2A.

Here, the parasitic channel 47 is formed on the side of the upper silicon layer due to the impurities present in the field oxide film before the main channel of the transistor is formed by the gate voltage, so that side conduction occurs, thereby increasing the leakage current of the transistor. There is a drawback to this. At this time, most of the impurities are precipitated in the field oxide film during the transistor fabrication process.

Thus, side conduction removal of transistors is essential for stable operation of transistor circuits fabricated using SOI wafers capable of high speed and low voltage.

Currently, a method mainly used to remove side conduction of a transistor is to increase the threshold voltage of the side channel by implanting ions into the interface between the field oxide film and the upper silicon layer. However, this method has difficulty in determining ion implantation energy and its effect is not clear.

In order to solve the problems of the prior art described above, in order to remove the side conduction of the transistor, by controlling the stress existing between the oxide film and the upper silicon layer, impurities injected into the upper silicon layer are diffused into the field oxide film and the buried oxide film. S.O.I. to remove side conduction by increasing the threshold voltage of the side channel by preventing impurities and accumulating impurities at the interface. It is an object of the present invention to provide a method for manufacturing a transistor of a device.

1 shows a semiconductor standard process and S.O.I. Silicon On Insulator (hereinafter referred to as SOI) S.O.I. fabricated using a wafer. Transistor top view of the device.

2A and 2B illustrate S.O.I. Sectional drawing which shows the transistor manufacturing method of a device.

3A-3D illustrate S.O.I. according to an embodiment of the present invention. Sectional drawing which shows the transistor manufacturing method of a device.

4 is S. O. I. according to the present invention. Graph showing the current-voltage characteristics of the device.

<Description of Symbols for Major Parts of Drawings>

11,31: semiconductor substrate 13,33: buried oxide film

15,35: upper silicon layer 17: pad oxide film

19 nitride film 21 photosensitive film pattern

23, 41: device isolation insulating film 25: impurities accumulated at the interface

27,43 gate oxide film 29,45 polysilicon film

39 source electrode 37 before drain

47: side channel

S. O. I. according to the present invention to achieve the above object. The transistor manufacturing method of the device,

Forming a pad insulating film pattern exposing the device isolation region of the SOI wafer in which the buried oxide film and the upper silicon layer are formed on the semiconductor substrate;

Performing a thermal oxidation process on the exposed upper silicon layer, wherein the buried oxide film has a compressive stress and the upper silicon layer has a tensile stress to form a device isolation insulating film;

And removing the pad insulating layer pattern and forming a gate electrode.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A-3E illustrate S.O.I. according to an embodiment of the present invention. It is sectional drawing which shows the transistor manufacturing method of an element, Comprising: It is process sectional drawing cut along the ⓑ-ⓑ cutting surface of FIG.

First, an SOI substrate is formed by forming a buried oxide film 13 on the semiconductor substrate 11 at a thickness of about 800 to 1200 GPa, and forming an upper silicon layer 15 on the buried oxide film 13. (FIG. 3A)

The pad oxide layer 17 and the nitride layer 19 are formed on the SOI substrate, respectively, and the photoresist layer pattern 21 is formed on the nitride layer 19. In this case, the photoresist pattern 21 is formed by an etching process using an element isolation mask. (FIG. 3B)

Thereafter, the photoresist film pattern 21 is removed, and the device isolation insulating film 23 is oxidized by oxidizing the upper silicon layer 15 using the pad oxide film 17 and the nitride film 19 as an oxide barrier by a thermal oxidation process. It is formed to a thickness of about 2500 to 3500 kPa.

In this case, the thermal oxidation process is performed in a dry oxygen atmosphere at a temperature of 900 to 1300 ° C. for 3 to 5 hours so that the device isolation insulating film 23 directly contacts the buried oxide film 13. The stress of the upper silicon layer 15 due to the stress of the oxide film 13 is adjusted by adjusting the thickness of the oxide film 13 or the growth condition of the device isolation insulating film 23 so that the stress is compressive stress, that is, compressive stress. Have a tensile stress.

In addition, when the buried oxide film 13 has a compressive strain, boron diffusion tends to be suppressed, and thus, boron may be accumulated at an interface between the upper silicon layer 15 and the buried oxide film 13. Therefore, the diffusion of impurities in the upper silicon layer 15 into the buried oxide layer 13 may be prevented, and impurities 25 may be formed at the interface between the upper silicon layer 15 and the buried oxide layer 13. Can be scaled. At this time, the amount of stress existing in the buried oxide film 13 may be at least 1 × 10 ¹⁰ dyne / cm 2 or more.

In this case, when the concentration of the impurity 25 increases at the interface between the buried oxide film 13 and the upper silicon layer 15, the threshold voltage of the side channel is increased to remove leakage current due to side conduction in the SOI device. (FIG. 3C)

Next, the pad oxide film 17 and the nitride film 19 are removed, and the gate electrode formed of a stacked structure of the gate oxide film 27 and the polysilicon film 29 for the gate electrode on the upper silicon layer 15. To form. (FIG. 3D, FIG. 3E)

" 는 측면전도가 존재하는 경우를 도시하고, "

"는 측면전도가 제거된 경우를 도시한다.4 is a graph showing the current-voltage characteristics of an SOI device with side conduction removed.

"Shows the case of lateral conduction, and"

Shows the case where the side conduction is removed.

Another embodiment of the present invention, the thickness control of the buried oxide film 13, the process conditions such as time, temperature, atmosphere during the device isolation insulating film formation process, the stress control of the buried oxide film and the upper silicon layer during the SOI wafer manufacturing and pads By controlling the thickness of the oxide film and the nitride film by controlling the stress present at the interface between the buried oxide film and the silicon thin film to produce a device without side conduction.

As described above, S.I.I. according to the present invention. In the transistor fabrication method of the device, a thin film type SOI transistor without side conduction is produced by varying the thickness of the buried oxide film and the conditions of forming the device isolation insulating film. It can work.

Claims (5)

Forming a pad insulating film pattern exposing the device isolation region of the SOI wafer in which the buried oxide film and the upper silicon layer are formed on the semiconductor substrate; Thermally oxidizing the exposed upper silicon layer, wherein the buried oxide film has a compressive stress and the upper silicon layer has a tensile stress to form a device isolation insulating film; And removing the pad insulating film pattern and forming a gate electrode. Method for manufacturing a transistor of the device. The method of claim 1, The buried oxide film is formed to a thickness of about 800 ~ 1200 Å S. O. I. Method for manufacturing a transistor of the device. The method of claim 1, The thermal oxidation process is performed in a dry oxygen atmosphere at a temperature of 900 to 1300 ° C. for about 3 to 5 hours. Method for manufacturing a transistor of the device. The method of claim 1, The device isolation insulating film is formed to a thickness of about 2500 ~ 3500 에스 S. O. I. Method for manufacturing a transistor of the device. The method of claim 1, S. O. I., characterized in that to accumulate boron impurities at the interface between the buried oxide film and the upper silicon layer. Method for manufacturing a transistor of the device.

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