KR20010063265A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR20010063265A KR20010063265A KR1019990060295A KR19990060295A KR20010063265A KR 20010063265 A KR20010063265 A KR 20010063265A KR 1019990060295 A KR1019990060295 A KR 1019990060295A KR 19990060295 A KR19990060295 A KR 19990060295A KR 20010063265 A KR20010063265 A KR 20010063265A
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- Prior art keywords
- film
- forming
- gate electrode
- thermal oxide
- contact hole
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 46
- 125000006850 spacer group Chemical group 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 14
- 238000005498 polishing Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 2
- BJAARRARQJZURR-UHFFFAOYSA-N trimethylazanium;hydroxide Chemical compound O.CN(C)C BJAARRARQJZURR-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 claims 1
- 238000007598 dipping method Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 6
- 239000005360 phosphosilicate glass Substances 0.000 abstract 4
- 238000000206 photolithography Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히, 미세 선폭의 게이트 전극을 안정되게 형성시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of stably forming a gate electrode having a fine line width.
반도체 소자의 집적도가 증가됨에 따라, 회로 내에 구비되는 패턴들의 크기가 감소되고 있고, 특히, 게이트 전극의 미세화가 요구되고 있다. 여기서, 상기 게이트 전극의 미세화는 게이트 전극의 선폭이 감소됨을 의미하는데, 통상의 반도체 제조 공정에서는 포토리소그라피(Photolithography) 공정시에 보다 짧은 파장의 광원을 사용하는 것에 의해 상기 게이트 전극의 미세화를 달성하고 있다.As the degree of integration of semiconductor devices is increased, the size of the patterns included in the circuit is reduced, and in particular, the miniaturization of the gate electrode is required. Here, the miniaturization of the gate electrode means that the line width of the gate electrode is reduced. In the conventional semiconductor manufacturing process, the miniaturization of the gate electrode is achieved by using a light source having a shorter wavelength at the time of photolithography. have.
그런데, 상기 방법은 노광 장비의 분해능에 따라 미세 폭의 패턴을 얻는 것이므로, 장비 능력 이하의 패턴 크기는 얻을 수 없고, 특히, 장비 투자 비용이 증가된다는 단점이 있다.However, since the method is to obtain a pattern having a fine width according to the resolution of the exposure equipment, a pattern size below the equipment capacity cannot be obtained, and in particular, the equipment investment cost is increased.
따라서, 상기한 방법 이외에 미세 패턴을 형성하기 위한 다양한 기술들이 제안되고 있으며, 한 예로서, 레지스트 패턴의 에슁(ashing)을 이용하는 기술이 최근의 반도체 제조 공정에 적용되고 있다.Accordingly, various techniques for forming a fine pattern in addition to the above-described method have been proposed, and as an example, a technique using ashing of a resist pattern has been applied to a recent semiconductor manufacturing process.
도 1a 내지 도 1c는 레지스트 패턴의 에슁을 이용한 종래 기술에 따른 미세 선폭의 게이트 전극 형성방법을 설명하기 위한 각 공정별 단면도이다.1A to 1C are cross-sectional views of respective processes for explaining a method of forming a gate electrode having a fine line width according to the prior art using etching of a resist pattern.
도 1a에 도시된 바와 같이, 반도체 기판(1) 상에 게이트 전극용 도전막(2)을 형성하고, 상기 게이트 전극용 도전막(2) 상에 공지된 포토리소그라피 공정으로 레지스트 패턴(3)을 형성한다. 그런다음, 상기 레지스트 패턴(3)에 대하여 O2가스를 이용한 에슁 공정을 수행하여, 도 1b에 도시된 바와 같이, 전 공정에서 얻어진 레지스트 패턴(3) 보다는 축소된 크기를 갖는 레지스트 패턴(3a)을 형성하고, 그리고나서, 도 1c에 도시된 바와 같이, 축소된 레지스트 패턴(3a)을 이용한 식각 공정을통해 그 하부의 상기 게이트 전극용 도전막(2)을 식각함으로써, 장비 능력 이하의 크기를 갖는 미세 선폭의 게이트 전극(2a)를 형성한다.As shown in FIG. 1A, a conductive film 2 for a gate electrode is formed on a semiconductor substrate 1, and a resist pattern 3 is formed on the gate electrode conductive film 2 by a known photolithography process. Form. Then, an etching process using an O 2 gas is performed on the resist pattern 3, and as shown in FIG. 1B, the resist pattern 3a having a smaller size than the resist pattern 3 obtained in the previous process is shown. And then, as shown in FIG. 1C, by etching the lower portion of the conductive film 2 for the gate electrode through an etching process using the reduced resist pattern 3a, the size below the capability of the device is increased. A gate electrode 2a having a fine line width is formed.
그러나, 상기 레지스트 패턴의 에슁을 이용한 게이트 전극 형성방법은 장비 능력 이하의 선폭을 갖는 게이트 전극을 비교적 용이하게 얻을 수 있다는 장점은 있으나, 에슁에 의해 얻어지는 레지스트 패턴의 폭의 제어가 어렵다는 문제점이 있고, 특히, 도 1b에 도시된 바와 같이, 레지스트 패턴(3a)의 두께가 얇아짐에 따라, 상기 레지스트 패턴(3a)이 식각 장벽으로서의 기능을 제대로 수행하지 못함으로써, 후속의 식각 공정이 안정하지 못한 문제점이 있다.However, the gate electrode forming method using the etching of the resist pattern has the advantage that it is relatively easy to obtain a gate electrode having a line width of less than the equipment capacity, there is a problem that it is difficult to control the width of the resist pattern obtained by etching. In particular, as shown in FIG. 1B, as the thickness of the resist pattern 3a becomes thin, the resist pattern 3a does not function properly as an etching barrier, and thus, subsequent etching processes are not stable. There is this.
따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, 미세 선폭의 게이트 전극을 안정되게 형성시킬 수 있는 반도체 소자의 제조방법을 제공하는데, 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of stably forming a gate electrode having a fine line width.
도 1a 내지 도 1c는 종래 기술에 따른 미세 선폭의 게이트 전극 형성방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views illustrating a method for forming a gate electrode having a fine line width according to the prior art.
도 2a 내지 도 2h는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 각 공정별 단면도.2A to 2H are cross-sectional views of respective processes for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 반도체 기판 12 : 제1열산화막11 semiconductor substrate 12 first thermal oxide film
13 : 희생막 14 : 소오스/드레인 영역13: sacrificial film 14: source / drain region
15 : 절연막 16 : 콘택홀15 insulating film 16 contact hole
17 : PSG막 스페이서 18 : 저도핑 드레인 영역17 PSG film spacer 18 low doping drain region
19 : 제2열산화막 20 : 절연막 스페이서19 second thermal oxide film 20 insulating film spacer
21 : 게이트 산화막 22 : 게이트 전극21: gate oxide film 22: gate electrode
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은, 일측 표면에 제1열산화막이 형성된 반도체 기판을 제공하는 단계; 상기 제1열산화막 상에 게이트 전극 형성 영역을 한정하는 희생막 패턴을 형성하는 단계; 상기 희생막 패턴 양측의 상기 반도체 기판 부분에 소오스/드레인 영역을 형성하는 단계; 상기 제1열산화막 상에 상기 희생막 패턴을 완전히 덮을 정도의 충분한 두께로 절연막을 형성하는 단계; 상기 희생막 패턴이 노출되도록, 상기 절연막을 연마하는 단계; 상기 반도체 기판을 노출시키는 콘택홀이 형성되도록, 노출된 희생막 패턴과그 하부의 제1열산화막 부분을 제거하는 단계; 상기 콘택홀의 양 측벽에 PSG막 스페이서를 형성하는 단계; 상기 PSG막 스페이서에 함유된 불순물이 확산되는 것에 의해 상기 PSG막 스페이서와 접촉하고 있는 반도체 기판 부분에 저도핑 드레인 영역이 형성되도록, 상기 결과물을 열처리하는 단계; 상기 PSG막 스페이서를 제거하는 단계; 노출된 반도체 기판 부분에 제2열산화막을 형성하는 단계; 상기 콘택홀의 양 측벽에 절연막 스페이서를 형성하는 단계; 게이트 전극이 형성될 반도체 기판이 노출되도록, 상기 절연막 스페이서 사이의 상기 제2열산화막 부분을 제거하는 단계; 노출된 반도체 기판 부분에 게이트 산화막을 형성하는 단계; 및 상기 콘택홀 내부 및 상기 절연막 상에 게이트 전극을 형성하는 단계를 포함한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of: providing a semiconductor substrate having a first thermal oxide film formed on one surface; Forming a sacrificial layer pattern defining a gate electrode formation region on the first thermal oxide layer; Forming source / drain regions on portions of the semiconductor substrate on both sides of the sacrificial layer pattern; Forming an insulating film on the first thermal oxide film to a thickness sufficient to completely cover the sacrificial film pattern; Polishing the insulating layer to expose the sacrificial layer pattern; Removing the exposed sacrificial layer pattern and a portion of the first thermal oxide layer under the exposed sacrificial layer so as to form a contact hole exposing the semiconductor substrate; Forming PSG film spacers on both sidewalls of the contact hole; Heat-treating the resultant so that a low doping drain region is formed in a portion of the semiconductor substrate in contact with the PSG film spacer by diffusion of impurities contained in the PSG film spacer; Removing the PSG film spacer; Forming a second thermal oxide film on the exposed portion of the semiconductor substrate; Forming insulating film spacers on both sidewalls of the contact hole; Removing the second thermal oxide film portion between the insulating film spacers so that the semiconductor substrate on which the gate electrode is to be formed is exposed; Forming a gate oxide film on the exposed portion of the semiconductor substrate; And forming a gate electrode in the contact hole and on the insulating layer.
본 발명에 따르면, 절연막 스페이서의 두께만을 조절함으로써, 선폭 제어가 용이한 미세 선폭의 게이트 전극을 형성할 수 있다.According to the present invention, by controlling only the thickness of the insulating film spacer, it is possible to form a gate electrode having a fine line width with easy line width control.
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2h는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다.2A to 2H are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판(11)을 마련하고, 상기 반도체 기판(1)의 일측 표면을 열산화시켜, 50 내지 200Å 정도의 제1열산화막(12)을 형성한다. 그런다음, 상기 제1열산화막(12) 상에 희생막(13), 예를들어, 폴리실리콘막을 1,500 내지 3,000Å 두께로 증착한다.First, as illustrated in FIG. 2A, a semiconductor substrate 11 is provided, and one surface of the semiconductor substrate 1 is thermally oxidized to form a first thermal oxide film 12 having a thickness of about 50 to about 200 kPa. Then, a sacrificial film 13, for example, a polysilicon film is deposited on the first thermal oxide film 12 to a thickness of 1,500 to 3,000 Å.
그 다음, 도 2b에 도시된 바와 같이, 게이트 전극이 형성될 영역을 한정하기위하여, 공지된 포토리소그라피 공정을 통해 상기 희생막(13) 상에 레지스트 패턴(도시안됨)을 형성하고, 이어서, 상기 레지스트 패턴을 마스크로하는 식각 공정을 통해 상기 희생막을 식각하여 희생막 패턴(13a)을 형성한다. 그런다음, 식각 마스크로 사용된 레지스트 패턴을 제거한다.Next, as shown in FIG. 2B, a resist pattern (not shown) is formed on the sacrificial layer 13 through a known photolithography process to define a region in which the gate electrode is to be formed. The sacrificial layer is etched through an etching process using a resist pattern as a mask to form the sacrificial layer pattern 13a. Then, the resist pattern used as the etching mask is removed.
다음으로, 도 2c에 도시된 바와 같이, 상기 결과물에 소정 불순물, 예를들어, 비소(As)를 고농도로 이온주입하여 희생막 패턴(13a) 양측의 반도체 기판 부분에 소오스/드레인 영역(14)을 형성하고, 그런다음, 상기 제1열산화막(12) 상에 상기 희생막 패턴(13a)을 완전히 덮을 수 있을 정도의 충분한 두께, 예를들어, 3,000 내지 5,000Å 두께로 절연막(15)을 증착한다.Next, as shown in FIG. 2C, a predetermined impurity, for example, arsenic (As) is implanted into the resultant at a high concentration, so that the source / drain regions 14 are formed on the semiconductor substrate portions on both sides of the sacrificial film pattern 13a. Then, the insulating film 15 is deposited to a thickness sufficient to completely cover the sacrificial film pattern 13a on the first thermal oxide film 12, for example, 3,000 to 5,000 kPa. do.
이어서, 도 2d에 도시된 바와 같이, 희생막 패턴이 노출되도록, 상기 희생막 패턴을 연마정지층으로 이용해서 화학적기계연마(Chemical Mechanical Polishing) 공정으로 절연막(15)을 연마하고, 그런다음, 게이트 전극이 형성될 반도체 기판 부분을 노출시키는 콘택홀(16)이 형성되도록, 상기 결과물을 TMAH(Trimethyl Ammonia Hydroxide) 용액에 침적시켜 노출된 희생막 패턴을 제거하고, 연이어서, 상기 결과물을 희석된 HF 용액에 재차 침적시켜, 상기 희생막 패턴의 제거로 인하여 노출된 제1열산화막 부분을 제거한다. 여기서, 상기 희생막 패턴의 제거는 TMAH 용액을 이용한 습식 식각 공정 대신에, SF6가스를 베이스로하는 플라즈마 식각 공정으로 수행하는 것도 가능하다.Subsequently, as shown in FIG. 2D, the insulating film 15 is polished by a chemical mechanical polishing process using the sacrificial film pattern as the polishing stop layer to expose the sacrificial film pattern, and then the gate The resulting product was deposited in a Trimethyl Ammonia Hydroxide (TMAH) solution to remove the exposed sacrificial layer pattern so as to form a contact hole 16 exposing a portion of the semiconductor substrate on which the electrode is to be formed, followed by diluting the resulting HF. By depositing again in the solution, the portion of the first thermal oxide layer exposed due to the removal of the sacrificial layer pattern is removed. Here, the removal of the sacrificial layer pattern may be performed by a plasma etching process based on SF 6 gas instead of a wet etching process using a TMAH solution.
계속해서, 도 2e에 도시된 바와 같이, 상기 결과물 상에 PSG막을 증착하고,이어서, 상기 PSG막을 에치백하여 콘택홀(16)의 양 측벽에 PSG막 스페이서(17)를 형성한다. 그런다음, 상기 결과물에 대한 열처리를 수행하여 상기 PSG막 스페이서(17)에 함유된 P 이온을 상기 PSG막 스페이서(17)와 접촉하고 있는 반도체 기판 부분으로 확산시켜, 그 부분에 저도핑 드레인 영역(18)을 형성한다.Subsequently, as shown in FIG. 2E, a PSG film is deposited on the resultant, and then the PSG film is etched back to form PSG film spacers 17 on both sidewalls of the contact hole 16. Then, heat treatment is performed on the resultant to diffuse P ions contained in the PSG film spacer 17 to a portion of the semiconductor substrate that is in contact with the PSG film spacer 17, thereby to form a low doping drain region ( 18).
여기서, 상기 PSG막 스페이서(17)의 폭은 상기 저도핑 드레인 영역(18)의 접합 길이를 한정하게 되므로, 상기 PSG막은 200 내지 500Å 두께로 증착함이 바람직하다. 또한, 저도핑 드레인 영역(18)을 형성하기 위한 열처리는 N2또는 O2분위기 및 700 내지 1,000℃에서 20 내지 60분 동안 수행하거나, 또는, 급속열처리인 경우에는 N2또는 O2분위기 및 800 내지 1,100℃에서 30 내지 60초 동안 수행한다.Here, the width of the PSG film spacer 17 is limited to the junction length of the low-doped drain region 18, the PSG film is preferably deposited to a thickness of 200 to 500 200. In addition, heat treatment for forming the low-doped drain region 18 is performed for 20 to 60 minutes in an N 2 or O 2 atmosphere and 700 to 1,000 ° C., or in an N 2 or O 2 atmosphere and 800 for rapid heat treatment. At 1,100 ° C. for 30-60 seconds.
다음으로, 도 2f에 도시된 바와 같이, 희석된 HF 용액에 상기 결과물을 침적시켜 PSG막 스페이서를 제거하고, 이 결과로 노출된 반도체 기판 부분을 재차 열산화시켜, 이 부분에 제2열산화막(19)을 형성한다. 그런다음, 콘택홀(16) 및 절연막(15) 상에 다른 절연막을 증착한 후, 상기 절연막을 식각하여 상기 콘택홀(16)의 양 측벽에 절연막 스페이서(20)을 형성한다. 여기서, 상기 절연막 스페이서(20)은 이전 단계에서의 PSG막 스페이서의 폭 보다 30 내지 70Å, 바람직하게는, 50Å 정도 짧은 폭을 갖도록 형성시킴으로써, 후속에서 형성될 게이트 전극이 저도핑 드레인 영역(18)과 오버랩되도록 한다.Next, as shown in FIG. 2F, the resultant is deposited in a diluted HF solution to remove the PSG film spacer, and as a result, the exposed portion of the semiconductor substrate is thermally oxidized again. 19). Thereafter, another insulating film is deposited on the contact hole 16 and the insulating film 15, and then the insulating film is etched to form insulating film spacers 20 on both sidewalls of the contact hole 16. Here, the insulating film spacer 20 is formed to have a width of 30 to 70 kHz, preferably about 50 kHz shorter than the width of the PSG film spacer in the previous step, so that the gate electrode to be formed subsequently has a low doping drain region 18. To overlap.
그 다음, 도 2g에 도시된 바와 같이, 상기 결과물에 대한 습식 세정을 수행하여 게이트 전극이 형성될 부분, 즉, 콘택홀(16)의 저면에 형성된 제2열산화막을제거하고, 재차, 이 부분에 게이트 산화막(21)을 형성한다. 여기서, 상기 게이트 산화막(21)은 실리콘 산화막, 알루미늄 산화막 또는 탄탈륨 산화막 중에서 선택되는 하나의 막으로 형성하거나, 혹은 이들 산화막의 혼합 막으로 형성하며, 그 유효 두께는 20 내지 100Å이 되도록 함이 바람직하다.Then, as illustrated in FIG. 2G, the wet cleaning of the resultant is performed to remove the portion where the gate electrode is to be formed, that is, the second thermal oxide film formed on the bottom surface of the contact hole 16. A gate oxide film 21 is formed in this. Here, the gate oxide film 21 is formed of one film selected from a silicon oxide film, an aluminum oxide film, or a tantalum oxide film, or a mixed film of these oxide films, and the effective thickness thereof is preferably set to 20 to 100 GPa. .
다음으로, 도 2h에 도시된 바와 같이, 콘택홀이 완전히 매립될 정도의 충분한 두께로 절연막(15) 상에 게이트 전극용 도전막을 증착하고, 상기 게이트 전극용 도전막을 공지된 포토리소그라피 공정 및 식각 공정을 통해 패터닝하여 미세 선폭을 갖는 게이트 전극(22)을 형성한다. 여기서, 상기 게이트 전극용 도전막은 폴리실리콘막, 폴리실리콘막-게르마늄, 텅스텐, 또는 실리사이드막 중에서 선택되는 하나의 막으로 형성하거나, 혹은, 이들의 혼합 막으로 형성한다. 또한, 상기 게이트 전극(22)은 포토리소그라피 공정 및 식각 공정 대신에 화학적기계연마 공정으로 형성하는 것도 가능하다.Next, as shown in FIG. 2H, a conductive film for a gate electrode is deposited on the insulating film 15 to a thickness sufficient to completely fill the contact hole, and the conductive film for the gate electrode is a known photolithography process and an etching process. The gate electrode 22 having a fine line width is formed by patterning through the insulating film. The gate electrode conductive film may be formed of one film selected from polysilicon film, polysilicon film-germanium, tungsten, or silicide film, or a mixed film thereof. In addition, the gate electrode 22 may be formed by a chemical mechanical polishing process instead of a photolithography process and an etching process.
이후, 공지된 후속 공정을 수행하여 반도체 소자를 제조한다.Thereafter, a known subsequent process is performed to fabricate a semiconductor device.
본 발명에 따르면, 게이트 전극이 형성될 영역을 미리 한정한 후에, 절연막 스페이서를 이용하여 그 폭을 줄임으로써, 장비 능력 이하의 미세 선폭을 갖는 게이트 전극을 형성할 수 있고, 특히, 절연막 스페이서를 형성하기 위한 절연막의 두께만을 조절함으로써, 최종적으로 얻게 되는 게이트 전극의 폭을 안정되게 조절할 수 있다.According to the present invention, after defining the region in which the gate electrode is to be formed in advance, by reducing the width by using the insulating film spacer, it is possible to form a gate electrode having a fine line width of less than or equal to the equipment capacity, and in particular, to form the insulating film spacer. By controlling only the thickness of the insulating film for the purpose, the width of the gate electrode finally obtained can be stably adjusted.
이상에서와 같이, 본 발명은 장비 능력 이하의 미세 선폭을 갖는 게이트 전극을 매우 용이하게 형성시킬 수 있으며, 특히, 그 폭의 조절을 안정되게 수행할 수 있다. 따라서, 고집적 반도체 소자의 제조에 매우 유리하게 적용시킬 수 있다.As described above, the present invention can very easily form a gate electrode having a fine line width of less than the equipment capacity, in particular, it is possible to stably control the width. Therefore, it can be very advantageously applied to the production of highly integrated semiconductor devices.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
Claims (19)
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| KR100665829B1 (en) * | 2000-05-30 | 2007-01-09 | 삼성전자주식회사 | Gate structure of semiconductor devices |
| KR100973094B1 (en) * | 2003-10-01 | 2010-07-29 | 매그나칩 반도체 유한회사 | Method for forming gate of nonvolatile memory device |
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| JPH08186082A (en) * | 1994-12-28 | 1996-07-16 | Nec Corp | Manufacture of semiconductor device |
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| KR100665829B1 (en) * | 2000-05-30 | 2007-01-09 | 삼성전자주식회사 | Gate structure of semiconductor devices |
| KR100973094B1 (en) * | 2003-10-01 | 2010-07-29 | 매그나칩 반도체 유한회사 | Method for forming gate of nonvolatile memory device |
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